Merge "plat/arm: Use common build flag for using generic sp804 driver" into integration
diff --git a/Makefile b/Makefile
index 1b986c4..61593c1 100644
--- a/Makefile
+++ b/Makefile
@@ -1137,7 +1137,7 @@
# Add Secure Partition packages
ifeq (${NEED_SP_PKG},yes)
$(BUILD_PLAT)/sp_gen.mk: ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT}
- ${Q}${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT)
+ ${Q}${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT}
sp: $(SPTOOL) $(DTBS) $(BUILD_PLAT)/sp_gen.mk
${Q}$(SPTOOL) $(SPTOOL_ARGS)
@${ECHO_BLANK_LINE}
diff --git a/docs/about/contact.rst b/docs/about/contact.rst
index 9cb25ef..4440a37 100644
--- a/docs/about/contact.rst
+++ b/docs/about/contact.rst
@@ -24,12 +24,21 @@
You can see a `summary of all the lists`_ on the TrustedFirmware.org website.
+Open Tech Forum Call
+^^^^^^^^^^^^^^^^^^^^
+
+Every other week, we organize a call with all interested TF-A contributors.
+Anyone is welcome to join. This is an opportunity to discuss any technical
+topic within the community. More details can be found `here`_.
+
+.. _here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/
+
Issue Tracker
^^^^^^^^^^^^^
-Specific issues may be raised using the `issue tracker`_ on the
-TrustedFirmware.org website. Using this tracker makes it easy for the
-maintainers to prioritise and respond to your ticket.
+Bug reports may be filed on the `issue tracker`_ on the TrustedFirmware.org
+website. Using this tracker gives everyone visibility of the known issues in
+TF-A.
Arm Licensees
^^^^^^^^^^^^^
@@ -44,4 +53,4 @@
--------------
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index 7886cf4..bdfb6d6 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -6,15 +6,20 @@
- Make sure you have a Github account and you are logged on both
`developer.trustedfirmware.org`_ and `review.trustedfirmware.org`_.
-- Create an `issue`_ for your work if one does not already exist. This gives
- everyone visibility of whether others are working on something similar.
- - If you intend to include Third Party IP in your contribution, please
- raise a separate `issue`_ for this and ensure that the changes that
- include Third Party IP are made on a separate topic branch.
+- If you plan to contribute a major piece of work, it is usually a good idea to
+ start a discussion around it on the mailing list. This gives everyone
+ visibility of what is coming up, you might learn that somebody else is
+ already working on something similar or the community might be able to
+ provide some early input to help shaping the design of the feature.
+
+ If you intend to include Third Party IP in your contribution, please mention
+ it explicitly in the email thread and ensure that the changes that include
+ Third Party IP are made in a separate patch (or patch series).
- Clone `Trusted Firmware-A`_ on your own machine as described in
:ref:`prerequisites_get_source`.
+
- Create a local topic branch based on the `Trusted Firmware-A`_ ``master``
branch.
@@ -23,44 +28,51 @@
- Make commits of logical units. See these general `Git guidelines`_ for
contributing to a project.
+
- Follow the :ref:`Coding Style` and :ref:`Coding Guidelines`.
- Use the checkpatch.pl script provided with the Linux source tree. A
Makefile target is provided for convenience.
- Keep the commits on topic. If you need to fix another bug or make another
- enhancement, please create a separate `issue`_ and address it on a separate
- topic branch.
+ enhancement, please address it on a separate topic branch.
+
- Avoid long commit series. If you do have a long series, consider whether
some commits should be squashed together or addressed in a separate topic.
+
- Make sure your commit messages are in the proper format. If a commit fixes
an `issue`_, include a reference.
-- Where appropriate, please update the documentation.
-
- - Consider whether the :ref:`Porting Guide`,
- :ref:`Firmware Design` document or other in-source documentation needs
- updating.
- - Ensure that each changed file has the correct copyright and license
- information. Files that entirely consist of contributions to this
- project should have a copyright notice and BSD-3-Clause SPDX license
- identifier of the form as shown in :ref:`license`. Files that contain
- changes to imported Third Party IP files should retain their original
- copyright and license notices. For significant contributions you may
- add your own copyright notice in following format:
- ::
+- Where appropriate, please update the documentation.
- Portions copyright (c) [XXXX-]YYYY, <OWNER>. All rights reserved.
+ - Consider whether the :ref:`Porting Guide`, :ref:`Firmware Design` document
+ or other in-source documentation needs updating.
- where XXXX is the year of first contribution (if different to YYYY) and
- YYYY is the year of most recent contribution. <OWNER> is your name or
- your company name.
- If you are submitting new files that you intend to be the code owner for
(for example, a new platform port), then also update the
:ref:`code owners` file.
- - For topics with multiple commits, you should make all documentation
- changes (and nothing else) in the last commit of the series. Otherwise,
- include the documentation changes within the single commit.
+
+ - For topics with multiple commits, you should make all documentation changes
+ (and nothing else) in the last commit of the series. Otherwise, include
+ the documentation changes within the single commit.
+
+- Ensure that each changed file has the correct copyright and license
+ information. Files that entirely consist of contributions to this project
+ should have a copyright notice and BSD-3-Clause SPDX license identifier of
+ the form as shown in :ref:`license`. Files that contain changes to imported
+ Third Party IP files should retain their original copyright and license
+ notices.
+
+ For significant contributions you may add your own copyright notice in the
+ following format:
+
+ ::
+
+ Portions copyright (c) [XXXX-]YYYY, <OWNER>. All rights reserved.
+
+ where XXXX is the year of first contribution (if different to YYYY) and YYYY
+ is the year of most recent contribution. <OWNER> is your name or your company
+ name.
- Please test your changes. As a minimum, ensure that Linux boots on the
Foundation FVP. See :ref:`Arm Fixed Virtual Platforms (FVP)` for more
diff --git a/docs/process/security.rst b/docs/process/security.rst
index 516eb98..a3b9971 100644
--- a/docs/process/security.rst
+++ b/docs/process/security.rst
@@ -20,13 +20,15 @@
Although we try to keep TF-A secure, we can only do so with the help of the
community of developers and security researchers.
-If you think you have found a security vulnerability, please **do not** report
-it in the `issue tracker`_. Instead, please follow the `TrustedFirmware.org
-security incident process`_. One of the goals of this process is to ensure
-providers of products that use TF-A have a chance to consider the implications
-of the vulnerability and its remedy before it is made public. As such, please
-follow the disclosure plan outlined in the process. We do our best to respond
-and fix any issues quickly.
+.. warning::
+ If you think you have found a security vulnerability, please **do not**
+ report it in the `issue tracker`_ or on the `mailing list`_. Instead, please
+ follow the `TrustedFirmware.org security incident process`_.
+
+One of the goals of this process is to ensure providers of products that use
+TF-A have a chance to consider the implications of the vulnerability and its
+remedy before it is made public. As such, please follow the disclosure plan
+outlined in the process. We do our best to respond and fix any issues quickly.
Afterwards, we encourage you to write-up your findings about the TF-A source
code.
@@ -69,6 +71,7 @@
+-----------+------------------------------------------------------------------+
.. _issue tracker: https://developer.trustedfirmware.org/project/board/1/
+.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a
.. |TFV-1| replace:: :ref:`Advisory TFV-1 (CVE-2016-10319)`
.. |TFV-2| replace:: :ref:`Advisory TFV-2 (CVE-2017-7564)`
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index b98abdf..b665bc7 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -13,6 +13,10 @@
#define DENVER_MIDR_PN2 U(0x4E0F0020)
#define DENVER_MIDR_PN3 U(0x4E0F0030)
#define DENVER_MIDR_PN4 U(0x4E0F0040)
+#define DENVER_MIDR_PN5 U(0x4E0F0050)
+#define DENVER_MIDR_PN6 U(0x4E0F0060)
+#define DENVER_MIDR_PN7 U(0x4E0F0070)
+#define DENVER_MIDR_PN8 U(0x4E0F0080)
/* Implementer code in the MIDR register */
#define DENVER_IMPL U(0x4E)
diff --git a/include/plat/arm/common/fconf_arm_sp_getter.h b/include/plat/arm/common/fconf_arm_sp_getter.h
index 236254b..c6315be 100644
--- a/include/plat/arm/common/fconf_arm_sp_getter.h
+++ b/include/plat/arm/common/fconf_arm_sp_getter.h
@@ -14,11 +14,13 @@
#define arm__sp_getter(prop) arm_sp.prop
#define ARM_SP_MAX_SIZE U(0x80000)
+#define ARM_SP_OWNER_NAME_LEN U(8)
struct arm_sp_t {
unsigned int number_of_sp;
union uuid_helper_t uuids[MAX_SP_IDS];
uintptr_t load_addr[MAX_SP_IDS];
+ char owner[MAX_SP_IDS][ARM_SP_OWNER_NAME_LEN];
};
int fconf_populate_arm_sp(uintptr_t config);
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index bdca4c3..d662e7f 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -387,3 +387,31 @@
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
+
+declare_cpu_ops_wa denver, DENVER_MIDR_PN5, \
+ denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
+ denver_core_pwr_dwn, \
+ denver_cluster_pwr_dwn
+
+declare_cpu_ops_wa denver, DENVER_MIDR_PN6, \
+ denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
+ denver_core_pwr_dwn, \
+ denver_cluster_pwr_dwn
+
+declare_cpu_ops_wa denver, DENVER_MIDR_PN7, \
+ denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
+ denver_core_pwr_dwn, \
+ denver_cluster_pwr_dwn
+
+declare_cpu_ops_wa denver, DENVER_MIDR_PN8, \
+ denver_reset_func, \
+ check_errata_cve_2017_5715, \
+ CPU_NO_EXTRA2_FUNC, \
+ denver_core_pwr_dwn, \
+ denver_cluster_pwr_dwn
diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
index 280a64a..1ee7285 100644
--- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
@@ -84,11 +84,13 @@
cactus-primary {
uuid = <0x1e67b5b4 0xe14f904a 0x13fb1fb8 0xcbdae1da>;
load-address = <0x7000000>;
+ owner = "SiP";
};
cactus-secondary {
uuid = <0x092358d1 0xb94723f0 0x64447c82 0xc88f57f5>;
load-address = <0x7100000>;
+ owner = "Plat";
};
#endif
};
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 350ecd1..5f125d3 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -52,6 +52,7 @@
[NON_TRUSTED_FW_CONTENT_CERT_ID] = {UUID_NON_TRUSTED_FW_CONTENT_CERT},
#if defined(SPD_spmd)
[SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT},
+ [PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT},
#endif
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
@@ -189,6 +190,11 @@
(uintptr_t)&arm_uuid_spec[SIP_SP_CONTENT_CERT_ID],
open_fip
},
+ [PLAT_SP_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[PLAT_SP_CONTENT_CERT_ID],
+ open_fip
+ },
#endif
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
@@ -197,7 +203,7 @@
#ifdef IMAGE_BL2
#if TRUSTED_BOARD_BOOT
-#define FCONF_ARM_IO_UUID_NUMBER U(20)
+#define FCONF_ARM_IO_UUID_NUMBER U(21)
#else
#define FCONF_ARM_IO_UUID_NUMBER U(10)
#endif
@@ -234,6 +240,7 @@
{NON_TRUSTED_FW_CONTENT_CERT_ID, "nt_fw_content_cert_uuid"},
#if defined(SPD_spmd)
{SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"},
+ {PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"},
#endif
#endif /* TRUSTED_BOARD_BOOT */
};
diff --git a/plat/arm/common/fconf/arm_fconf_sp.c b/plat/arm/common/fconf/arm_fconf_sp.c
index 4459264..50a9dd4 100644
--- a/plat/arm/common/fconf/arm_fconf_sp.c
+++ b/plat/arm/common/fconf/arm_fconf_sp.c
@@ -30,7 +30,13 @@
union uuid_helper_t uuid_helper;
unsigned int index = 0;
uint32_t val32;
- const unsigned int sp_start_index = SP_PKG1_ID;
+ bool is_plat_owned = false;
+ const unsigned int sip_start = SP_PKG1_ID;
+ unsigned int sip_index = sip_start;
+ const unsigned int sip_end = sip_start + MAX_SP_IDS / 2;
+ const unsigned int plat_start = SP_PKG5_ID;
+ unsigned int plat_index = plat_start;
+ const unsigned int plat_end = plat_start + MAX_SP_IDS / 2;
/* As libfdt use void *, we can't avoid this cast */
const void *dtb = (void *)config;
@@ -45,27 +51,20 @@
}
fdt_for_each_subnode(sp_node, dtb, node) {
- if (index == MAX_SP_IDS) {
+ if ((index == MAX_SP_IDS) || (sip_index == sip_end)
+ || (plat_index == plat_end)) {
ERROR("FCONF: Reached max number of SPs\n");
return -1;
}
+ /* Read UUID */
err = fdt_read_uint32_array(dtb, sp_node, "uuid", 4,
uuid_helper.word);
if (err < 0) {
ERROR("FCONF: cannot read SP uuid\n");
return -1;
}
-
arm_sp.uuids[index] = uuid_helper;
-
- err = fdt_read_uint32(dtb, sp_node, "load-address", &val32);
- if (err < 0) {
- ERROR("FCONF: cannot read SP load address\n");
- return -1;
- }
- arm_sp.load_addr[index] = val32;
-
VERBOSE("FCONF: %s UUID %x-%x-%x-%x load_addr=%lx\n",
__func__,
uuid_helper.word[0],
@@ -74,8 +73,52 @@
uuid_helper.word[3],
arm_sp.load_addr[index]);
+ /* Read Load address */
+ err = fdt_read_uint32(dtb, sp_node, "load-address", &val32);
+ if (err < 0) {
+ ERROR("FCONF: cannot read SP load address\n");
+ return -1;
+ }
+ arm_sp.load_addr[index] = val32;
+
- /* Add SP information in mem param descriptor */
- sp_mem_params_descs[index].image_id = sp_start_index + index;
+ /* Read owner field only for dualroot CoT */
+#if defined(ARM_COT_dualroot)
+ /* Owner is an optional field, no need to catch error */
+ fdtw_read_string(dtb, sp_node, "owner",
+ arm_sp.owner[index], ARM_SP_OWNER_NAME_LEN);
+#endif
+ /* If owner is empty mark it as SiP owned */
+ if ((strncmp(arm_sp.owner[index], "SiP",
+ ARM_SP_OWNER_NAME_LEN) == 0) ||
+ (strncmp(arm_sp.owner[index], "",
+ ARM_SP_OWNER_NAME_LEN) == 0)) {
+ is_plat_owned = false;
+ } else if (strcmp(arm_sp.owner[index], "Plat") == 0) {
+ is_plat_owned = true;
+ } else {
+ ERROR("FCONF: %s is not a valid SP owner\n",
+ arm_sp.owner[index]);
+ return -1;
+ }
+ /*
+ * Add SP information in mem param descriptor and IO policies
+ * structure.
+ */
+ if (is_plat_owned) {
+ sp_mem_params_descs[index].image_id = plat_index;
+ policies[plat_index].image_spec =
+ (uintptr_t)&arm_sp.uuids[index];
+ policies[plat_index].dev_handle = &fip_dev_handle;
+ policies[plat_index].check = open_fip;
+ plat_index++;
+ } else {
+ sp_mem_params_descs[index].image_id = sip_index;
+ policies[sip_index].image_spec =
+ (uintptr_t)&arm_sp.uuids[index];
+ policies[sip_index].dev_handle = &fip_dev_handle;
+ policies[sip_index].check = open_fip;
+ sip_index++;
+ }
SET_PARAM_HEAD(&sp_mem_params_descs[index].image_info,
PARAM_IMAGE_BINARY, VERSION_2, 0);
sp_mem_params_descs[index].image_info.image_max_size =
@@ -84,13 +127,6 @@
INVALID_IMAGE_ID;
sp_mem_params_descs[index].image_info.image_base =
arm_sp.load_addr[index];
-
- /* Add SP information in IO policies structure */
- policies[sp_start_index + index].image_spec =
- (uintptr_t)&arm_sp.uuids[index];
- policies[sp_start_index + index].dev_handle = &fip_dev_handle;
- policies[sp_start_index + index].check = open_fip;
-
index++;
}
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 40713b2..e56909d 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -248,12 +248,6 @@
tegra_memctrl_setup();
/*
- * Set up the TZRAM memory aperture to allow only secure world
- * access
- */
- tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
-
- /*
* Late setup handler to allow platforms to performs additional
* functionality.
* This handler gets called with MMU enabled.
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index f412a80..bb8bd7d 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -12,37 +12,46 @@
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-COMMON_DIR := plat/nvidia/tegra/common
+TEGRA_COMMON := plat/nvidia/tegra/common
+TEGRA_DRIVERS := plat/nvidia/tegra/drivers
+TEGRA_LIBS := plat/nvidia/tegra/lib
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
TEGRA_GICv3_SOURCES := $(GICV3_SOURCES) \
plat/common/plat_gicv3.c \
- ${COMMON_DIR}/tegra_gicv3.c
+ ${TEGRA_COMMON}/tegra_gicv3.c
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
TEGRA_GICv2_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
- ${COMMON_DIR}/tegra_gicv2.c
+ ${TEGRA_COMMON}/tegra_gicv2.c
+
+TEGRA_GICv3_SOURCES := drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v3/arm_gicv3_common.c \
+ drivers/arm/gic/v3/gicv3_main.c \
+ drivers/arm/gic/v3/gicv3_helpers.c \
+ plat/common/plat_gicv3.c \
+ ${TEGRA_COMMON}/tegra_gicv3.c
BL31_SOURCES += drivers/delay_timer/delay_timer.c \
drivers/io/io_storage.c \
plat/common/aarch64/crash_console_helpers.S \
${TEGRA_GICv2_SOURCES} \
- ${COMMON_DIR}/aarch64/tegra_helpers.S \
- ${COMMON_DIR}/lib/debug/profiler.c \
- ${COMMON_DIR}/tegra_bl31_setup.c \
- ${COMMON_DIR}/tegra_delay_timer.c \
- ${COMMON_DIR}/tegra_ehf.c \
- ${COMMON_DIR}/tegra_fiq_glue.c \
- ${COMMON_DIR}/tegra_io_storage.c \
- ${COMMON_DIR}/tegra_platform.c \
- ${COMMON_DIR}/tegra_pm.c \
- ${COMMON_DIR}/tegra_sip_calls.c \
- ${COMMON_DIR}/tegra_sdei.c
+ ${TEGRA_COMMON}/aarch64/tegra_helpers.S \
+ ${TEGRA_LIBS}/debug/profiler.c \
+ ${TEGRA_COMMON}/tegra_bl31_setup.c \
+ ${TEGRA_COMMON}/tegra_delay_timer.c \
+ ${TEGRA_COMMON}/tegra_ehf.c \
+ ${TEGRA_COMMON}/tegra_fiq_glue.c \
+ ${TEGRA_COMMON}/tegra_io_storage.c \
+ ${TEGRA_COMMON}/tegra_platform.c \
+ ${TEGRA_COMMON}/tegra_pm.c \
+ ${TEGRA_COMMON}/tegra_sip_calls.c \
+ ${TEGRA_COMMON}/tegra_sdei.c
ifneq ($(ENABLE_STACK_PROTECTOR), 0)
-BL31_SOURCES += ${COMMON_DIR}/tegra_stack_protector.c
+BL31_SOURCES += ${TEGRA_COMMON}/tegra_stack_protector.c
endif
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 0430048..78e96cf 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -180,11 +180,6 @@
tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
(uint32_t)plat_params->tzdram_size);
- /*
- * Set up the TZRAM memory aperture to allow only secure world
- * access
- */
- tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
} else {
/*
* Initialize the GIC cpu and distributor interfaces
diff --git a/plat/nvidia/tegra/common/drivers/bpmp/bpmp.c b/plat/nvidia/tegra/drivers/bpmp/bpmp.c
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/bpmp/bpmp.c
rename to plat/nvidia/tegra/drivers/bpmp/bpmp.c
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c b/plat/nvidia/tegra/drivers/bpmp_ipc/intf.c
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
rename to plat/nvidia/tegra/drivers/bpmp_ipc/intf.c
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h b/plat/nvidia/tegra/drivers/bpmp_ipc/intf.h
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h
rename to plat/nvidia/tegra/drivers/bpmp_ipc/intf.h
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c b/plat/nvidia/tegra/drivers/bpmp_ipc/ivc.c
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c
rename to plat/nvidia/tegra/drivers/bpmp_ipc/ivc.c
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.h b/plat/nvidia/tegra/drivers/bpmp_ipc/ivc.h
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.h
rename to plat/nvidia/tegra/drivers/bpmp_ipc/ivc.h
diff --git a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c b/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
rename to plat/nvidia/tegra/drivers/flowctrl/flowctrl.c
diff --git a/plat/nvidia/tegra/common/drivers/gpcdma/gpcdma.c b/plat/nvidia/tegra/drivers/gpcdma/gpcdma.c
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/gpcdma/gpcdma.c
rename to plat/nvidia/tegra/drivers/gpcdma/gpcdma.c
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c
similarity index 95%
rename from plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
rename to plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c
index c3f95db..b3dcd2a 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
+++ b/plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,20 +93,6 @@
tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
}
-/*
- * Secure the BL31 TZRAM aperture.
- *
- * phys_base = physical base of TZRAM aperture
- * size_in_bytes = size of aperture in bytes
- */
-void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
-{
- /*
- * The v1 hardware controller does not have any registers
- * for setting up the on-chip TZRAM.
- */
-}
-
static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
unsigned long long non_overlap_area_size)
{
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
rename to plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
diff --git a/plat/nvidia/tegra/common/drivers/pmc/pmc.c b/plat/nvidia/tegra/drivers/pmc/pmc.c
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/pmc/pmc.c
rename to plat/nvidia/tegra/drivers/pmc/pmc.c
diff --git a/plat/nvidia/tegra/common/drivers/smmu/smmu.c b/plat/nvidia/tegra/drivers/smmu/smmu.c
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/smmu/smmu.c
rename to plat/nvidia/tegra/drivers/smmu/smmu.c
diff --git a/plat/nvidia/tegra/common/drivers/spe/shared_console.S b/plat/nvidia/tegra/drivers/spe/shared_console.S
similarity index 100%
rename from plat/nvidia/tegra/common/drivers/spe/shared_console.S
rename to plat/nvidia/tegra/drivers/spe/shared_console.S
diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h
index d5ef60d..cc85095 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +11,6 @@
void tegra_memctrl_setup(void);
void tegra_memctrl_restore_settings(void);
void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
-void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_disable_ahb_redirection(void);
void tegra_memctrl_clear_pending_interrupts(void);
diff --git a/plat/nvidia/tegra/common/lib/debug/profiler.c b/plat/nvidia/tegra/lib/debug/profiler.c
similarity index 100%
rename from plat/nvidia/tegra/common/lib/debug/profiler.c
rename to plat/nvidia/tegra/lib/debug/profiler.c
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 16bd0ea..3d76be9 100644
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -25,9 +25,9 @@
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
- ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
- ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
- ${COMMON_DIR}/drivers/pmc/pmc.c \
+ ${TEGRA_DRIVERS}/flowctrl/flowctrl.c \
+ ${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \
+ ${TEGRA_DRIVERS}/pmc/pmc.c \
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_sip_calls.c \
${SOC_DIR}/plat_setup.c \
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index d320aac..6739c50 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -43,16 +43,16 @@
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
lib/cpus/aarch64/cortex_a57.S \
- ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \
- ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \
- ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \
- ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
- ${COMMON_DIR}/drivers/smmu/smmu.c \
+ ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
+ ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \
+ ${TEGRA_DRIVERS}/gpcdma/gpcdma.c \
+ ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \
+ ${TEGRA_DRIVERS}/smmu/smmu.c \
${SOC_DIR}/drivers/mce/mce.c \
${SOC_DIR}/drivers/mce/ari.c \
${SOC_DIR}/drivers/mce/nvg.c \
${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
- $(SOC_DIR)/drivers/se/se.c \
+ $(SOC_DIR)/drivers/se/se.c \
${SOC_DIR}/plat_memctrl.c \
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_setup.c \
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index d7d15f5..7573ed2 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -40,11 +40,10 @@
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
- ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \
- ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \
- ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \
- ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
- ${COMMON_DIR}/drivers/smmu/smmu.c \
+ ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
+ ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \
+ ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \
+ ${TEGRA_DRIVERS}/smmu/smmu.c \
${SOC_DIR}/drivers/mce/mce.c \
${SOC_DIR}/drivers/mce/nvg.c \
${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
@@ -57,8 +56,12 @@
${SOC_DIR}/plat_smmu.c \
${SOC_DIR}/plat_trampoline.S
+ifeq (${USE_GPC_DMA}, 1)
+BL31_SOURCES += ${TEGRA_DRIVERS}/gpcdma/gpcdma.c
+endif
+
ifeq (${ENABLE_CONSOLE_SPE},1)
-BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S
+BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S
endif
# RAS sources
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index 14e3324..6c4c175 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -25,20 +25,20 @@
ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1
-PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \
-I${SOC_DIR}/drivers/se
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
- ${COMMON_DIR}/drivers/bpmp/bpmp.c \
- ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
- ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
- ${COMMON_DIR}/drivers/pmc/pmc.c \
+ ${TEGRA_DRIVERS}/bpmp/bpmp.c \
+ ${TEGRA_DRIVERS}/flowctrl/flowctrl.c \
+ ${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \
+ ${TEGRA_DRIVERS}/pmc/pmc.c \
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/drivers/se/security_engine.c \
- ${SOC_DIR}/plat_secondary.c \
+ ${SOC_DIR}/plat_secondary.c \
${SOC_DIR}/plat_sip_calls.c
# Enable workarounds for selected Cortex-A57 erratas.
diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
index 5d7d495..8866fb5 100644
--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
+++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
@@ -16,9 +16,9 @@
plat/st/stm32mp1/stm32mp1_topology.c
# Generic GIC v2
-BL32_SOURCES += drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
- drivers/arm/gic/v2/gicv2_main.c \
+include drivers/arm/gic/v2/gicv2.mk
+
+BL32_SOURCES += ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/st/stm32mp1/stm32mp1_gic.c
diff --git a/tools/sptool/sp_mk_generator.py b/tools/sptool/sp_mk_generator.py
index 2153a56..a37e702 100755
--- a/tools/sptool/sp_mk_generator.py
+++ b/tools/sptool/sp_mk_generator.py
@@ -19,6 +19,7 @@
param1: Generated mk file "sp_gen.mk"
param2: "SP_LAYOUT_FILE", json file containing platform provided information
param3: plat out directory
+param4: CoT parameter
Generated "sp_gen.mk" file contains triplet of following information for each
Secure Partition entry
@@ -58,11 +59,39 @@
gen_file = os.path.abspath(sys.argv[1])
out_dir = os.path.abspath(sys.argv[3])
dtb_dir = out_dir + "/fdts/"
+MAX_SP = 8
+dualroot = sys.argv[4].lower() == "dualroot"
+split = int(MAX_SP / 2)
print(dtb_dir)
+platform_count = 1
+sip_count = 1
with open(gen_file, 'w') as out_file:
for idx, key in enumerate(data.keys()):
+ pkg_num = idx + 1
+
+ if (pkg_num > MAX_SP):
+ print("WARNING: Too many secure partitions\n")
+ exit(-1)
+
+ if dualroot:
+ owner = data[key].get('owner')
+ if owner == "Plat":
+ if (platform_count > split):
+ print("WARNING: Maximum Secure partitions by Plat " +
+ "have been exceeded (" + str(split) + ")\n")
+ exit(-1)
+ pkg_num = split + platform_count
+ platform_count += 1
+ elif (sip_count > split):
+ print("WARNING: Maximum Secure partitions by SiP " +
+ "have been exceeded (" + str(split) + ")\n")
+ exit(-1)
+ else:
+ pkg_num = sip_count
+ sip_count += 1
+
"""
Append FDT_SOURCES
"""
@@ -81,10 +110,10 @@
Extract uuid from partition manifest
"""
pm_file = open(dts)
- key = "uuid"
+ uuid_key = "uuid"
for line in pm_file:
- if key in line:
+ if uuid_key in line:
uuid_hex = re.findall(r'\<(.+?)\>', line)[0];
# PM has uuid in format 0xABC... 0x... 0x... 0x...
@@ -103,5 +132,6 @@
"""
Append CRT_ARGS
"""
- out_file.write("CRT_ARGS += --sp-pkg" + str(idx + 1) + " " + dst + "\n")
+
+ out_file.write("CRT_ARGS += --sp-pkg" + str(pkg_num) + " " + dst + "\n")
out_file.write("\n")