Merge "fix(intel): update CCU configuration for Agilex5 platform" into integration
diff --git a/Makefile b/Makefile
index c2ed9ee..280f096 100644
--- a/Makefile
+++ b/Makefile
@@ -32,6 +32,12 @@
################################################################################
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
+include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
+
+# To be able to set platform specific defaults
+ifneq ($(PLAT_DEFAULTS_MAKEFILE_FULL),)
+include ${PLAT_DEFAULTS_MAKEFILE_FULL}
+endif
################################################################################
# Configure the toolchains used to build TF-A and its tools
@@ -42,7 +48,6 @@
# Assertions enabled for DEBUG builds by default
ENABLE_ASSERTIONS := ${DEBUG}
ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION}
-PLAT := ${DEFAULT_PLAT}
################################################################################
# Checkpatch script options
@@ -407,7 +412,6 @@
################################################################################
# Generic definitions
################################################################################
-include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
ifeq (${BUILD_BASE},)
BUILD_BASE := ./build
@@ -1733,8 +1737,8 @@
tl: ${BUILD_PLAT}/tl.bin
${BUILD_PLAT}/tl.bin: ${HW_CONFIG}
- $(q)poetry -q install
- $(q)poetry run tlc create --fdt $< -s ${FW_HANDOFF_SIZE} $@
+ $(if $(host-poetry),$(q)poetry -q install)
+ $(q)$(if $(host-poetry),poetry run )tlc create --fdt $< -s ${FW_HANDOFF_SIZE} $@
doc:
$(s)echo " BUILD DOCUMENTATION"
diff --git a/changelog.yaml b/changelog.yaml
index d073a84..5224441 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -272,6 +272,13 @@
- title: Corstone-1000
scope: corstone-1000
+ - title: Automotive RD
+ scope: automotive_rd
+
+ subsections:
+ - title: RD-1 AE
+ scope: rd1ae
+
- title: Aspeed
scope: aspeed
diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index 783b660..b213ffa 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,6 +88,19 @@
return 0;
}
+uint64_t fdt_read_uint64_default(const void *dtb, int node,
+ const char *prop_name, uint64_t dflt_value)
+{
+ uint64_t ret = dflt_value;
+ int err = fdt_read_uint64(dtb, node, prop_name, &ret);
+
+ if (err < 0) {
+ return dflt_value;
+ }
+
+ return ret;
+}
+
/*
* Read bytes from a given property of the given node. Any number of
* bytes of the property can be read. The fdt pointer is updated.
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 8bb12ab..4d08a7f 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -594,6 +594,16 @@
:|G|: `rupsin01`_
:|F|: plat/arm/board/tc
+Arm Automotive RD platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Diego Sueiro <diego.sueiro@arm.com>
+:|G|: `diego-sueiro`_
+:|M|: Peter Hoyes <peter.hoyes@arm.com>
+:|G|: `hoyes`_
+:|M|: Divin Raj <divin.raj@arm.com>
+:|G|: `divin-raj`_
+:|F|: plat/arm/board/automotive_rd
+
Aspeed platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
@@ -1041,12 +1051,15 @@
.. _CJKay: https://github.com/cjkay
.. _danh-arm: https://github.com/danh-arm
.. _davidvincze: https://github.com/davidvincze
+.. _diego-sueiro: https://github.com/diego-sueiro
+.. _divin-raj: https://github.com/divin-raj
.. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo
.. _gprocopciucnxp: https://github.com/gprocopciucnxp
.. _grandpaul: https://github.com/grandpaul
.. _harrisonmutai-arm: https://github.com/harrisonmutai-arm
.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
+.. _hoyes: https://github.com/hoyes
.. _hzhuang1: https://github.com/hzhuang1
.. _hugues-kambampiana-arm: https://github.com/hugueskamba
.. _JackyBai: https://github.com/JackyBai
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index e1b3ef0..afbb157 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -16,6 +16,12 @@
should match the frame used by the Non-Secure image (normally the Linux
kernel). Default is true (access to the frame is allowed).
+- ``ARM_FW_CONFIG_LOAD_ENABLE``: Boolean option to enable the loading of
+ FW_CONFIG device trees from the Firmware Image Package (FIP). When enabled,
+ BL2 calls the platform specific function `arm_bl2_el3_plat_config_load`.
+ This function is responsible for loading, parsing, and validating the
+ FW_CONFIG device trees from the FIP. The option depends on RESET_TO_BL2.
+
- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
By default, Arm platforms use a watchdog to trigger a system reset in case
an error is encountered during the boot process (for example, when an image
diff --git a/docs/plat/arm/automotive_rd/index.rst b/docs/plat/arm/automotive_rd/index.rst
new file mode 100644
index 0000000..d0db6ac
--- /dev/null
+++ b/docs/plat/arm/automotive_rd/index.rst
@@ -0,0 +1,50 @@
+RD-1 AE (Kronos) Platform
+=========================
+
+Some of the features of the RD-1 AE platform referenced in TF-A include:
+
+- Neoverse-V3AE, Arm9.2-A application processor (64-bit mode)
+- A GICv4-compatible GIC-720AE
+
+Further information on RD1-AE is available at `rd1ae`_
+
+Boot Sequence
+-------------
+
+BL2 –> BL31 –> BL33
+
+The boot process starts from RSE (Runtime Security Engine) that loads the BL2 image
+and signals the System Control Processor (SCP) to power up the Application Processor (AP).
+The AP then runs BL2, which loads the rest of the images, including the runtime firmware
+BL31, and proceeds to execute it. Finally, it passes control to the non-secure world
+BL33 (u-boot).
+
+BL2 performs the actions described in the `Trusted Board Boot (TBB)`_ document.
+
+Build Procedure (TF-A only)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Obtain `Arm toolchain`_ and set the CROSS_COMPILE environment variable to
+ point to the toolchain folder.
+
+- Build TF-A:
+
+ .. code:: shell
+
+ make \
+ PLAT=rd1ae \
+ MBEDTLS_DIR=<mbedtls_dir> \
+ ARCH=aarch64 \
+ CREATE_KEYS=1 \
+ GENERATE_COT=1 \
+ TRUSTED_BOARD_BOOT=1 \
+ COT=tbbr \
+ ARM_ROTPK_LOCATION=devel_rsa \
+ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
+ BL33=<path to u-boot binary> \
+
+*Copyright (c) 2024, Arm Limited. All rights reserved.*
+
+.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
+.. _rd1ae: https://developer.arm.com/Tools%20and%20Software/Arm%20Reference%20Design-1%20AE
+.. _Trusted Board Boot (TBB): https://trustedfirmware-a.readthedocs.io/en/latest/design/trusted-board-boot.html
diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
index 2f68522..35c0c59 100644
--- a/docs/plat/arm/index.rst
+++ b/docs/plat/arm/index.rst
@@ -14,6 +14,7 @@
arm-build-options
morello/index
corstone1000/index
+ automotive_rd/index
This chapter holds documentation related to Arm's development platforms,
including both software models (FVPs) and hardware development boards
@@ -21,4 +22,4 @@
--------------
-*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/s32g274a.rst b/docs/plat/s32g274a.rst
index 3aa858e..d3f31ca 100644
--- a/docs/plat/s32g274a.rst
+++ b/docs/plat/s32g274a.rst
@@ -95,5 +95,17 @@
-d "${BOOT_IMAGE}" \
fip.s32
+SoC Errata Workarounds
+----------------------
+
+The S32G274A port of the TF-A includes compilation flags that can be used to
+control the workaround for the SoC. These flags are used similarly to how the
+:ref:`arm_cpu_macros_errata_workarounds` are used. The list of workarounds
+includes the following switches:
+
+- ``ERRATA_S32_051700``: This applies erratum ERR051700 workaround to
+ SoCs part of the S32 Common Chassis family, and therefore it needs to
+ be enabled for the S32G and S32R devices.
+
.. _s32g2: https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g2-processors-for-vehicle-networking:S32G2
.. _s32g274ardb2: https://www.nxp.com/design/design-center/designs/s32g2-vehicle-networking-reference-design:S32G-VNP-RDB2
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h b/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
new file mode 100644
index 0000000..5ff55fb
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2020-2021, 2023-2024 NXP
+ */
+#ifndef S32CC_MC_RGM_H
+#define S32CC_MC_RGM_H
+
+#include <stdint.h>
+
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value);
+
+#endif /* MC_RGM_H */
diff --git a/drivers/nxp/clk/s32cc/mc_rgm.c b/drivers/nxp/clk/s32cc/mc_rgm.c
new file mode 100644
index 0000000..cbf4022
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/mc_rgm.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <s32cc-mc-rgm.h>
+
+#define MC_RGM_PRST(MC_RGM, PER) ((MC_RGM) + 0x40UL + ((PER) * 0x8UL))
+
+/* ERR051700
+ * Releasing more than one Software Resettable Domain (SRD)
+ * from reset simultaneously, by clearing the corresponding
+ * peripheral MC_RGM_PRSTn[PERIPH_x_RST] reset control may
+ * cause a false setting of the Fault Collection and
+ * Control Unit (FCCU) Non-Critical Fault (NCF) flag
+ * corresponding to a Memory-Test-Repair (MTR) Error
+ */
+#if (ERRATA_S32_051700 == 1)
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value)
+{
+ uint32_t current_bit_checked, i;
+ uint32_t current_regs, mask;
+ int bit_index;
+
+ current_regs = mmio_read_32(MC_RGM_PRST(rgm, part));
+ /* Create a mask with all changed bits */
+ mask = current_regs ^ value;
+
+ while (mask != 0U) {
+ bit_index = __builtin_ffs(mask);
+ if (bit_index < 1) {
+ break;
+ }
+
+ i = (uint32_t)bit_index - 1U;
+ current_bit_checked = BIT_32(i);
+
+ /* Check if we assert or de-assert.
+ * Also wait for completion.
+ */
+ if ((value & current_bit_checked) != 0U) {
+ mmio_setbits_32(MC_RGM_PRST(rgm, part),
+ current_bit_checked);
+ while ((mmio_read_32(MC_RGM_PRST(rgm, part)) &
+ current_bit_checked) == 0U)
+ ;
+ } else {
+ mmio_clrbits_32(MC_RGM_PRST(rgm, part),
+ current_bit_checked);
+ while ((mmio_read_32(MC_RGM_PRST(rgm, part)) &
+ current_bit_checked) != 0U)
+ ;
+ }
+
+ mask &= ~current_bit_checked;
+ }
+}
+#else /* ERRATA_S32_051700 */
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value)
+{
+ mmio_write_32(MC_RGM_PRST(rgm, part), value);
+}
+#endif /* ERRATA_S32_051700 */
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk.mk b/drivers/nxp/clk/s32cc/s32cc_clk.mk
index 7a65ea6..2a9a376 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk.mk
+++ b/drivers/nxp/clk/s32cc/s32cc_clk.mk
@@ -9,6 +9,7 @@
-I${PLAT_DRIVERS_PATH}/clk/s32cc/include \
CLK_SOURCES := \
+ ${PLAT_DRIVERS_PATH}/clk/s32cc/mc_rgm.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_modules.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_utils.c \
diff --git a/drivers/st/crypto/stm32_hash.c b/drivers/st/crypto/stm32_hash.c
index e92f980..bd49324 100644
--- a/drivers/st/crypto/stm32_hash.c
+++ b/drivers/st/crypto/stm32_hash.c
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
+#include <common/sha_common_macros.h>
#include <drivers/clk.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_hash.h>
@@ -62,15 +63,6 @@
#define HASH_STR_NBLW_MASK GENMASK(4, 0)
#define HASH_STR_DCAL BIT(8)
-#define MD5_DIGEST_SIZE 16U
-#define SHA1_DIGEST_SIZE 20U
-#define SHA224_DIGEST_SIZE 28U
-#define SHA256_DIGEST_SIZE 32U
-#define SHA384_DIGEST_SIZE 48U
-#define SHA512_224_DIGEST_SIZE 28U
-#define SHA512_256_DIGEST_SIZE 32U
-#define SHA512_DIGEST_SIZE 64U
-
#define RESET_TIMEOUT_US_1MS 1000U
#define HASH_TIMEOUT_US 10000U
diff --git a/fdts/rd1ae.dts b/fdts/rd1ae.dts
new file mode 100644
index 0000000..3060b5a
--- /dev/null
+++ b/fdts/rd1ae.dts
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "RD-1 AE";
+ compatible = "arm,rd1ae", "arm,neoverse";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ stdout-path = &soc_serial0;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu1: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu2: cpu@20000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x20000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu3: cpu@30000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x30000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu4: cpu@40000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x40000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu5: cpu@50000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x50000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu6: cpu@60000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x60000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu7: cpu@70000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x70000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu8: cpu@80000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x80000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu9: cpu@90000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x90000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu10: cpu@a0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xa0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu11: cpu@b0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xb0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu12: cpu@c0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xc0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu13: cpu@d0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xd0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu14: cpu@e0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xe0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu15: cpu@f0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xf0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /*
+ * 0x7fc0 0000 - 0x7fff ffff : BL32
+ * 0x7fbf 0000 - 0x7fbf ffff : FFA_SHARED_MM_BUF
+ */
+ reg = <0x00000000 0x80000000 0 0x7fbf0000>,
+ <0x00000080 0x80000000 0 0x80000000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc_clk24mhz: clk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "refclk24mhz";
+ };
+
+ soc_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "refclk1mhz";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@30000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x30000000 0 0x10000>, // GICD
+ <0x0 0x301c0000 0 0x8000000>; // GICR
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ its1: msi-controller@30040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30040000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its2: msi-controller@30080000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30080000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its3: msi-controller@300c0000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x300c0000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its4: msi-controller@30100000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30100000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its5: msi-controller@30140000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30140000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its6: msi-controller@30180000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30180000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ soc_serial0: serial@2a400000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2a400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ watchdog@2a440000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x2a440000 0 0x1000>,
+ <0x0 0x2a450000 0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ rtc@c170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0x0c170000 0x0 0x10000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clk24mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ virtio-net@c150000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc150000 0x0 0x200>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio-block@c130000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc130000 0x0 0x200>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio-rng@c140000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc140000 0x0 0x200>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci@4000000000 {
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0x00 0x11>;
+ reg = <0x40 0x00 0x00 0x04000000>;
+ ranges = <0x43000000 0x40 0x40000000 0x40 0x40000000 0x10 0x00000000
+ 0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x08000000
+ 0x01000000 0x00 0x00 0x00 0x77800000 0x00 0x800000>;
+ msi-map = <0x00 &its1 0x40000 0x10000>;
+ iommu-map = <0x00 &smmu 0x40000 0x10000>;
+ dma-coherent;
+ };
+
+ smmu: iommu@280000000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x2 0x80000000 0x0 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ interrupts = <1 210 1>,
+ <1 211 1>,
+ <1 212 1>,
+ <1 213 1>;
+ interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+ msi-parent = <&its1 0x10000>;
+ };
+
+ sysreg: sysreg@c010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ fixed_3v3: v2m-3v3@c011000 {
+ compatible = "regulator-fixed";
+ reg = <0x0 0xc011000 0x0 0x1000>;
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ mmci@c050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x0 0xc050000 0x0 0x1000>;
+ interrupts = <0 0x8B 0x4>,
+ <0 0x8C 0x4>;
+ cd-gpios = <&sysreg 0 0>;
+ wp-gpios = <&sysreg 1 0>;
+ bus-width = <8>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&fixed_3v3>;
+ clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
+ clock-names = "mclk", "apb_pclk";
+ };
+
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ };
+
+};
diff --git a/fdts/tbbr_cot_descriptors.dtsi b/fdts/tbbr_cot_descriptors.dtsi
index b3c0ca7..253297f 100644
--- a/fdts/tbbr_cot_descriptors.dtsi
+++ b/fdts/tbbr_cot_descriptors.dtsi
@@ -195,6 +195,12 @@
hash = <&hw_config_hash>;
};
+ fw_config {
+ image-id = <FW_CONFIG_ID>;
+ parent = <&trusted_boot_fw_cert>;
+ hash = <&fw_config_hash>;
+ };
+
scp_bl2_image {
image-id = <SCP_BL2_IMAGE_ID>;
parent = <&scp_fw_content_cert>;
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index abbf976..de08f1d 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,8 @@
const char *prop_name, uint32_t dflt_value);
int fdt_read_uint64(const void *dtb, int node, const char *prop_name,
uint64_t *value);
+uint64_t fdt_read_uint64_default(const void *dtb, int node,
+ const char *prop_name, uint64_t dflt_value);
int fdt_read_uint32_array(const void *dtb, int node, const char *prop_name,
unsigned int cells, uint32_t *value);
int fdtw_read_string(const void *dtb, int node, const char *prop,
diff --git a/include/common/sha_common_macros.h b/include/common/sha_common_macros.h
new file mode 100644
index 0000000..a419488
--- /dev/null
+++ b/include/common/sha_common_macros.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SHA_COMMON_MACROS_H
+#define SHA_COMMON_MACROS_H
+
+#define MD5_DIGEST_SIZE 16U
+#define SHA1_DIGEST_SIZE 20U
+#define SHA224_DIGEST_SIZE 28U
+#define SHA256_DIGEST_SIZE 32U
+#define SHA384_DIGEST_SIZE 48U
+#define SHA512_224_DIGEST_SIZE 28U
+#define SHA512_256_DIGEST_SIZE 32U
+#define SHA512_DIGEST_SIZE 64U
+
+#endif /* SHA_COMMON_MACROS_H */
diff --git a/include/drivers/measured_boot/event_log/tcg.h b/include/drivers/measured_boot/event_log/tcg.h
index 4ac2c2f..653f9c2 100644
--- a/include/drivers/measured_boot/event_log/tcg.h
+++ b/include/drivers/measured_boot/event_log/tcg.h
@@ -8,6 +8,7 @@
#define TCG_H
#include <stdint.h>
+#include <common/sha_common_macros.h>
#define TCG_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
#define TCG_STARTUP_LOCALITY_SIGNATURE "StartupLocality"
@@ -66,12 +67,6 @@
#define PLATFORM_CLASS_CLIENT 0
#define PLATFORM_CLASS_SERVER 1
-/* SHA digest sizes in bytes */
-#define SHA1_DIGEST_SIZE 20
-#define SHA256_DIGEST_SIZE 32
-#define SHA384_DIGEST_SIZE 48
-#define SHA512_DIGEST_SIZE 64
-
enum {
/*
* SRTM, BIOS, Host Platform Extensions, Embedded
diff --git a/include/drivers/nxp/crypto/caam/hash.h b/include/drivers/nxp/crypto/caam/hash.h
index 9136dca..6201d23 100644
--- a/include/drivers/nxp/crypto/caam/hash.h
+++ b/include/drivers/nxp/crypto/caam/hash.h
@@ -9,6 +9,7 @@
#define __HASH_H__
#include <stdbool.h>
+#include <common/sha_common_macros.h>
/* List of hash algorithms */
enum hash_algo {
@@ -16,9 +17,6 @@
SHA256
};
-/* number of bytes in the SHA256-256 digest */
-#define SHA256_DIGEST_SIZE 32
-
/*
* number of words in the digest - Digest is kept internally
* as 8 32-bit words
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 83a5cd2..c3756bf 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -262,6 +262,9 @@
/* BL2 at EL3 functions */
void arm_bl2_el3_early_platform_setup(void);
void arm_bl2_el3_plat_arch_setup(void);
+#if ARM_FW_CONFIG_LOAD_ENABLE
+void arm_bl2_el3_plat_config_load(void);
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
/* BL2U utility functions */
void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h
index 4615ffb..635c28e 100644
--- a/include/services/rmmd_svc.h
+++ b/include/services/rmmd_svc.h
@@ -7,6 +7,7 @@
#ifndef RMMD_SVC_H
#define RMMD_SVC_H
+#include <common/sha_common_macros.h>
#include <lib/smccc.h>
#include <lib/utils_def.h>
@@ -96,11 +97,6 @@
#define RMI_SUCCESS 0
#define RMI_ERROR_INPUT 1
-/* Acceptable SHA sizes for Challenge object */
-#define SHA256_DIGEST_SIZE 32U
-#define SHA384_DIGEST_SIZE 48U
-#define SHA512_DIGEST_SIZE 64U
-
/*
* Retrieve Realm attestation key from EL3. Only P-384 ECC curve key is
* supported. The arguments to this SMC are :
diff --git a/make_helpers/plat_helpers.mk b/make_helpers/plat_helpers.mk
index a7ae9a2..bc02a20 100644
--- a/make_helpers/plat_helpers.mk
+++ b/make_helpers/plat_helpers.mk
@@ -11,6 +11,7 @@
ifndef PLAT_HELPERS_MK
PLAT_HELPERS_MK := $(lastword $(MAKEFILE_LIST))
+ PLAT:= ${DEFAULT_PLAT}
ifeq (${PLAT},)
$(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform")
endif
@@ -18,15 +19,18 @@
# TF_PLATFORM_ROOT can be overridden for when building tools directly
TF_PLATFORM_ROOT ?= plat/
PLAT_MAKEFILE := platform.mk
+ PLAT_DEFAULTS_MAKEFILE := platform_defaults.mk
# Generate the platforms list by recursively searching for all directories
# under /plat containing a PLAT_MAKEFILE. Append each platform with a `|`
# char and strip out the final '|'.
ALL_PLATFORM_MK_FILES := $(call rwildcard,${TF_PLATFORM_ROOT},${PLAT_MAKEFILE})
+ ALL_PLATFORM_MK_DEF_FILES := $(call rwildcard,${TF_PLATFORM_ROOT},${PLAT_DEFAULTS_MAKEFILE})
ALL_PLATFORM_DIRS := $(patsubst %/,%,$(dir ${ALL_PLATFORM_MK_FILES}))
ALL_PLATFORMS := $(sort $(notdir ${ALL_PLATFORM_DIRS}))
PLAT_MAKEFILE_FULL := $(filter %/${PLAT}/${PLAT_MAKEFILE},${ALL_PLATFORM_MK_FILES})
+ PLAT_DEFAULTS_MAKEFILE_FULL := $(filter %/${PLAT}/${PLAT_DEFAULTS_MAKEFILE},${ALL_PLATFORM_MK_DEF_FILES})
PLATFORM_LIST := $(subst ${space},|,${ALL_PLATFORMS})
ifeq ($(PLAT_MAKEFILE_FULL),)
$(error "Error: Invalid platform. The following platforms are available: ${PLATFORM_LIST}")
diff --git a/make_helpers/toolchain.mk b/make_helpers/toolchain.mk
index 243e18f..2ab577c 100644
--- a/make_helpers/toolchain.mk
+++ b/make_helpers/toolchain.mk
@@ -118,6 +118,9 @@
toolchain-tool-classes += dtc
toolchain-tool-class-name-dtc := device tree compiler
+ toolchain-tool-classes += poetry
+ toolchain-tool-class-name-poetry := Python Poetry package manager
+
#
# Configure tools that we recognize.
#
@@ -175,6 +178,9 @@
toolchain-tools += generic-dtc
toolchain-tool-name-generic-dtc := Device Tree Compiler (`dtc`)
+ toolchain-tools += generic-poetry
+ toolchain-tool-name-generic-poetry := Poetry (`poetry`)
+
#
# Assign tools to tool classes.
#
@@ -199,6 +205,7 @@
# Other tools
toolchain-tools-dtc := generic-dtc # Device tree compilers
+ toolchain-tools-poetry := generic-poetry # Python Poetry package manager
#
# Helper functions to identify toolchain tools.
@@ -256,9 +263,10 @@
# Other tools
toolchain-guess-tool-generic-dtc = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Version: DTC")
+ toolchain-guess-tool-generic-poetry = $(shell $(1) --version 2>&1 <$(nul))
- toolchain-guess-tool = $(firstword $(foreach candidate,$(1), \
- $(if $(call toolchain-guess-tool-$(candidate),$(2)),$(candidate))))
+ toolchain-guess-tool = $(if $(2),$(firstword $(foreach candidate,$(1),$\
+ $(if $(call toolchain-guess-tool-$(candidate),$(2)),$(candidate)))))
#
# Warn the user that a tool could not be identified.
@@ -313,26 +321,28 @@
# toolchain.
#
- toolchain-guess-arm-clang-cpp = $(1)
- toolchain-guess-arm-clang-as = $(1)
- toolchain-guess-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
- toolchain-guess-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
- toolchain-guess-arm-clang-od = # Fall back to `$(toolchain)-od-default`
- toolchain-guess-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
+ toolchain-derive-arm-clang-cpp = $(1)
+ toolchain-derive-arm-clang-as = $(1)
+ toolchain-derive-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
+ toolchain-derive-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
+ toolchain-derive-arm-clang-od = # Fall back to `$(toolchain)-od-default`
+ toolchain-derive-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
- toolchain-guess-llvm-clang-cpp = $(1)
- toolchain-guess-llvm-clang-as = $(1)
- toolchain-guess-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
- toolchain-guess-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
- toolchain-guess-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
- toolchain-guess-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
+ toolchain-derive-llvm-clang-cpp = $(1)
+ toolchain-derive-llvm-clang-as = $(1)
+ toolchain-derive-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
+ toolchain-derive-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
+ toolchain-derive-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
+ toolchain-derive-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
- toolchain-guess-gnu-gcc-cpp = $(1)
- toolchain-guess-gnu-gcc-as = $(1)
- toolchain-guess-gnu-gcc-ld = $(1)
- toolchain-guess-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
- toolchain-guess-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
- toolchain-guess-gnu-gcc-ar = $(shell $(1) --print-prog-name ar 2>$(nul))
+ toolchain-derive-gnu-gcc-cpp = $(1)
+ toolchain-derive-gnu-gcc-as = $(1)
+ toolchain-derive-gnu-gcc-ld = $(1)
+ toolchain-derive-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
+ toolchain-derive-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
+ toolchain-derive-gnu-gcc-ar = $(shell $(1) --print-prog-name ar 2>$(nul))
+
+ toolchain-derive = $(if $3,$(call toolchain-derive-$1-$2,$3))
#
# Configure a toolchain.
@@ -393,25 +403,32 @@
#
define toolchain-determine-tool
- toolchain-$1-$2-guess-from-cc = $$(if $$(filter-out cc,$2),$\
- $$(call toolchain-guess-$$($1-cc-id)-$2,$$($1-cc)))
+ toolchain-$1-$2-derive-from-cc = $$(if $$(filter-out cc,$2),$\
+ $$(call toolchain-derive,$$($1-cc-id),$2,$$($1-cc)))
- toolchain-$1-$2-shell = $$(or $$($$($1-$2-parameter)),$\
- $$(toolchain-$1-$2-guess-from-cc),$\
- $$(toolchain-$1-$2-default))
+ toolchain-$1-$2-shell = $\
+ $$(if $$(call defined,$$($1-$2-parameter)),$\
+ $$($$($1-$2-parameter)),$\
+ $$(or $$(toolchain-$1-$2-derive-from-cc),$\
+ $$(toolchain-$1-$2-default)))
toolchain-$1-$2-default = $$(firstword $\
$$(foreach default,$$($1-$2-default),$\
$$(if $$(call which,$$(default)),$$(default))) $\
$$($1-$2-default))
- $1-$2 := $(if $(call which,$$(toolchain-$1-$2-shell)),$\
+ $1-$2 := $$(if $$(call which,$$(toolchain-$1-$2-shell)),$\
$$(call escape-shell,$$(toolchain-$1-$2-shell)),$\
$$(toolchain-$1-$2-shell))
- $1-$2-id := $$(or \
- $$(call toolchain-guess-tool,$$(toolchain-tools-$2),$$($1-$2)),$\
- $$(strip $$(call toolchain-warn-unrecognized,$1,$2)$$($1-$2-default-id)))
+ $1-$2-id := $$(if $$($1-$2),$$(or $\
+ $$(call toolchain-guess-tool,$$\
+ $$(toolchain-tools-$2),$$($1-$2)),$\
+ $$($1-$2-default-id)))
+
+ ifeq ($$(or $$($1-$2-id),$$(call bool,$$($1-$2-optional))),)
+ $$(call toolchain-warn-unrecognized,$1,$2)
+ endif
endef
$(foreach toolchain,$(toolchains), \
diff --git a/make_helpers/toolchains/host.mk b/make_helpers/toolchains/host.mk
index 00a9dd6..dc538c6 100644
--- a/make_helpers/toolchains/host.mk
+++ b/make_helpers/toolchains/host.mk
@@ -37,3 +37,8 @@
host-dtc-parameter := HOSTDTC
host-dtc-default-id := generic-dtc
host-dtc-default := dtc
+
+host-poetry-parameter := POETRY
+host-poetry-optional := yes
+host-poetry-default-id := generic-poetry
+host-poetry-default := poetry
diff --git a/make_helpers/utilities.mk b/make_helpers/utilities.mk
index 45ef12e..efa0ab9 100644
--- a/make_helpers/utilities.mk
+++ b/make_helpers/utilities.mk
@@ -100,3 +100,23 @@
#
bool-01 = $(if $(call bool,$(1)),1,0)
+
+#
+# Determine whether a variable is defined or not.
+#
+# Parameters:
+#
+# - $(1): The variable to check.
+#
+# Example usage:
+#
+# xyz-defined := $(call defined,xyz) # <empty>
+#
+# xyz :=
+# xyz-defined := $(call defined,xyz) # <non-empty>
+#
+# xyz := hello
+# xyz-defined := $(call defined,xyz) # <non-empty>
+#
+
+defined = $(call bool,$(filter-out undefined,$(origin $(1))))
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 1c977a3..3892fcb 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -32,7 +32,7 @@
$(eval $(call add_define,MEM_BASE))
ifndef MEM_SIZE
- $(error "ATF_BASE defined without ATF_SIZE")
+ $(error "MEM_BASE defined without MEM_SIZE")
endif
$(eval $(call add_define,MEM_SIZE))
@@ -45,7 +45,7 @@
$(eval $(call add_define,BL32_MEM_BASE))
ifndef BL32_MEM_SIZE
- $(error "BL32_BASE defined without BL32_SIZE")
+ $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE")
endif
$(eval $(call add_define,BL32_MEM_SIZE))
endif
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts b/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts
new file mode 100644
index 0000000..53cd3b0
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/tbbr/tbbr_img_def.h>
+
+/dts-v1/;
+
+/ {
+ dtb-registry {
+ compatible = "fconf,dyn_cfg-dtb_registry";
+
+ hw-config {
+ load-address = <0x0 0x83000000>;
+ max-size = <0x8000>;
+ id = <HW_CONFIG_ID>;
+ };
+ };
+};
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S b/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S
new file mode 100644
index 0000000..8efe8ac
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <arm_macros.S>
+
+/* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ *
+ * There are currently no platform specific regs
+ * to print.
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h b/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h
new file mode 100644
index 0000000..44c8ee3
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+
+/* These are referenced by arm_def.h #included next, so #define first. */
+#define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x0)
+
+#include <plat/arm/common/arm_def.h>
+#include <plat/arm/css/common/css_def.h>
+#include <plat/common/common_def.h>
+
+#define PLATFORM_CORE_COUNT U(16)
+#define PLAT_ARM_CLUSTER_COUNT U(16)
+#define PLAT_MAX_CPUS_PER_CLUSTER U(1)
+#define PLAT_MAX_PE_PER_CPU U(1)
+
+#define PLATFORM_STACK_SIZE UL(0x1000)
+
+/* BL1 is not supported */
+#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x0)
+#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x0)
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000)
+
+/* USE_ROMLIB is not supported */
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
+
+/* Defined based on actual binary sizes */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0x0
+#define PLAT_ARM_MAX_BL2_SIZE 0x20000
+#define PLAT_ARM_MAX_BL31_SIZE 0x70000
+
+#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
+#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
+
+#define PLAT_CSS_MHU_BASE UL(0x2A920000)
+#define PLAT_ARM_NSTIMER_FRAME_ID U(0)
+
+#define SOC_CSS_SEC_UART_BASE UL(0x2A410000)
+#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000)
+#define SOC_CSS_UART_SIZE UL(0x10000)
+#define SOC_CSS_UART_CLK_IN_HZ UL(7372800)
+#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+
+/* Physical and virtual address space limits for MMU */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE UL(0x30000000)
+#define PLAT_ARM_GICR_BASE UL(0x301C0000)
+#define PLAT_ARM_GICC_BASE UL(0x2C000000)
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+
+/* Virtual address used by dynamic mem_protect for chunk_base */
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
+
+/* Secure Watchdog Constants */
+#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
+#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
+
+#define V2M_SYS_LED_SS_SHIFT U(0)
+#define V2M_SYS_LED_EL_SHIFT U(1)
+#define V2M_SYS_LED_EC_SHIFT U(3)
+
+#define V2M_SYS_LED_SS_MASK U(0x01)
+#define V2M_SYS_LED_EL_MASK U(0x03)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
+
+#define V2M_SYSREGS_BASE UL(0x0C010000)
+#define V2M_SYS_LED U(0x8)
+
+#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1)
+#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+
+#define MAX_IO_DEVICES U(3)
+#define MAX_IO_HANDLES U(4)
+
+#ifdef IMAGE_BL2
+#define PLAT_ARM_MMAP_ENTRIES U(5)
+#else
+#define PLAT_ARM_MMAP_ENTRIES U(6)
+#endif
+#define MAX_XLAT_TABLES U(6)
+
+#define V2M_FLASH0_BASE UL(0x08000000)
+#define V2M_FLASH0_SIZE UL(0x04000000)
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_FW_CONFIG_MAX_SIZE (ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE)
+#define PLAT_FW_CONFIG_BASE ARM_FW_CONFIG_BASE
+
+/* RD1AE-specific memory mappings */
+#define RD1AE_EXTERNAL_FLASH MAP_REGION_FLAT(V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | \
+ MT_SECURE)
+
+#define RD1AE_MAP_NS_DRAM1 MAP_REGION_FLAT(ARM_DRAM1_BASE, \
+ ARM_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | \
+ MT_NS)
+
+#define RD1AE_DEVICE_BASE (0x20000000)
+#define RD1AE_DEVICE_SIZE (0x20000000)
+#define RD1AE_MAP_DEVICE MAP_REGION_FLAT(RD1AE_DEVICE_BASE, \
+ RD1AE_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | \
+ MT_SECURE)
+
+#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
+#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
+#define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT(SOC_PLATFORM_PERIPH_BASE, \
+ SOC_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/* Non-volatile counters */
+#define TRUSTED_NVCTR_BASE_OFFSET UL(0x00E70000)
+#define TFW_NVCTR_BASE_OFFSET 0x0000
+#define NTFW_CTR_BASE_OFFSET 0x0004
+#define SOC_TRUSTED_NVCTR_BASE (SOC_PLATFORM_PERIPH_BASE + TRUSTED_NVCTR_BASE_OFFSET)
+#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + TFW_NVCTR_BASE_OFFSET)
+#define TFW_NVCTR_SIZE U(4)
+#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + NTFW_CTR_BASE_OFFSET)
+#define NTFW_CTR_SIZE U(4)
+
+/*******************************************************************************
+ * Memprotect definitions
+ ******************************************************************************/
+/* PSCI memory protect definitions:
+ * This variable is stored in a non-secure flash because some ARM reference
+ * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
+ * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
+ */
+#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
+ V2M_FLASH0_SIZE - \
+ V2M_FLASH_BLOCK_SIZE)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S b/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S
new file mode 100644
index 0000000..32260ef
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .globl plat_arm_calc_core_pos
+
+ /* ---------------------------------------------------------------------
+ * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
+ *
+ * Function to calculate the core position on rd1ae.
+ *
+ * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
+ * (CPUId * PLAT_MAX_PE_PER_CPU) +
+ * ThreadId
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
+ */
+func plat_arm_calc_core_pos
+ mov x4, x0
+
+ /* Extract individual affinity fields from MPIDR */
+ ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
+
+ /* Compute linear position */
+ mov x4, #PLAT_ARM_CLUSTER_COUNT
+ madd x2, x3, x4, x2
+ mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
+ madd x1, x2, x4, x1
+ mov x4, #PLAT_MAX_PE_PER_CPU
+ madd x0, x1, x4, x0
+ ret
+endfunc plat_arm_calc_core_pos
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
new file mode 100644
index 0000000..35cd8a1
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
@@ -0,0 +1,88 @@
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# RD1AE (Kronos) platform.
+$(info Platform ${PLAT} is (kronos) specific.)
+
+RD1AE_BASE = plat/arm/board/automotive_rd/platform/rd1ae
+
+PLAT_INCLUDES += -I${RD1AE_BASE}/include/
+
+override ARM_FW_CONFIG_LOAD_ENABLE := 1
+override ARM_PLAT_MT := 1
+override ARM_RECOM_STATE_ID_ENC := 1
+override CSS_LOAD_SCP_IMAGES := 0
+override CTX_INCLUDE_AARCH32_REGS := 0
+override ENABLE_SVE_FOR_NS := 1
+override ENABLE_SVE_FOR_SWD := 1
+override NEED_BL1 := 0
+override NEED_BL2U := 0
+override PSCI_EXTENDED_STATE_ID := 1
+
+ARM_ARCH_MAJOR := 9
+ARM_ARCH_MINOR := 2
+CSS_USE_SCMI_SDS_DRIVER := 1
+ENABLE_FEAT_AMU := 1
+ENABLE_FEAT_ECV := 1
+ENABLE_FEAT_FGT := 1
+ENABLE_FEAT_MTE2 := 1
+ENABLE_MPAM_FOR_LOWER_ELS := 1
+GIC_ENABLE_V4_EXTN := 1
+GICV3_SUPPORT_GIC600 := 1
+HW_ASSISTED_COHERENCY := 1
+PLAT_MHU_VERSION := 1
+RESET_TO_BL2 := 1
+SVE_VECTOR_LEN := 128
+USE_COHERENT_MEM := 0
+
+RD1AE_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S
+
+include drivers/arm/gic/v3/gicv3.mk
+RD1AE_GIC_SOURCES := ${GICV3_SOURCES} \
+ plat/common/plat_gicv3.c \
+ plat/arm/common/arm_gicv3.c
+
+PLAT_BL_COMMON_SOURCES += ${RD1AE_BASE}/rd1ae_plat.c \
+ ${RD1AE_BASE}/include/rd1ae_helpers.S
+
+BL2_SOURCES += ${RD1AE_CPU_SOURCES} \
+ ${RD1AE_BASE}/rd1ae_err.c \
+ ${RD1AE_BASE}/rd1ae_bl2_mem_params_desc.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c \
+ drivers/arm/sbsa/sbsa.c
+
+BL31_SOURCES += ${RD1AE_CPU_SOURCES} \
+ ${RD1AE_GIC_SOURCES} \
+ ${RD1AE_BASE}/rd1ae_bl31_setup.c \
+ ${RD1AE_BASE}/rd1ae_topology.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+BL2_SOURCES += ${RD1AE_BASE}/rd1ae_tbb.c
+endif
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${RD1AE_BASE}/fdts/${PLAT}_fw_config.dts \
+ fdts/${PLAT}.dts
+
+FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
+
+# Add the FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+FIP_BL2_ARGS := tb-fw
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+
+include plat/arm/common/arm_common.mk
+include plat/arm/css/common/css_common.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c
new file mode 100644
index 0000000..30cc90f
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#include <platform_def.h>
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+#if DEBUG
+ .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
+#endif
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+ /* Fill HW_CONFIG related information */
+ {
+ .image_id = HW_CONFIG_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ NON_SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ /* Fill BL33 related information */
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+ .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+ - PLAT_ARM_NS_IMAGE_BASE,
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c
new file mode 100644
index 0000000..ce7bad7
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/css/css_mhu_doorbell.h>
+#include <drivers/arm/css/scmi.h>
+
+static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+ .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+};
+
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
+{
+ return &plat_rd_scmi_info[channel_id];
+}
+
+const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+{
+ return css_scmi_override_pm_ops(ops);
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c
new file mode 100644
index 0000000..6254473
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/sbsa.h>
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * rd1ae error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+ console_flush();
+
+ sbsa_wdog_refresh(SBSA_SECURE_WDOG_BASE);
+
+ while (1) {
+ wfi();
+ }
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c
new file mode 100644
index 0000000..e917330
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/arm/sbsa.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ RD1AE_MAP_DEVICE,
+ RD1AE_EXTERNAL_FLASH,
+ SOC_PLATFORM_PERIPH_MAP_DEVICE,
+#if IMAGE_BL2
+ RD1AE_MAP_NS_DRAM1,
+#endif
+ {0}
+};
+
+void plat_arm_secure_wdt_start(void)
+{
+ sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+}
+
+void plat_arm_secure_wdt_stop(void)
+{
+ sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+}
+
+/*
+ * For rd1ae we should not do anything in these interface functions.
+ * They are used to override the weak functions in cci drivers
+ */
+void plat_arm_interconnect_init(void)
+{
+}
+
+void plat_arm_interconnect_enter_coherency(void)
+{
+}
+
+void plat_arm_interconnect_exit_coherency(void)
+{
+}
+
+/*
+ * TZC programming is currently not done.
+ */
+void plat_arm_security_setup(void)
+{
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c
new file mode 100644
index 0000000..01fbcce
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+
+/*
+ * Return the ROTPK hash in the following ASN.1 structure in DER format:
+ *
+ * AlgorithmIdentifier ::= SEQUENCE {
+ * algorithm OBJECT IDENTIFIER,
+ * parameters ANY DEFINED BY algorithm OPTIONAL
+ * }
+ *
+ * DigestInfo ::= SEQUENCE {
+ * digestAlgorithm AlgorithmIdentifier,
+ * digest OCTET STRING
+ * }
+ */
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c
new file mode 100644
index 0000000..2533184
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ *
+ * This descriptor defines the layout of the power domain tree for the RD1AE
+ * platform, which consists of 16 clusters.
+ ******************************************************************************/
+const unsigned char rd1_ae_pd_tree_desc[] = {
+ (PLAT_ARM_CLUSTER_COUNT),
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return rd1_ae_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
+};
+
+unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
+{
+ return PLAT_MAX_CPUS_PER_CLUSTER;
+}
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
index 1b92ec2..3fbc125 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
@@ -111,4 +111,18 @@
ARM_REALM_SIZE, \
MT_MEMORY | MT_RW | MT_REALM)
+#if RESET_TO_BL31
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+
+/* Define the DTB image base and size */
+#define NRD_CSS_BL31_PRELOAD_DTB_BASE UL(0xF3000000)
+#define NRD_CSS_BL31_PRELOAD_DTB_SIZE UL(0x1000)
+#define NRD_CSS_MAP_BL31_DTB MAP_REGION_FLAT( \
+ NRD_CSS_BL31_PRELOAD_DTB_BASE, \
+ NRD_CSS_BL31_PRELOAD_DTB_SIZE, \
+ MT_RW_DATA | MT_NS)
+#endif /* RESET_TO_BL31 */
+
#endif /* NRD_CSS_FW_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
index 0dce512..8d6d1cb 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
@@ -56,8 +56,8 @@
* chips are accessed - secure ram, css device and soc device regions.
*/
#if defined(IMAGE_BL31)
-# define PLAT_ARM_MMAP_ENTRIES (9 + ((NRD_CHIP_COUNT - 1) * 3))
-# define MAX_XLAT_TABLES (9 + ((NRD_CHIP_COUNT - 1) * 3))
+# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (10 + ((NRD_CHIP_COUNT - 1) * 3))
#elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES U(8)
# define MAX_XLAT_TABLES U(5)
@@ -442,7 +442,7 @@
* SRAM layout
******************************************************************************/
-/*
+/* if !RESET_TO_BL31
* Trusted SRAM
* 0x00100000 +--------------+
* | L0 GPT |
@@ -460,6 +460,26 @@
* 0x00019000 +--------------+
* | BL1 (ro) |
* 0x00000000 +--------------+
+ *
+ * else
+ *
+ * Trusted SRAM
+ * 0x00100000 +--------------+
+ * | L0 GPT |
+ * 0x000E0000 +--------------
+ * | | side-loaded +----------------+
+ * | | <<<<<<<<<<<<< | |
+ * | | <<<<<<<<<<<<< | BL31 NOBITS |
+ * | | <<<<<<<<<<<<< | |
+ * | | <<<<<<<<<<<<< |----------------|
+ * | | <<<<<<<<<<<<< | BL31 PROGBITS |
+ * 0x00063000 | | +----------------+
+ * 0x0001A000 +--------------+
+ * | Shared |
+ * 0x00019000 +--------------+
+ * | BL1 (ro) |
+ * 0x00000000 +--------------+
+ * endif
*/
/*******************************************************************************
@@ -531,7 +551,11 @@
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2)
+#if RESET_TO_BL31
+#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE)
+#else
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
+#endif
/*******************************************************************************
* BL1 RW specifics
@@ -556,9 +580,13 @@
******************************************************************************/
/* Keep BL31 below BL2 in the Trusted SRAM.*/
+#if RESET_TO_BL31
+#define BL31_BASE (0x63000)
+#else
#define BL31_BASE ((ARM_BL_RAM_BASE + \
ARM_BL_RAM_SIZE) - \
PLAT_ARM_MAX_BL31_SIZE)
+#endif
#define BL31_PROGBITS_LIMIT BL2_BASE
#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
diff --git a/plat/arm/board/neoverse_rd/common/nrd-common.mk b/plat/arm/board/neoverse_rd/common/nrd-common.mk
index 95a221f..a09f369 100644
--- a/plat/arm/board/neoverse_rd/common/nrd-common.mk
+++ b/plat/arm/board/neoverse_rd/common/nrd-common.mk
@@ -54,11 +54,6 @@
${NRD_COMMON_BASE}/nrd_topology.c \
drivers/delay_timer/generic_delay_timer.c
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
$(eval $(call add_define,NRD_CHIP_COUNT))
$(eval $(call add_define,NRD_PLATFORM_VARIANT))
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index 18aa2fb..bce8834 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -155,6 +155,65 @@
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
}
+/*******************************************************************************
+ * This function inserts platform information via device tree nodes as,
+ * system-id {
+ * platform-id = <0>;
+ * config-id = <0>;
+ * }
+ ******************************************************************************/
+#if RESET_TO_BL31
+static int append_config_node(uintptr_t fdt_base_addr, uintptr_t fdt_base_size)
+{
+ void *fdt;
+ int nodeoffset, err;
+ unsigned int platid = 0, platcfg = 0;
+
+ if (fdt_base_addr == 0) {
+ ERROR("NT_FW CONFIG base address is NULL\n");
+ return -1;
+ }
+
+ fdt = (void *)fdt_base_addr;
+
+ /* Check the validity of the fdt */
+ if (fdt_check_header(fdt) != 0) {
+ ERROR("Invalid NT_FW_CONFIG DTB passed\n");
+ return -1;
+ }
+
+ nodeoffset = fdt_subnode_offset(fdt, 0, "system-id");
+ if (nodeoffset < 0) {
+ ERROR("Failed to get system-id node offset\n");
+ return -1;
+ }
+
+ platid = plat_arm_nrd_get_platform_id();
+ err = fdt_setprop_u32(fdt, nodeoffset, "platform-id", platid);
+ if (err < 0) {
+ ERROR("Failed to set platform-id\n");
+ return -1;
+ }
+
+ platcfg = plat_arm_nrd_get_config_id();
+ err = fdt_setprop_u32(fdt, nodeoffset, "config-id", platcfg);
+ if (err < 0) {
+ ERROR("Failed to set config-id\n");
+ return -1;
+ }
+
+ platcfg = plat_arm_nrd_get_multi_chip_mode();
+ err = fdt_setprop_u32(fdt, nodeoffset, "multi-chip-mode", platcfg);
+ if (err < 0) {
+ ERROR("Failed to set multi-chip-mode\n");
+ return -1;
+ }
+
+ flush_dcache_range((uintptr_t)fdt, fdt_base_size);
+ return 0;
+}
+#endif
+
void nrd_bl31_common_platform_setup(void)
{
generic_delay_timer_init();
@@ -169,6 +228,15 @@
ehf_register_priority_handler(PLAT_REBOOT_PRI,
css_reboot_interrupt_handler);
#endif
+
+#if RESET_TO_BL31
+ int ret = append_config_node(NRD_CSS_BL31_PRELOAD_DTB_BASE,
+ NRD_CSS_BL31_PRELOAD_DTB_SIZE);
+
+ if (ret != 0) {
+ panic();
+ }
+#endif
}
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat3.c b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
index 7b98052..00f346e 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat3.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
@@ -60,6 +60,9 @@
NRD_CSS_GPT_L1_DRAM_MMAP,
NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
+#if RESET_TO_BL31
+ NRD_CSS_MAP_BL31_DTB,
+#endif
{0}
};
#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
index 15fc9bb..4892804 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
@@ -71,6 +71,11 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override CTX_INCLUDE_AARCH32_REGS := 0
override SPMD_SPM_AT_SEL2 := 0
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
index c8f0899..c2dfba6 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
@@ -103,6 +103,11 @@
$(eval $(call TOOL_ADD_PAYLOAD,${TOS_FW_CONFIG},--tos-fw-config,${TOS_FW_CONFIG}))
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_FEAT_AMU := 2
override ENABLE_FEAT_MTE2 := 2
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
index fe87779..db8efbb 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
@@ -66,5 +66,10 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
# Enable the flag since RD-V1 has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
index a0a1204..6d518d5 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
@@ -77,5 +77,10 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
# Enable the flag since RD-V1-MC has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
index 98029bb..f37d903 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
@@ -24,6 +24,24 @@
# Misc options
override CTX_INCLUDE_AARCH32_REGS := 0
+ifeq (${PLAT_RESET_TO_BL31}, 1)
+# Support for BL31 boot flow
+override RESET_TO_BL31 := 1
+
+# arm_common.mk sets ENABLE_PIE=1, but Makefile blocks PIE for RME
+override ENABLE_PIE := 0
+
+# Non Trusted Firmware parameters
+override ARM_PRELOADED_DTB_BASE := 0xF3000000
+override ARM_LINUX_KERNEL_AS_BL33 := 1
+override PRELOADED_BL33_BASE := 0xE0000000
+
+# These are internal build flags but as of now RESET_TO_BL31 won't work without defining them
+override NEED_BL1 := no
+override NEED_BL2 := no
+override NEED_BL32 := no
+endif
+
# RD-V3 platform uses GIC-700 which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
@@ -86,6 +104,10 @@
${RDV3_BASE}/rdv3_bl2_measured_boot.c
endif
+ifeq (${PLAT_RESET_TO_BL31}, 1)
+BL31_SOURCES += ${RDV3_BASE}/rdv3_security.c
+endif
+
BL31_SOURCES += ${NRD_CPU_SOURCES} \
${MBEDTLS_SOURCES} \
${RSE_COMMS_SOURCES} \
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
index 21675f6..a5d687e 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
@@ -130,3 +130,92 @@
WARN("Failed initializing AP-RSE comms.\n");
}
}
+
+#if RESET_TO_BL31
+/*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+static pas_region_t pas_regions[] = {
+ NRD_PAS_SHARED_SRAM,
+ NRD_PAS_SYSTEM_NCI,
+ NRD_PAS_DEBUG_NIC,
+ NRD_PAS_NS_UART,
+ NRD_PAS_REALM_UART,
+ NRD_PAS_AP_NS_WDOG,
+ NRD_PAS_AP_ROOT_WDOG,
+ NRD_PAS_AP_SECURE_WDOG,
+ NRD_PAS_SECURE_SRAM_ERB_AP,
+ NRD_PAS_NS_SRAM_ERB_AP,
+ NRD_PAS_ROOT_SRAM_ERB_AP,
+ NRD_PAS_REALM_SRAM_ERB_AP,
+ NRD_PAS_SECURE_SRAM_ERB_SCP,
+ NRD_PAS_NS_SRAM_ERB_SCP,
+ NRD_PAS_ROOT_SRAM_ERB_SCP,
+ NRD_PAS_REALM_SRAM_ERB_SCP,
+ NRD_PAS_SECURE_SRAM_ERB_MCP,
+ NRD_PAS_NS_SRAM_ERB_MCP,
+ NRD_PAS_ROOT_SRAM_ERB_MCP,
+ NRD_PAS_REALM_SRAM_ERB_MCP,
+ NRD_PAS_SECURE_SRAM_ERB_RSE,
+ NRD_PAS_NS_SRAM_ERB_RSE,
+ NRD_PAS_ROOT_SRAM_ERB_RSE,
+ NRD_PAS_REALM_SRAM_ERB_RSE,
+ NRD_PAS_RSE_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_RSE_NS_SRAM_ERB_RSM,
+ NRD_PAS_SCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_SCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_MCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_MCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_AP_SCP_ROOT_MHU,
+ NRD_PAS_AP_MCP_NS_MHU,
+ NRD_PAS_AP_MCP_SECURE_MHU,
+ NRD_PAS_AP_MCP_ROOT_MHU,
+ NRD_PAS_AP_RSE_NS_MHU,
+ NRD_PAS_AP_RSE_SECURE_MHU,
+ NRD_PAS_AP_RSE_ROOT_MHU,
+ NRD_PAS_AP_RSE_REALM_MHU,
+ NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU,
+ NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR,
+ NRD_PAS_STM_SYSTEM_ITS,
+ NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
+ NRD_PAS_GIC,
+ NRD_PAS_NS_DRAM,
+ NRD_PAS_RMM,
+ NRD_PAS_L1GPT,
+ NRD_PAS_CMN,
+ NRD_PAS_LCP_PERIPHERAL,
+ NRD_PAS_DDR_IO,
+ NRD_PAS_SMMU_NCI_IO,
+ NRD_PAS_DRAM2_CHIP0,
+#if NRD_CHIP_COUNT > 1
+ NRD_PAS_DRAM1_CHIP1,
+ NRD_PAS_DRAM2_CHIP1,
+#endif
+#if NRD_CHIP_COUNT > 2
+ NRD_PAS_DRAM1_CHIP2,
+ NRD_PAS_DRAM2_CHIP2,
+#endif
+#if NRD_CHIP_COUNT > 3
+ NRD_PAS_DRAM1_CHIP3,
+ NRD_PAS_DRAM2_CHIP3
+#endif
+};
+
+static const arm_gpt_info_t arm_gpt_info = {
+ .pas_region_base = pas_regions,
+ .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
+ .l0_base = (uintptr_t)ARM_L0_GPT_BASE,
+ .l1_base = (uintptr_t)ARM_L1_GPT_BASE,
+ .l0_size = (size_t)ARM_L0_GPT_SIZE,
+ .l1_size = (size_t)ARM_L1_GPT_SIZE,
+ .pps = GPCCR_PPS_256TB,
+ .pgs = GPCCR_PGS_4K
+};
+
+const arm_gpt_info_t *plat_arm_get_gpt_info(void)
+{
+ return &arm_gpt_info;
+}
+
+#endif /* RESET_TO_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
index 37306be..1f40107 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
@@ -65,4 +65,9 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override SPMD_SPM_AT_SEL2 := 0
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index 01e0db0..869830d 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,8 @@
#include <drivers/generic_delay_timer.h>
#include <drivers/partition/partition.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -64,6 +66,43 @@
generic_delay_timer_init();
}
+#if ARM_FW_CONFIG_LOAD_ENABLE
+/*************************************************************************************
+ * FW CONFIG load function for BL2 when RESET_TO_BL2=1 && ARM_FW_CONFIG_LOAD_ENABLE=1
+ *************************************************************************************/
+void arm_bl2_el3_plat_config_load(void)
+{
+ int ret;
+ const struct dyn_cfg_dtb_info_t *fw_config_info;
+
+ /* Set global DTB info for fixed fw_config information */
+ set_config_info(PLAT_FW_CONFIG_BASE, ~0UL, PLAT_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
+
+ /* Fill the device tree information struct with the info from the config dtb */
+ ret = fconf_load_config(FW_CONFIG_ID);
+ if (ret < 0) {
+ ERROR("Loading of FW_CONFIG failed %d\n", ret);
+ plat_error_handler(ret);
+ }
+
+ /*
+ * FW_CONFIG loaded successfully. Check the FW_CONFIG device tree parsing
+ * is successful.
+ */
+ fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
+ if (fw_config_info == NULL) {
+ ret = -1;
+ ERROR("Invalid FW_CONFIG address\n");
+ plat_error_handler(ret);
+ }
+ ret = fconf_populate_dtb_registry(fw_config_info->config_addr);
+ if (ret < 0) {
+ ERROR("Parsing of FW_CONFIG failed %d\n", ret);
+ plat_error_handler(ret);
+ }
+}
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
+
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only initializes the mmu in a quick and dirty way.
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index b5a7db1..90ee70c 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -42,7 +42,7 @@
#if TRANSFER_LIST
CASSERT(BL2_BASE >= PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE,
assert_bl2_base_overflows);
-#else
+#elif !RESET_TO_BL2
CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
#endif /* TRANSFER_LIST */
@@ -140,6 +140,9 @@
arm_transfer_list_dyn_cfg_init(secure_tl);
#else
+#if ARM_FW_CONFIG_LOAD_ENABLE
+ arm_bl2_el3_plat_config_load();
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
arm_bl2_dyn_cfg_init();
#endif
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 65023bf..3650854 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -7,6 +7,7 @@
#include <assert.h>
#include <arch.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -544,6 +545,13 @@
enable_mmu_el3(0);
#if ENABLE_RME
+#if RESET_TO_BL31
+ /* initialize GPT only when RME is enabled. */
+ assert(is_feat_rme_present());
+
+ /* Initialise and enable granule protection after MMU. */
+ arm_gpt_setup();
+#endif /* RESET_TO_BL31 */
/*
* Initialise Granule Protection library and enable GPC for the primary
* processor. The tables have already been initialized by a previous BL
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 0c9b943..2fd993c 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -164,6 +164,25 @@
ENABLE_PIE := 1
endif
+# On Arm platform, disable ARM_FW_CONFIG_LOAD_ENABLE by default.
+ARM_FW_CONFIG_LOAD_ENABLE := 0
+$(eval $(call assert_boolean,ARM_FW_CONFIG_LOAD_ENABLE))
+$(eval $(call add_define,ARM_FW_CONFIG_LOAD_ENABLE))
+
+# In order to enable ARM_FW_CONFIG_LOAD_ENABLE for the Arm platform, the
+# platform should be reset to BL2 (RESET_TO_BL2=1), and FW_CONFIG must be
+# specified.
+ifeq (${ARM_FW_CONFIG_LOAD_ENABLE},1)
+ ifneq (${RESET_TO_BL2},1)
+ $(error RESET_TO_BL2 must be enabled when ARM_FW_CONFIG_LOAD_ENABLE \
+ is enabled)
+ endif
+ ifeq (${FW_CONFIG},)
+ $(error FW_CONFIG must be specified when ARM_FW_CONFIG_LOAD_ENABLE \
+ is enabled)
+ endif
+endif
+
# Disable GPT parser support, use FIP image by default
ARM_GPT_SUPPORT := 0
$(eval $(call assert_boolean,ARM_GPT_SUPPORT))
@@ -275,7 +294,7 @@
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
else
-ifneq (${PLAT}, corstone1000)
+ifeq ($(filter $(PLAT), corstone1000 rd1ae),)
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
endif
endif
@@ -484,8 +503,8 @@
$(q)$($(ARCH)-cpp) $(cot-dt-cpp-flags)
$(BUILD_PLAT)/$(COTDTPATH:.dtsi=.c): $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.dts) | $$(@D)/
- $(q)poetry -q install
- $(q)poetry run cot-dt2c convert-to-c $< $@
+ $(if $(host-poetry),$(q)poetry -q install)
+ $(q)$(if $(host-poetry),poetry run )cot-dt2c convert-to-c $< $@
BL2_SOURCES += $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.c)
endif
diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index 316ed2c..7dc287d 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -15,6 +15,10 @@
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
+# Flag to apply S32 erratum ERR051700. This erratum applies to all S32
+# revisions.
+S32_ERRATA_LIST += ERRATA_S32_051700
+
PLAT_INCLUDES = \
-I${PLAT_S32G274ARDB2}/include
@@ -32,6 +36,7 @@
ERRATA_A53_836870 := 1
ERRATA_A53_1530924 := 1
ERRATA_SPECULATIVE_AT := 1
+ERRATA_S32_051700 := 1
# Selecting Drivers for SoC
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
@@ -39,7 +44,6 @@
include ${PLAT_DRIVERS_PATH}/drivers.mk
-
BL_COMMON_SOURCES += \
${PLAT_S32G274ARDB2}/plat_console.c \
${PLAT_S32G274ARDB2}/plat_helpers.S \
@@ -64,3 +68,8 @@
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
+
+# process all errata flags
+$(eval $(call default_zeros, $(S32_ERRATA_LIST)))
+$(eval $(call add_defines, $(S32_ERRATA_LIST)))
+$(eval $(call assert_booleans, $(S32_ERRATA_LIST)))
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 1cbf51b..282f53f 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -243,7 +243,11 @@
return 0U;
}
+#ifdef __aarch64__
+ size = (size_t)fdt_read_uint64_default(fdt, node, "st,mem-size", 0ULL);
+#else /* __aarch64__ */
size = (size_t)fdt_read_uint32_default(fdt, node, "st,mem-size", 0U);
+#endif /* __aarch64__ */
flush_dcache_range((uintptr_t)&size, sizeof(size_t));
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 6cc28e1..e65800e 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -22,7 +22,7 @@
$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
ifndef VERSAL_ATF_MEM_SIZE
- $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
+ $(error "VERSAL_ATF_MEM_BASE defined without VERSAL_ATF_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
@@ -35,7 +35,7 @@
$(eval $(call add_define,VERSAL_BL32_MEM_BASE))
ifndef VERSAL_BL32_MEM_SIZE
- $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
+ $(error "VERSAL_BL32_MEM_BASE defined without VERSAL_BL32_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
endif
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index da91abc..40e9206 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -34,7 +34,7 @@
$(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE))
ifndef VERSAL_NET_ATF_MEM_SIZE
- $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE")
+ $(error "VERSAL_NET_ATF_MEM_BASE defined without VERSAL_NET_ATF_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE))
@@ -47,7 +47,7 @@
$(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE))
ifndef VERSAL_NET_BL32_MEM_SIZE
- $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE")
+ $(error "VERSAL_NET_BL32_MEM_BASE defined without VERSAL_NET_BL32_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE))
endif
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 22eceb6..9fdc649 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -39,7 +39,7 @@
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
ifndef ZYNQMP_ATF_MEM_SIZE
- $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE")
+ $(error "ZYNQMP_ATF_MEM_BASE defined without ZYNQMP_ATF_MEM_SIZE")
endif
$(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
@@ -56,7 +56,7 @@
$(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
ifndef ZYNQMP_BL32_MEM_SIZE
- $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE")
+ $(error "ZYNQMP_BL32_MEM_BASE defined without ZYNQMP_BL32_MEM_SIZE")
endif
$(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
endif
diff --git a/services/std_svc/spm/el3_spmc/spmc_setup.c b/services/std_svc/spm/el3_spmc/spmc_setup.c
index 4360832..f7357f1 100644
--- a/services/std_svc/spm/el3_spmc/spmc_setup.c
+++ b/services/std_svc/spm/el3_spmc/spmc_setup.c
@@ -386,7 +386,7 @@
write_el1_ctx_common(get_el1_sysregs_ctx(ctx), vbar_el1,
SPM_SHIM_EXCEPTIONS_PTR);
#if NS_TIMER_SWITCH
- write_el1_ctx_common(get_el1_sysregs_ctx(ctx), cntkctl_el1,
+ write_el1_ctx_arch_timer(get_el1_sysregs_ctx(ctx), cntkctl_el1,
EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
#endif