feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED
Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SME specific setup.
Change the FVP platform default to the now supported dynamic option
(=2),so the right decision can be made by the code at runtime.
Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 12f3e6d..7fbbd81 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -489,10 +489,11 @@
amu_enable(el2_unused, ctx);
}
-#if ENABLE_SME_FOR_NS
/* Enable SME, SVE, and FPU/SIMD for non-secure world. */
- sme_enable(ctx);
-#elif ENABLE_SVE_FOR_NS
+ if (is_feat_sme_supported()) {
+ sme_enable(ctx);
+ }
+#if ENABLE_SVE_FOR_NS
/* Enable SVE and FPU/SIMD for non-secure world. */
sve_enable(ctx);
#endif
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index ec8cca8..1846e00 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,28 +7,13 @@
#include <stdbool.h>
#include <arch.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/extensions/sme.h>
#include <lib/extensions/sve.h>
-static bool feat_sme_supported(void)
-{
- uint64_t features;
-
- features = read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SME_SHIFT;
- return (features & ID_AA64PFR1_EL1_SME_MASK) != 0U;
-}
-
-static bool feat_sme_fa64_supported(void)
-{
- uint64_t features;
-
- features = read_id_aa64smfr0_el1();
- return (features & ID_AA64SMFR0_EL1_FA64_BIT) != 0U;
-}
-
void sme_enable(cpu_context_t *context)
{
u_register_t reg;
@@ -36,7 +21,7 @@
el3_state_t *state;
/* Make sure SME is implemented in hardware before continuing. */
- if (!feat_sme_supported()) {
+ if (!is_feat_sme_supported()) {
/* Perhaps the hardware supports SVE only */
sve_enable(context);
return;
@@ -66,7 +51,7 @@
* using SMCR_EL2 and SMCR_EL1.
*/
reg = SMCR_ELX_LEN_MASK;
- if (feat_sme_fa64_supported()) {
+ if (read_feat_sme_fa64_id_field() != 0U) {
VERBOSE("[SME] FA64 enabled\n");
reg |= SMCR_ELX_FA64_BIT;
}
@@ -86,7 +71,7 @@
el3_state_t *state;
/* Make sure SME is implemented in hardware before continuing. */
- if (!feat_sme_supported()) {
+ if (!is_feat_sme_supported()) {
/* Perhaps the hardware supports SVE only */
sve_disable(context);
return;