Merge "docs(changelog): changelog for v2.12 release" into integration
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index dea1825..c414b1f 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -28,15 +28,15 @@
======================== =====================
Arm Compiler 6.18
Arm GNU Compiler 13.3
-Clang/LLVM 11.0.0
-Device Tree Compiler 1.4.7
+Clang/LLVM 18.1.8
+Device Tree Compiler 1.6.1
GNU make 3.81
mbed TLS\ [#f1]_ 3.6.1
Node.js [#f2]_ 16
OpenSSL 1.0.0
Poetry 1.3.2
QCBOR\ [#f3]_ 1.2
-Sphinx\ [#f2]_ 2.4.4
+Sphinx\ [#f2]_ 5.3.0
======================== =====================
.. [#f1] Required for Trusted Board Boot and Measured Boot.
diff --git a/docs/plat/arm/fvp/fvp-support.rst b/docs/plat/arm/fvp/fvp-support.rst
index 5292d68..ad76cf1 100644
--- a/docs/plat/arm/fvp/fvp-support.rst
+++ b/docs/plat/arm/fvp/fvp-support.rst
@@ -11,8 +11,8 @@
.. note::
The FVP models used are Version 11.26 Build 11, unless otherwise stated.
-- ``FVP_Base_AEMvA``
- ``FVP_Base_AEMvA-AEMvA``
+- ``FVP_Base_RevC-2xAEMvA``
- ``FVP_Base_Cortex-A32x4``
- ``FVP_Base_Cortex-A35x4``
- ``FVP_Base_Cortex-A53x4``
@@ -40,11 +40,12 @@
- ``FVP_Base_Neoverse-N1``
- ``FVP_Base_Neoverse-N2``
- ``FVP_Base_Neoverse-V1``
-- ``FVP_Base_RevC-2xAEMv8A``
- ``FVP_BaseR_AEMv8R``
- ``FVP_Morello`` (Version 0.11/33)
- ``FVP_RD_V1``
-- ``FVP_TC2`` (Version 11.23/17)
+- ``FVP_RD_1_AE`` (Version 11.27/20)
+- ``FVP_TC3`` (Version 11.26/16)
+- ``FVP_TC4`` (Version 0.0/8404)
The latest version of the AArch32 build of TF-A has been tested on the
following Arm FVPs without shifted affinities, and that do not support threaded
diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst
index 9469e9a..467738c 100644
--- a/docs/plat/arm/tc/index.rst
+++ b/docs/plat/arm/tc/index.rst
@@ -13,13 +13,15 @@
- SCMI
- MHUv2
-Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1
-(TARGET_PLATFORM=1), TC2 (TARGET_PLATFORM=2) platforms w.r.t to TF-A
-is the CPUs supported as below:
+The TF-A build is specified by the option `TARGET_PLATFORM` which represents
+the Total Compute platform number. The platforms support the CPU variants
+listed as below:
- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
- TC1 has support for Cortex A510, Cortex A715 and Cortex X3. (Note TC1 is now deprecated)
-- TC2 has support for Cortex A520, Cortex A720 and Cortex x4.
+- TC2 has support for Cortex A520, Cortex A720 and Cortex x4. (Note TC2 is now deprecated)
+- TC3 has support for Cortex A520, Cortex A725 and Cortex x925.
+
Boot Sequence
-------------
@@ -43,7 +45,7 @@
.. code:: shell
make PLAT=tc BL33=<path_to_uboot.bin> \
- SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1,2} all fip
+ SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={3} all fip
Enable TBBR by adding the following options to the make command:
diff --git a/fdts/stm32mp15xx-dhcom-som.dtsi b/fdts/stm32mp15xx-dhcom-som.dtsi
index 12846db..46ef0f0 100644
--- a/fdts/stm32mp15xx-dhcom-som.dtsi
+++ b/fdts/stm32mp15xx-dhcom-som.dtsi
@@ -195,7 +195,7 @@
CLK_MCU_PLL3P
CLK_RTC_LSE
CLK_MCO1_DISABLED
- CLK_MCO2_PLL4P
+ CLK_MCO2_PLL4
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK