fix(intel): update warm reset routine and bootscratch register usage
Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.
Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.
Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index c090117..1ad28e1 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -234,9 +234,9 @@
unsigned int pchctlr_new = 0x00;
uint32_t boot_core = 0x00;
- /* Store magic number for SMP secondary cores boot */
- mmio_write_32(L2_RESET_DONE_REG, SMP_SEC_CORE_BOOT_REQ);
-
+ /* Set bit for SMP secondary cores boot */
+ mmio_clrsetbits_32(L2_RESET_DONE_REG, BS_REG_MAGIC_KEYS_MASK,
+ SMP_SEC_CORE_BOOT_REQ);
boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00);
/* Update the p-channel based on cpu id */
pch_cpu = 1 << cpu_id;