diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..92fd25f
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mt_gic_v3.h>
+#include <plat_mt_cirq.h>
+#endif
+
+#define CONSTRAINT_BUS26M_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_VCORE_LP |	\
+	 MT_RM_CONSTRAINT_ALLOW_LVTS_STATE |	\
+	 MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_ENABLE_TIA_WORKAROUND |	\
+	 SPM_FLAG_ENABLE_LVTS_WORKAROUND |	\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1		\
+	(SPM_FLAG1_DISABLE_MD26M_CK_OFF)
+
+#define CONSTRAINT_BUS26M_RESOURCE_REQ		0U
+
+static unsigned int bus26m_ext_opand;
+static struct mt_irqremain *refer2remain_irq;
+static struct mt_spm_cond_tables cond_bus26m = {
+	.name = "bus26m",
+	.table_cg = {
+		0x07CBF1FC,	/* MTCMOS1 */
+		0x0A0D8856,	/* INFRA0  */
+		0x03AF9A00,	/* INFRA1  */
+		0x86000650,	/* INFRA2  */
+		0xC800C000,	/* INFRA3  */
+		0x00000000,     /* INFRA4  */
+		0x4000007C,     /* INFRA5  */
+		0x280E0800,	/* MMSYS0  */
+		0x00000001,     /* MMSYS1  */
+		0x00000000,	/* MMSYS2  */
+	},
+	.table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
+		      PLL_BIT_MSDCPLL | PLL_BIT_TVDPLL |
+		      PLL_BIT_MMPLL),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_BUS26M,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_bus26m_res,
+};
+
+/*
+ * Cirq will take the place of gic when gic is off.
+ * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
+ * Therefore, we need to set irq pending for specific wakeup source.
+ */
+#ifdef ATF_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+				   unsigned int irq_index,
+				   struct wake_status *wakeup)
+{
+	INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
+	     wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
+	     wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
+	     wakeup->tr.comm.b_sw_flag1);
+
+	INFO("irq:%u(0x%08x) set pending\n",
+	     irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+	unsigned int idx;
+	int res = 0;
+	struct wake_status *wakeup = NULL;
+	struct mt_irqremain *irqs = refer2remain_irq;
+
+	res = spm_conservation_get_result(&wakeup);
+
+	if ((res != 0) && (irqs == NULL)) {
+		return;
+	}
+
+	for (idx = 0U; idx < irqs->count; ++idx) {
+		if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+		    ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+			if ((irqs->wakeupsrc_cat[idx] &
+			     MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+				mt_spm_irq_remain_dump(irqs, idx, wakeup);
+			}
+
+			mt_irq_set_pending(irqs->irqs[idx]);
+		}
+	}
+}
+#endif
+
+static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp,
+			       unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	if (type == PLAT_RC_UPDATE_CONDITION) {
+		tlb = (const struct mt_spm_cond_tables *)val;
+		tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+		status.cond_block =
+			mt_spm_cond_check(state_id, tlb, tlb_check,
+					  ((status.valid &
+					    MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+					  &cond_bus26m_res : NULL);
+	} else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
+		refer2remain_irq = (struct mt_irqremain *)val;
+	} else {
+		res = MT_RM_STATUS_BAD;
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      bus26m_ext_opand),
+				     CONSTRAINT_BUS26M_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT,
+					  spm_bus26m_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
+		mt_spm_suspend_resume(state_id, ext_op, NULL);
+		bus26m_ext_opand = 0U;
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+		status.enter_cnt++;
+	}
+
+	do_irqs_delivery();
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..9618f3b
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1		0U
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ	\
+	(MT_SPM_DRAM_S1 |			\
+	 MT_SPM_DRAM_S0 |			\
+	 MT_SPM_SYSPLL |			\
+	 MT_SPM_INFRA |				\
+	 MT_SPM_26M |				\
+	 MT_SPM_XO_FPM)
+
+
+static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
+static unsigned int cpubuckldo_enter_cnt;
+
+static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
+				     unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+	(void)state_id;
+
+	return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     MT_SPM_EX_OP_SET_WDT,
+				     CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, 0U,
+					  spm_cpu_bcuk_ldo_conduct);
+	}
+
+	cpubuckldo_enter_cnt++;
+
+	return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, 0U, NULL);
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..34293c4
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#define CONSTRAINT_DRAM_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_DRAM_S0	|	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1		0U
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ		\
+	(MT_SPM_SYSPLL |			\
+	 MT_SPM_INFRA |				\
+	 MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+	.name = "dram",
+	.table_cg = {
+		0x078BF1FC,	/* MTCMOS1 */
+		0x080D8856,	/* INFRA0  */
+		0x03AF9A00,	/* INFRA1  */
+		0x86000640,	/* INFRA2  */
+		0xC800C000,	/* INFRA3  */
+		0x00000000,     /* INFRA4  */
+		0x00000000,     /* INFRA5  */
+		0x200C0000,	/* MMSYS0  */
+		0x00000000,     /* MMSYS1  */
+		0x00000000,	/* MMSYS2  */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_DRAM,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH |
+		  MT_SPM_RC_VALID_XSOC_BBLPM),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_dram_res,
+};
+
+static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
+			     unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	if (type == PLAT_RC_UPDATE_CONDITION) {
+		tlb = (const struct mt_spm_cond_tables *)val;
+		tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+		status.cond_block =
+			mt_spm_cond_check(state_id, tlb, tlb_check,
+					  ((status.valid &
+					    MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+					  &cond_dram_res : NULL);
+	} else {
+		res = MT_RM_STATUS_BAD;
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#else
+	(void)allows;
+#endif
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT),
+				     CONSTRAINT_DRAM_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_WDT |
+				       MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+		status.enter_cnt++;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..aeb778a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#include <stdbool.h>
+
+#define SPM_FLAG_SRAM_SLEEP_CTRL			\
+	(SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |	\
+	 SPM_FLAG_DISABLE_SYSRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_SRAM_EVENT)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+#endif /* MT_SPM_RC_INTERNAL_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..8d76d63
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH |	\
+	 SPM_FLAG_ENABLE_6315_CTRL |		\
+	 SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1		0U
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ		\
+	(MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_syspll = {
+	.name = "syspll",
+	.table_cg = {
+		0x078BF1FC,	/* MTCMOS1 */
+		0x080D8856,	/* INFRA0  */
+		0x03AF9A00,	/* INFRA1  */
+		0x86000640,	/* INFRA2  */
+		0xC800C000,	/* INFRA3  */
+		0x00000000,     /* INFRA4  */
+		0x0000007C,     /* INFRA5  */
+		0x280E0800,	/* MMSYS0  */
+		0x00000001,     /* MMSYS1  */
+		0x00000000,	/* MMSYS2  */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+	.table_cg = { 0U },
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_SYSPLL,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH |
+		  MT_SPM_RC_VALID_XSOC_BBLPM),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_syspll_res,
+};
+
+static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
+			       unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		return MT_RM_STATUS_BAD;
+	}
+
+	if (type == PLAT_RC_UPDATE_CONDITION) {
+		tlb = (const struct mt_spm_cond_tables *)val;
+		tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
+
+		status.cond_block =
+			mt_spm_cond_check(state_id, tlb, tlb_check,
+					  ((status.valid &
+					    MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+					  &cond_syspll_res : NULL);
+	} else {
+		res = MT_RM_STATUS_BAD;
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#else
+	(void)allows;
+#endif
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE),
+				     CONSTRAINT_SYSPLL_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				       MT_SPM_EX_OP_SET_WDT |
+				       MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+		status.enter_cnt++;
+	}
+
+	return 0;
+}