tree 0f63e1ee431d91bfa7c5bacbe2e0c7630f7cc119
parent da44d42206a485b75acfb06877d2d3d96fd5026f
author David Cunado <david.cunado@arm.com> 1477935454 +0000
committer David Cunado <david.cunado@arm.com> 1478706306 +0000

Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR

In order to avoid unexpected traps into EL3/MON mode, this patch
resets the debug registers, MDCR_EL3 and MDCR_EL2 for AArch64,
and SDCR and HDCR for AArch32.

MDCR_EL3/SDCR is zero'ed when EL3/MON mode is entered, at the
start of BL1 and BL31/SMP_MIN.

For MDCR_EL2/HDCR, this patch zero's the bits that are
architecturally UNKNOWN values on reset. This is done when
exiting from EL3/MON mode but only on platforms that support
EL2/HYP mode but choose to exit to EL1/SVC mode.

Fixes ARM-software/tf-issues#430

Change-Id: Idb992232163c072faa08892251b5626ae4c3a5b6
Signed-off-by: David Cunado <david.cunado@arm.com>