tzc: Fix MISRA defects
The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.
The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int because it is not allowed to do logical
operations on enums.
Also, fix some address definitions in arm_def.h.
Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h
index e1b7727..5fbea92 100644
--- a/drivers/arm/tzc/tzc_common_private.h
+++ b/drivers/arm/tzc/tzc_common_private.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TZC_COMMON_PRIVATE_H__
-#define __TZC_COMMON_PRIVATE_H__
+#ifndef TZC_COMMON_PRIVATE_H
+#define TZC_COMMON_PRIVATE_H
#include <arch.h>
#include <arch_helpers.h>
@@ -15,7 +15,7 @@
#define DEFINE_TZC_COMMON_WRITE_ACTION(fn_name, macro_name) \
static inline void _tzc##fn_name##_write_action( \
uintptr_t base, \
- tzc_action_t action) \
+ unsigned int action) \
{ \
mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \
action); \
@@ -24,7 +24,7 @@
#define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \
static inline void _tzc##fn_name##_write_region_base( \
uintptr_t base, \
- int region_no, \
+ unsigned int region_no, \
unsigned long long region_base) \
{ \
mmio_write_32(base + \
@@ -44,7 +44,7 @@
#define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \
static inline void _tzc##fn_name##_write_region_top( \
uintptr_t base, \
- int region_no, \
+ unsigned int region_no, \
unsigned long long region_top) \
{ \
mmio_write_32(base + \
@@ -52,19 +52,19 @@
(TZC_##macro_name##_REGION_SIZE, \
region_no) + \
TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \
- (uint32_t)region_top); \
+ (uint32_t)region_top); \
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \
- (uint32_t)(region_top >> 32)); \
+ (uint32_t)(region_top >> 32)); \
}
#define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \
static inline void _tzc##fn_name##_write_region_attributes( \
uintptr_t base, \
- int region_no, \
+ unsigned int region_no, \
unsigned int attr) \
{ \
mmio_write_32(base + \
@@ -78,7 +78,7 @@
#define DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(fn_name, macro_name) \
static inline void _tzc##fn_name##_write_region_id_access( \
uintptr_t base, \
- int region_no, \
+ unsigned int region_no, \
unsigned int val) \
{ \
mmio_write_32(base + \
@@ -94,13 +94,13 @@
*/
#define DEFINE_TZC_COMMON_CONFIGURE_REGION0(fn_name) \
static void _tzc##fn_name##_configure_region0(uintptr_t base, \
- tzc_region_attributes_t sec_attr, \
+ unsigned int sec_attr, \
unsigned int ns_device_access) \
{ \
- assert(base); \
+ assert(base != 0U); \
VERBOSE("TrustZone : Configuring region 0 " \
- "(TZC Interface Base=%p sec_attr=0x%x," \
- " ns_devs=0x%x)\n", (void *)base, \
+ "(TZC Interface Base=0x%lx sec_attr=0x%x," \
+ " ns_devs=0x%x)\n", base, \
sec_attr, ns_device_access); \
\
/* Set secure attributes on region 0 */ \
@@ -126,18 +126,18 @@
#define DEFINE_TZC_COMMON_CONFIGURE_REGION(fn_name) \
static void _tzc##fn_name##_configure_region(uintptr_t base, \
unsigned int filters, \
- int region_no, \
+ unsigned int region_no, \
unsigned long long region_base, \
unsigned long long region_top, \
- tzc_region_attributes_t sec_attr, \
- unsigned int nsaid_permissions) \
+ unsigned int sec_attr, \
+ unsigned int nsaid_permissions) \
{ \
- assert(base); \
+ assert(base != 0U); \
VERBOSE("TrustZone : Configuring region " \
- "(TZC Interface Base: %p, region_no = %d)" \
- "...\n", (void *)base, region_no); \
+ "(TZC Interface Base: 0x%lx, region_no = %u)" \
+ "...\n", base, region_no); \
VERBOSE("TrustZone : ... base = %llx, top = %llx," \
- "\n", region_base, region_top);\
+ "\n", region_base, region_top); \
VERBOSE("TrustZone : ... sec_attr = 0x%x," \
" ns_devs = 0x%x)\n", \
sec_attr, nsaid_permissions); \
@@ -175,42 +175,44 @@
id = mmio_read_32(base + PID0_OFF);
/* Masks DESC part in PID1 */
- id |= ((mmio_read_32(base + PID1_OFF) & 0xF) << 8);
+ id |= ((mmio_read_32(base + PID1_OFF) & 0xFU) << 8U);
return id;
}
#if ENABLE_ASSERTIONS
#ifdef AARCH32
-static inline unsigned long long _tzc_get_max_top_addr(int addr_width)
+static inline unsigned long long _tzc_get_max_top_addr(unsigned int addr_width)
{
/*
* Assume at least 32 bit wide address and initialize the max.
* This function doesn't use 64-bit integer arithmetic to avoid
* having to implement additional compiler library functions.
*/
- unsigned long long addr_mask = 0xFFFFFFFF;
+ unsigned long long addr_mask = 0xFFFFFFFFU;
uint32_t *addr_ptr = (uint32_t *)&addr_mask;
- assert(addr_width >= 32);
+ assert(addr_width >= 32U);
/* This logic works only on little - endian platforms */
- assert((read_sctlr() & SCTLR_EE_BIT) == 0);
+ assert((read_sctlr() & SCTLR_EE_BIT) == 0U);
/*
* If required address width is greater than 32, populate the higher
* 32 bits of the 64 bit field with the max address.
*/
- if (addr_width > 32)
- *(addr_ptr + 1) = ((1 << (addr_width - 32)) - 1);
+ if (addr_width > 32U)
+ *(addr_ptr + 1U) = ((1U << (addr_width - 32U)) - 1U);
return addr_mask;
}
#else
-#define _tzc_get_max_top_addr(addr_width)\
- (UINT64_MAX >> (64 - (addr_width)))
+static inline unsigned long long _tzc_get_max_top_addr(unsigned int addr_width)
+{
+ return UINT64_MAX >> (64U - addr_width);
+}
#endif /* AARCH32 */
#endif /* ENABLE_ASSERTIONS */
-#endif /* __TZC_COMMON_PRIVATE_H__ */
+#endif /* TZC_COMMON_PRIVATE_H */