Merge changes Ia1142b31,I424f1cde into integration
* changes:
fix(tc): enable the execution of both platform tests
fix(tc): update the name of mbedtls config header
diff --git a/Makefile b/Makefile
index 5306ddf..892c2c9 100644
--- a/Makefile
+++ b/Makefile
@@ -861,8 +861,12 @@
$(info FEATURE_DETECTION is an experimental feature)
endif
-ifneq ($(ENABLE_SME_FOR_NS), 0)
- $(info ENABLE_SME_FOR_NS is an experimental feature)
+ifneq ($(ENABLE_SME2_FOR_NS), 0)
+ ifeq (${ENABLE_SME_FOR_NS}, 0)
+ $(warning "ENABLE_SME2_FOR_NS requires ENABLE_SME_FOR_NS also to be set")
+ $(warning "Forced ENABLE_SME_FOR_NS=1")
+ override ENABLE_SME_FOR_NS := 1
+ endif
endif
ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
@@ -884,6 +888,7 @@
ifneq (${ENABLE_SME_FOR_NS},0)
$(error "ENABLE_SME_FOR_NS cannot be used with ARCH=aarch32")
endif
+
ifeq (${ENABLE_SVE_FOR_NS},1)
# Warning instead of error due to CI dependency on this
$(error "ENABLE_SVE_FOR_NS cannot be used with ARCH=aarch32")
@@ -925,6 +930,7 @@
ifneq (${ENABLE_SME_FOR_NS},0)
$(error "ENABLE_SME_FOR_NS cannot be used with CTX_INCLUDE_FPREGS")
endif
+
ifeq (${ENABLE_SVE_FOR_NS},1)
# Warning instead of error due to CI dependency on this
$(warning "ENABLE_SVE_FOR_NS cannot be used with CTX_INCLUDE_FPREGS")
@@ -1196,6 +1202,7 @@
ENABLE_SPE_FOR_NS \
ENABLE_SYS_REG_TRACE_FOR_NS \
ENABLE_SME_FOR_NS \
+ ENABLE_SME2_FOR_NS \
ENABLE_SVE_FOR_NS \
ENABLE_TRF_FOR_NS \
FW_ENC_STATUS \
@@ -1251,6 +1258,7 @@
ENABLE_RME \
ENABLE_RUNTIME_INSTRUMENTATION \
ENABLE_SME_FOR_NS \
+ ENABLE_SME2_FOR_NS \
ENABLE_SME_FOR_SWD \
ENABLE_SPE_FOR_NS \
ENABLE_SVE_FOR_NS \
diff --git a/changelog.yaml b/changelog.yaml
index d54c62b..6dbb9b2 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -128,7 +128,7 @@
- title: Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP)
scope: rng-trap
- - title: Scalable Matrix Extension (FEAT_SME)
+ - title: Scalable Matrix Extension (FEAT_SME, FEAT_SME2)
scope: sme
- title: Statistical profiling Extension (FEAT_SPE)
diff --git a/common/feat_detect.c b/common/feat_detect.c
index c8a0703..eb4db95 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -218,6 +218,8 @@
/* v9.2 features */
check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(),
"SME", 1, 2);
+ check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(),
+ "SME2", 2, 2);
/* v9.4 features */
check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
diff --git a/docs/design_documents/measured_boot_poc.rst b/docs/design_documents/measured_boot_poc.rst
index 2e25057..7f73d7e 100644
--- a/docs/design_documents/measured_boot_poc.rst
+++ b/docs/design_documents/measured_boot_poc.rst
@@ -135,11 +135,11 @@
(4) Now, you should be able to continue with step 5 in "`Get and build the solution`_"
instructions. In order to enable support for Measured Boot, you need to
- set the ``MEASURED_BOOT`` build option:
+ set the following build options:
.. code:: shell
- $ MEASURED_BOOT=y make -j `nproc`
+ $ MEASURED_BOOT=y MEASURED_BOOT_FTPM=y make -j `nproc`
.. note::
The build process will likely take a long time. It is strongly recommended to
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index d2f463f..2229591 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -442,6 +442,13 @@
build with these options will fail. This flag can take the values 0 to 2, to
align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
+- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension
+ version 2 (SME2) for the non-secure world only. SME2 is an optional
+ architectural feature for AArch64 and TF-A support is experimental.
+ This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME
+ accesses will still be trapped. This flag can take the values 0 to 2, to
+ align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
+
- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS
must also be set to use this. If enabling this, the secure world MUST
diff --git a/docs/glossary.rst b/docs/glossary.rst
index 57fde2d..12c6ab7 100644
--- a/docs/glossary.rst
+++ b/docs/glossary.rst
@@ -229,7 +229,7 @@
Trusted Platform Module
TRNG
- True Randon Number Generator (hardware based)
+ True Random Number Generator (hardware based)
TSP
Test Secure Payload
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 1f15a73..ea7d11c 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -56,7 +56,7 @@
#. Obtain SCP binaries (Juno)
- This version of TF-A is tested with SCP version 2.8.0 on Juno. You can
+ This version of TF-A is tested with SCP version 2.12.0 on Juno. You can
download pre-built SCP binaries (``scp_bl1.bin`` and ``scp_bl2.bin``)
from `TF-A downloads page`_. Alternatively, you can `build
the binaries from source`_.
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 9e061bf..ac5eae2 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -412,6 +412,7 @@
#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
+#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@@ -519,6 +520,8 @@
#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
#define CPACR_EL1_FP_TRAP_NONE UL(0x3)
+#define CPACR_EL1_SMEN_SHIFT U(24)
+#define CPACR_EL1_SMEN_MASK ULL(0x3)
/* SCR definitions */
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
@@ -1026,11 +1029,16 @@
#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
+#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55)
+#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf)
+#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0)
+#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1)
/* SMCR_ELx definitions */
#define SMCR_ELX_LEN_SHIFT U(0)
-#define SMCR_ELX_LEN_MASK U(0x1ff)
+#define SMCR_ELX_LEN_MAX U(0x1ff)
#define SMCR_ELX_FA64_BIT (U(1) << 31)
+#define SMCR_ELX_EZT0_BIT (U(1) << 30)
/*******************************************************************************
* Definitions of MAIR encodings for device and normal memory
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 40ab82f..a0141de 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -657,4 +657,17 @@
return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME_SUPPORTED;
}
+static inline bool is_feat_sme2_supported(void)
+{
+ if (ENABLE_SME2_FOR_NS == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_SME2_FOR_NS == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME2_SUPPORTED;
+}
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index b4dab08..7d1407a 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -186,11 +186,12 @@
.space SPINLOCK_ASM_SIZE
.endm
-#if RAS_EXTENSION
+ /*
+ * With RAS extension executes esb instruction, else NOP
+ */
.macro esb
.inst 0xd503221f
.endm
-#endif
/*
* Helper macro to read system register value into x0
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index 29034fd..f888d12 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -43,11 +43,23 @@
* to be the least restrictive, then lower ELs can restrict as needed
* using SMCR_EL2 and SMCR_EL1.
*/
- reg = SMCR_ELX_LEN_MASK;
+ reg = SMCR_ELX_LEN_MAX;
+
if (read_feat_sme_fa64_id_field() != 0U) {
VERBOSE("[SME] FA64 enabled\n");
reg |= SMCR_ELX_FA64_BIT;
}
+
+ /*
+ * Enable access to ZT0 register.
+ * Make sure FEAT_SME2 is supported by the hardware before continuing.
+ * If supported, Set the EZT0 bit in SMCR_EL3 to allow instructions to
+ * access ZT0 register without trapping.
+ */
+ if (is_feat_sme2_supported()) {
+ VERBOSE("SME2 enabled\n");
+ reg |= SMCR_ELX_EZT0_BIT;
+ }
write_smcr_el3(reg);
/* Reset CPTR_EL3 value. */
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 34a9bc6..021893c 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -405,6 +405,9 @@
override ENABLE_SVE_FOR_SWD := 0
endif
+# SME2 defaults to disabled
+ENABLE_SME2_FOR_NS := 0
+
SANITIZE_UB := off
# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
diff --git a/plat/arm/board/fvp/aarch64/fvp_ea.c b/plat/arm/board/fvp/aarch64/fvp_ea.c
new file mode 100644
index 0000000..07053a9
--- /dev/null
+++ b/plat/arm/board/fvp/aarch64/fvp_ea.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <inttypes.h>
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <bl31/ea_handle.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <context.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <plat/common/platform.h>
+
+/*
+ * This source file with custom plat_ea_handler function is compiled only when
+ * building TF-A with compile option PLATFORM_TEST_EA_FFH
+ */
+
+/* Test address(non-existent) used in tftf to cause External aborts */
+#define TEST_ADDRESS UL(0x7FFFF000)
+
+void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
+ void *handle, uint64_t flags)
+{
+#ifdef PLATFORM_TEST_EA_FFH
+ u_register_t elr_el3;
+ u_register_t fault_address;
+ cpu_context_t *ctx = cm_get_context(NON_SECURE);
+ el3_state_t *el3_ctx = get_el3state_ctx(ctx);
+ gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx);
+ unsigned int level = (unsigned int)GET_EL(read_spsr_el3());
+
+ fault_address = read_ctx_reg(gpregs_ctx, CTX_GPREG_X0);
+
+ if ((level < MODE_EL3) && (fault_address == TEST_ADDRESS)) {
+ if (ea_reason == ERROR_EA_SYNC) {
+ INFO("Handled sync EA from lower EL at address 0x%lx\n", fault_address);
+ /* To avoid continuous faults, forward return address */
+ elr_el3 = read_ctx_reg(el3_ctx, CTX_ELR_EL3);
+ elr_el3 += 4;
+ write_ctx_reg(el3_ctx, CTX_ELR_EL3, elr_el3);
+ return;
+ } else if (ea_reason == ERROR_EA_ASYNC) {
+ INFO("Handled Serror from lower EL at address 0x%lx\n", fault_address);
+ return;
+ }
+ }
+#endif
+ plat_default_ea_handler(ea_reason, syndrome, cookie, handle, flags);
+}
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 214064b..af082ba 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -55,6 +55,7 @@
ifeq (${ENABLE_RME}, 0)
ifeq (${CTX_INCLUDE_FPREGS}, 0)
ENABLE_SME_FOR_NS := 2
+ ENABLE_SME2_FOR_NS := 2
endif
endif
endif
@@ -186,31 +187,21 @@
# Cores used with DSU only
ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
# AArch64-only cores
- FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
+ # TODO: add all cores to the appropriate lists
+ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \
+ lib/cpus/aarch64/cortex_a65ae.S \
+ lib/cpus/aarch64/cortex_a76.S \
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
lib/cpus/aarch64/cortex_a78.S \
+ lib/cpus/aarch64/cortex_a78c.S \
+ lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_n2.S \
- lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/neoverse_v2.S \
- lib/cpus/aarch64/cortex_a78_ae.S \
- lib/cpus/aarch64/cortex_a510.S \
- lib/cpus/aarch64/cortex_a710.S \
- lib/cpus/aarch64/cortex_a715.S \
- lib/cpus/aarch64/cortex_x3.S \
- lib/cpus/aarch64/cortex_a65.S \
- lib/cpus/aarch64/cortex_a65ae.S \
- lib/cpus/aarch64/cortex_a78c.S \
- lib/cpus/aarch64/cortex_hayes.S \
- lib/cpus/aarch64/cortex_hunter.S \
- lib/cpus/aarch64/cortex_hunter_elp_arm.S \
- lib/cpus/aarch64/cortex_x2.S \
- lib/cpus/aarch64/neoverse_poseidon.S \
- lib/cpus/aarch64/cortex_chaberton.S \
- lib/cpus/aarch64/cortex_blackhawk.S
+ lib/cpus/aarch64/neoverse_e1.S \
+ lib/cpus/aarch64/cortex_x2.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
@@ -511,3 +502,11 @@
endif
PSCI_OS_INIT_MODE := 1
+
+$(eval $(call add_define,PLATFORM_TEST_EA_FFH))
+ifeq (${PLATFORM_TEST_EA_FFH}, 1)
+ ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
+ $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1")
+ endif
+BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
+endif
diff --git a/plat/arm/board/tc/plat_fiptool.mk b/plat/arm/board/tc/plat_fiptool.mk
deleted file mode 100644
index 0e13556..0000000
--- a/plat/arm/board/tc/plat_fiptool.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# Copyright (c) 2021, NXP. All rights reserved.
-# Copyright (c) 2022, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Name of the platform defined source file name,
-# which contains platform defined UUID entries populated
-# in the plat_def_toc_entries[].
-PLAT_DEF_UUID_CONFIG_FILE_NAME := plat_def_uuid_config
-
-PLAT_DEF_UUID_CONFIG_FILE_PATH := ../../plat/arm/board/tc
-
-PLAT_DEF_UUID := yes
-PLAT_DEF_UUID_OID_CONFIG_PATH := ../../plat/arm/board/tc
-
-
-INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \
- -I./
-# Clean the stale object file.
-$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
-
-ifeq (${PLAT_DEF_OID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_OID
-endif
-
-ifeq (${PLAT_DEF_UUID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-PLAT_OBJECTS += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o
-endif
-
-OBJECTS += ${PLAT_OBJECTS}
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 7171c24..63a9237 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -53,9 +53,6 @@
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 1
-# Enable RSS-required FIP UUIDs
-$(shell cp plat/arm/board/tc/plat_fiptool.mk ${PLAT_DIR})
-
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 6a3eae0..050ef52 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,21 +92,16 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
- plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
+ struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params();
+ plat_params_from_bl2_t *plat_params = plat_get_bl31_plat_params();
int32_t ret;
/*
- * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
- * there's no argument to relay from a previous bootloader. Platforms
- * might use custom ways to get arguments.
+ * Tegra platforms will receive boot parameters through custom
+ * mechanisms. So, we ignore the input parameters.
*/
- if (arg_from_bl2 == NULL) {
- arg_from_bl2 = plat_get_bl31_params();
- }
- if (plat_params == NULL) {
- plat_params = plat_get_bl31_plat_params();
- }
+ (void)arg0;
+ (void)arg1;
/*
* Copy BL3-3, BL3-2 entry point information.
diff --git a/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk b/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
index 7d673ba..36c07b7 100644
--- a/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
+++ b/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
@@ -1,5 +1,6 @@
#
# Copyright 2020 NXP
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -22,8 +23,6 @@
DDR_FIP_IO_SOURCES += $(DDR_FIP_IO_STORAGE_PATH)/ddr_io_storage.c
-$(shell cp tools/nxp/plat_fiptool/plat_fiptool.mk ${PLAT_DIR})
-
ifeq (${BL_COMM_DDR_FIP_IO_NEEDED},yes)
BL_COMMON_SOURCES += ${DDR_FIP_IO_SOURCES}
else
diff --git a/plat/nxp/common/fip_handler/fuse_fip/fuse.mk b/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
index d8f5ae6..4e84d02 100644
--- a/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
+++ b/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
@@ -1,5 +1,6 @@
#
# Copyright 2018-2020 NXP
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -29,8 +30,6 @@
ifeq (${FUSE_PROV_FILE},)
-$(shell cp tools/nxp/plat_fiptool/plat_fiptool.mk ${PLAT_DIR})
-
else
ifeq (${TRUSTED_BOARD_BOOT},1)
FUSE_PROV_FILE_SB = $(notdir ${FUSE_PROV_FILE})_prov.sb
diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index 0188443..c5587fd 100644
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index a83c286..c5dbf41 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/custom_sip_svc.c b/plat/xilinx/zynqmp/custom_sip_svc.c
index 7ffffd2..b9664af 100644
--- a/plat/xilinx/zynqmp/custom_sip_svc.c
+++ b/plat/xilinx/zynqmp/custom_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/include/custom_svc.h b/plat/xilinx/zynqmp/include/custom_svc.h
index 7ccde24..242f3eb 100644
--- a/plat/xilinx/zynqmp/include/custom_svc.h
+++ b/plat/xilinx/zynqmp/include/custom_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 691dfeb..fb7b009 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
index 736fcb1..2baad3d 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index 7644af3..c0c5d14 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.h b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.h
index 9eda90b..bef72b6 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.h
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c
index 0d709a7..7ddd28c 100644
--- a/plat/xilinx/zynqmp/sip_svc_setup.c
+++ b/plat/xilinx/zynqmp/sip_svc_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved.
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index ac262cd..2ebee33 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -54,10 +54,13 @@
ifneq (${PLAT},)
TF_PLATFORM_ROOT := ../../plat/
include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
-PLAT_FIPTOOL_HELPER_MK := ${PLAT_DIR}/plat_fiptool.mk
+COMBINED_PATH_FRAG := plat_fiptool/
+PLAT_FIPTOOL_HELPER_MK := $(foreach path_frag,$(subst /, ,$(patsubst ../../plat/%/,%,${PLAT_DIR})),\
+ $(eval COMBINED_PATH_FRAG := ${COMBINED_PATH_FRAG}/${path_frag})\
+ $(wildcard ${COMBINED_PATH_FRAG}/plat_fiptool.mk))
endif
-ifneq (,$(wildcard ${PLAT_FIPTOOL_HELPER_MK}))
+ifneq (,$(wildcard $(lastword ${PLAT_FIPTOOL_HELPER_MK})))
include ${PLAT_FIPTOOL_HELPER_MK}
endif
diff --git a/plat/arm/board/tc/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
similarity index 100%
rename from plat/arm/board/tc/plat_def_uuid_config.c
rename to tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
diff --git a/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk b/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
new file mode 100644
index 0000000..70ccfc5
--- /dev/null
+++ b/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2021, NXP. All rights reserved.
+# Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+INCLUDE_PATHS += -I./ \
+ -I../../plat/arm/board/tc
+
+HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
+OBJECTS += plat_fiptool/arm/board/tc/plat_def_uuid_config.o
diff --git a/tools/nxp/plat_fiptool/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/nxp/plat_def_uuid_config.c
similarity index 100%
rename from tools/nxp/plat_fiptool/plat_def_uuid_config.c
rename to tools/fiptool/plat_fiptool/nxp/plat_def_uuid_config.c
diff --git a/tools/nxp/plat_fiptool/plat_fiptool.mk b/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
similarity index 80%
rename from tools/nxp/plat_fiptool/plat_fiptool.mk
rename to tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
index ca2962a..6d7b07b 100644
--- a/tools/nxp/plat_fiptool/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
@@ -1,5 +1,6 @@
#
# Copyright (c) 2021, NXP. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -9,7 +10,7 @@
# in the plat_def_toc_entries[].
PLAT_DEF_UUID_CONFIG_FILE_NAME := plat_def_uuid_config
-PLAT_DEF_UUID_CONFIG_FILE_PATH := ../nxp/plat_fiptool
+PLAT_DEF_UUID_CONFIG_FILE_PATH := plat_fiptool/nxp/
PLAT_DEF_OID := yes
PLAT_DEF_UUID := yes
@@ -18,8 +19,6 @@
INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \
-I./
-# Clean the stale object file.
-$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
ifeq (${PLAT_DEF_OID},yes)
HOSTCCFLAGS += -DPLAT_DEF_OID
diff --git a/plat/st/stm32mp1/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
similarity index 100%
rename from plat/st/stm32mp1/plat_def_uuid_config.c
rename to tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
diff --git a/plat/st/stm32mp1/plat_fiptool.mk b/tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk
similarity index 87%
rename from plat/st/stm32mp1/plat_fiptool.mk
rename to tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk
index 00570c2..1ba47c1 100644
--- a/plat/st/stm32mp1/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk
@@ -16,7 +16,7 @@
ifeq (${PLAT_DEF_UUID},yes)
HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-${PLAT_DEF_UUID_FILE_NAME}.o: ${PLAT_DIR}${PLAT_DEF_UUID_FILE_NAME}.c
+${PLAT_DEF_UUID_FILE_NAME}.o: plat_fiptool/st/stm32mp1/${PLAT_DEF_UUID_FILE_NAME}.c
${HOSTCC} -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
PLAT_OBJECTS += ${PLAT_DEF_UUID_FILE_NAME}.o