diff --git a/drivers/marvell/comphy.h b/drivers/marvell/comphy.h
index 788b1b6..fab564e 100644
--- a/drivers/marvell/comphy.h
+++ b/drivers/marvell/comphy.h
@@ -7,8 +7,8 @@
 
 /* Driver for COMPHY unit that is part or Marvell A8K SoCs */
 
-#ifndef _COMPHY_H_
-#define _COMPHY_H_
+#ifndef COMPHY_H
+#define COMPHY_H
 
 /* COMPHY registers */
 #define COMMON_PHY_CFG1_REG			0x0
@@ -469,5 +469,4 @@
 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK	\
 			(0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
 
-#endif /* _COMPHY_H_ */
-
+#endif /* COMPHY_H */
diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h
index 1d7aec8..6eb7fd0 100644
--- a/drivers/marvell/comphy/comphy-cp110.h
+++ b/drivers/marvell/comphy/comphy-cp110.h
@@ -7,8 +7,8 @@
 
 /* Marvell CP110 SoC COMPHY unit driver */
 
-#ifndef _PHY_COMPHY_CP110_H
-#define _PHY_COMPHY_CP110_H
+#ifndef COMPHY_CP110_H
+#define COMPHY_CP110_H
 
 #define SD_ADDR(base, lane)			(base + 0x1000 * lane)
 #define HPIPE_ADDR(base, lane)			(SD_ADDR(base, lane) + 0x800)
@@ -862,5 +862,4 @@
 /* General defines */
 #define PLL_LOCK_TIMEOUT			15000
 
-#endif /* _PHY_COMPHY_CP110_H */
-
+#endif /* COMPHY_CP110_H */
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 714a41c..1628e36 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -5,8 +5,8 @@
  * https://spdx.org/licenses
  */
 
-#ifndef _PHY_COMPHY_3700_H
-#define _PHY_COMPHY_3700_H
+#ifndef PHY_COMPHY_3700_H
+#define PHY_COMPHY_3700_H
 
 #define PLL_SET_DELAY_US			600
 #define COMPHY_PLL_TIMEOUT			1000
@@ -255,4 +255,4 @@
 int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode);
 int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode);
 int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode);
-#endif /* _PHY_COMPHY_3700_H */
+#endif /* PHY_COMPHY_3700_H */
diff --git a/drivers/marvell/comphy/phy-comphy-common.h b/drivers/marvell/comphy/phy-comphy-common.h
index ba1a83c..78c7a38 100644
--- a/drivers/marvell/comphy/phy-comphy-common.h
+++ b/drivers/marvell/comphy/phy-comphy-common.h
@@ -7,8 +7,8 @@
 
 /* Marvell CP110 ana A3700 common */
 
-#ifndef _PHY_COMPHY_COMMON_H
-#define _PHY_COMPHY_COMMON_H
+#ifndef PHY_COMPHY_COMMON_H
+#define PHY_COMPHY_COMMON_H
 
 /* #define DEBUG_COMPHY */
 #ifdef DEBUG_COMPHY
@@ -153,4 +153,4 @@
 	debug("new val 0x%x\n", mmio_read_16(addr));
 }
 
-#endif /* _PHY_COMPHY_COMMON_H */
+#endif /* PHY_COMPHY_COMMON_H */
diff --git a/drivers/marvell/comphy/phy-default-porting-layer.h b/drivers/marvell/comphy/phy-default-porting-layer.h
index 39cd181..b3ad7eb 100644
--- a/drivers/marvell/comphy/phy-default-porting-layer.h
+++ b/drivers/marvell/comphy/phy-default-porting-layer.h
@@ -5,8 +5,8 @@
  * https://spdx.org/licenses
  */
 
-#ifndef __PHY_DEFAULT_PORTING_LAYER_H
-#define __PHY_DEFAULT_PORTING_LAYER_H
+#ifndef PHY_DEFAULT_PORTING_LAYER_H
+#define PHY_DEFAULT_PORTING_LAYER_H
 
 
 #define MAX_LANE_NR		6
@@ -48,4 +48,4 @@
 		.valid = 0x1
 	},
 };
-#endif /* __PHY_DEFAULT_PORTING_LAYER_H */
+#endif /* PHY_DEFAULT_PORTING_LAYER_H */
diff --git a/drivers/marvell/mc_trustzone/mc_trustzone.h b/drivers/marvell/mc_trustzone/mc_trustzone.h
index 8a06923..d36dcb5 100644
--- a/drivers/marvell/mc_trustzone/mc_trustzone.h
+++ b/drivers/marvell/mc_trustzone/mc_trustzone.h
@@ -5,8 +5,8 @@
  * https://spdx.org/licenses
  */
 
-#ifndef _MC_TRUSTZONE_H
-#define _MC_TRUSTZONE_H
+#ifndef MC_TRUSTZONE_H
+#define MC_TRUSTZONE_H
 
 #include <addr_map.h>
 
@@ -24,4 +24,4 @@
 
 void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id);
 
-#endif /* _MC_TRUSTZONE_H */
+#endif /* MC_TRUSTZONE_H */
diff --git a/drivers/marvell/uart/a3700_console.h b/drivers/marvell/uart/a3700_console.h
index 1831360..de7c4fc 100644
--- a/drivers/marvell/uart/a3700_console.h
+++ b/drivers/marvell/uart/a3700_console.h
@@ -5,8 +5,8 @@
  * https://spdx.org/licenses
  */
 
-#ifndef __A3700_CONSOLE_H__
-#define __A3700_CONSOLE_H__
+#ifndef A3700_CONSOLE_H
+#define A3700_CONSOLE_H
 
 /* MVEBU UART Registers */
 #define UART_RX_REG		0x00
@@ -52,4 +52,4 @@
 #define UART_CTRL_TXFIFO_RESET	(1 << 15)
 #define UARTLSR_TXFIFOEMPTY	(1 << 6)
 
-#endif	/* __A3700_CONSOLE_H__ */
+#endif /* A3700_CONSOLE_H */