tree d142cda266ea9315ae3d2fb2e21073b5e0537788
parent 44d1e066831843871d32915347d0ef5bae43c46f
author Jit Loon Lim <jit.loon.lim@intel.com> 1684297571 +0800
committer Jit Loon Lim <jit.loon.lim@intel.com> 1688519307 +0800

feat(intel): system manager support for Agilex5 SoC FPGA

This patch is used to implement system manager data
support for Agilex5 SoC FPGA.

	1. Initial SM bring up
	2. Support Candence SDMMC/NAND/COMBO PHY
	3. Updated product name -> Agilex5
	4. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I12712bddfb67e36a2bf56d2d98ea4ca3037f0a82