feat(tc): define MCN related macros for TC4
Define MCN related macros for TC4 to add TC4 specific MCN PMU
nodes in dts and to enable MCN PMU NS access in further commits.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ifc02fcd833888a9953fac404585468316aa0168c
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 7f24f84..5a22628 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -463,28 +463,41 @@
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK
#define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK
-#if TARGET_PLATFORM == 3
+#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4)
#define NCI_BASE_ADDR UL(0x4F000000)
-#ifdef TARGET_FLAVOUR_FPGA
+#if (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA)
#define MCN_ADDRESS_SPACE_SIZE 0x00120000
#else
#define MCN_ADDRESS_SPACE_SIZE 0x00130000
-#endif /* TARGET_FLAVOUR_FPGA */
+#endif /* (TARGET_PLATFORM == 3) && defined(TARGET_FLAVOUR_FPGA) */
+#if TARGET_PLATFORM == 3
#define MCN_OFFSET_IN_NCI 0x00C90000
-#define MCN_BASE_ADDR (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI)
+#else /* TARGET_PLATFORM == 4 */
+#ifdef TARGET_FLAVOUR_FPGA
+#define MCN_OFFSET_IN_NCI 0x00420000
+#else
+#define MCN_OFFSET_IN_NCI 0x00D80000
+#endif /* TARGET_FLAVOUR_FPGA */
+#endif /* TARGET_PLATFORM == 3 */
+#define MCN_BASE_ADDR(n) (NCI_BASE_ADDR + MCN_OFFSET_IN_NCI + \
+ ((n) * MCN_ADDRESS_SPACE_SIZE))
#define MCN_PMU_OFFSET 0x000C4000
#define MCN_MICROARCH_OFFSET 0x000E4000
-#define MCN_MICROARCH_BASE_ADDR (MCN_BASE_ADDR + MCN_MICROARCH_OFFSET)
+#define MCN_MICROARCH_BASE_ADDR(n) (MCN_BASE_ADDR(n) + \
+ MCN_MICROARCH_OFFSET)
#define MCN_SCR_OFFSET 0x4
#define MCN_SCR_PMU_BIT 10
+#if TARGET_PLATFORM == 3
#define MCN_INSTANCES 4
-#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR + \
- (n * MCN_ADDRESS_SPACE_SIZE) + \
- MCN_PMU_OFFSET)
+#else /* TARGET_PLATFORM == 4 */
+#define MCN_INSTANCES 8
+#endif /* TARGET_PLATFORM == 3 */
+#define MCN_PMU_ADDR(n) (MCN_BASE_ADDR(n) + \
+ MCN_PMU_OFFSET)
#define MCN_MPAM_NS_OFFSET 0x000D0000
-#define MCN_MPAM_NS_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_NS_OFFSET)
+#define MCN_MPAM_NS_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_NS_OFFSET)
#define MCN_MPAM_S_OFFSET 0x000D4000
-#define MCN_MPAM_S_BASE_ADDR (MCN_BASE_ADDR + MCN_MPAM_S_OFFSET)
+#define MCN_MPAM_S_BASE_ADDR(n) (MCN_BASE_ADDR(n) + MCN_MPAM_S_OFFSET)
#define MPAM_SLCCFG_CTL_OFFSET 0x00003018
#define SLC_RDALLOCMODE_SHIFT 8
#define SLC_RDALLOCMODE_MASK (3 << SLC_RDALLOCMODE_SHIFT)
@@ -496,7 +509,7 @@
#define SLC_ALLOC_BUS_SIGNAL_ATTR 2
#define MCN_CONFIG_OFFSET 0x204
-#define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET)
+#define MCN_CONFIG_ADDR(n) (MCN_BASE_ADDR(n) + MCN_CONFIG_OFFSET)
#define MCN_CONFIG_SLC_PRESENT_BIT 3
/*
@@ -507,7 +520,7 @@
*/
#define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1
#define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT
-#endif /* TARGET_PLATFORM == 3 */
+#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */
#define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12)
diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S
index 48ca16c..1fde9e9 100644
--- a/plat/arm/board/tc/include/tc_helpers.S
+++ b/plat/arm/board/tc/include/tc_helpers.S
@@ -54,7 +54,7 @@
func mark_extllc_presence
#ifdef MCN_CONFIG_ADDR
- mov_imm x0, (MCN_CONFIG_ADDR)
+ mov_imm x0, (MCN_CONFIG_ADDR(0))
ldr w1, [x0]
ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 0afc73b..f014bae 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -79,8 +79,8 @@
* Enable non-secure access to MCN PMU registers
*/
for (int i = 0; i < MCN_INSTANCES; i++) {
- uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET +
- (i * MCN_ADDRESS_SPACE_SIZE);
+ uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) +
+ MCN_SCR_OFFSET;
mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT);
}
}
@@ -93,10 +93,10 @@
* attribute from interface).
*/
for (int i = 0; i < MCN_INSTANCES; i++) {
- uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR +
- (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
- uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR +
- (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
+ uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) +
+ MPAM_SLCCFG_CTL_OFFSET;
+ uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) +
+ MPAM_SLCCFG_CTL_OFFSET;
mmio_clrsetbits_32(slccfg_ctl_ns,
(SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),