/*
 * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/* If SCMI power domain control is enabled */
#if TC_SCMI_PD_CTRL_EN
#define GPU_SCMI_PD_IDX		(PLAT_MAX_CPUS_PER_CLUSTER + 1)
#define DPU_SCMI_PD_IDX		(PLAT_MAX_CPUS_PER_CLUSTER + 2)
#endif /* TC_SCMI_PD_CTRL_EN */

/* All perf is normalized against the big core */
#define BIG_CAPACITY		1024

#if TARGET_PLATFORM <= 2
#if TARGET_FLAVOUR_FVP
#define LIT_CAPACITY		406
#define MID_CAPACITY		912
#else /* TARGET_FLAVOUR_FPGA */
#define LIT_CAPACITY		280
#define MID_CAPACITY		775
/* this is an area optimized configuration of the big core */
#define BIG2_CAPACITY		930
#endif /* TARGET_FLAVOUR_FPGA */

#define INT_MBOX_RX		317
#define MHU_TX_ADDR(pref)	pref##45000000 /* hex */
#define MHU_RX_ADDR(pref)	pref##45010000 /* hex */
#define MPAM_ADDR		0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ		5000000
#elif TARGET_PLATFORM == 3

#define LIT_CAPACITY		239
#define MID_CAPACITY		686

#define INT_MBOX_RX		300
#define MHU_TX_ADDR(pref)	pref##46040000 /* hex */
#define MHU_RX_ADDR(pref)	pref##46140000 /* hex */
#define MPAM_ADDR		0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ		3750000
#endif /* TARGET_PLATFORM == 3 */

#if TARGET_FLAVOUR_FVP
#define STDOUT_PATH		"serial0:115200n8"
#define GIC_CTRL_ADDR		2c010000
#define GIC_GICR_OFFSET		0x200000
#define UART_OFFSET		0x1000
#define VENCODER_TIMING_CLK 25175000
#define VENCODER_TIMING								\
	clock-frequency = <VENCODER_TIMING_CLK>;				\
	hactive = <640>;							\
	vactive = <480>;							\
	hfront-porch = <16>;							\
	hback-porch = <48>;							\
	hsync-len = <96>;							\
	vfront-porch = <10>;							\
	vback-porch = <33>;							\
	vsync-len = <2>
#define ETH_COMPATIBLE		"smsc,lan91c111"
#define MMC_REMOVABLE		cd-gpios = <&sysreg 0 0>
#if TARGET_PLATFORM <= 2
#define DPU_ADDR(pref)		pref##2cc00000
#define DPU_IRQ			69
#else /* TARGET_PLATFORM >= 3 */
#define DPU_ADDR(pref)		pref##4000000000
#define DPU_IRQ			579
#endif /* TARGET_PLATFORM >= 3 */

#else /* TARGET_FLAVOUR_FPGA */

#define STDOUT_PATH		"serial0:38400n8"
#define GIC_CTRL_ADDR		30000000
#define GIC_GICR_OFFSET		0x1000000
#define UART_OFFSET		0x10000
/* 1440x3200@120 framebuffer */
#define VENCODER_TIMING_CLK 836000000
#define VENCODER_TIMING								\
	clock-frequency = <VENCODER_TIMING_CLK>;				\
	hactive = <1440>;							\
	vactive = <3200>;							\
	hfront-porch = <136>;							\
	hback-porch = <296>;							\
	hsync-len = <160>;							\
	vfront-porch = <3>;							\
	vback-porch = <217>;							\
	vsync-len = <10>
#define ETH_COMPATIBLE		"smsc,lan9115"
#define MMC_REMOVABLE		non-removable
#define DPU_ADDR(pref)		pref##2cc00000
#define DPU_IRQ			69
#endif /* TARGET_FLAVOUR_FPGA */

/* Use SCMI controlled clocks */
#if TC_DPU_USE_SCMI_CLK
#define DPU_CLK_ATTR1								\
	clocks = <&scmi_clk 0>;							\
	clock-names = "aclk"

#define DPU_CLK_ATTR2								\
	clocks = <&scmi_clk 1>;							\
	clock-names = "pxclk"

#define DPU_CLK_ATTR3								\
	clocks = <&scmi_clk 2>;							\
	clock-names = "pxclk"							\
/* Use fixed clocks */
#else /* !TC_DPU_USE_SCMI_CLK */
#define DPU_CLK_ATTR1								\
	clocks = <&dpu_aclk>;							\
	clock-names = "aclk"

#define DPU_CLK_ATTR2								\
	clocks = <&dpu_pixel_clk>, <&dpu_aclk>;					\
	clock-names = "pxclk", "aclk"

#define DPU_CLK_ATTR3 DPU_CLK_ATTR2
#endif /* !TC_DPU_USE_SCMI_CLK */

/ {
#if TARGET_PLATFORM <= 2
	cmn-pmu {
		compatible = "arm,ci-700";
		reg = <0x0 0x50000000 0x0 0x10000000>;
		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
	};
#endif /* TARGET_PLATFORM <= 2 */

#if !TC_DPU_USE_SCMI_CLK
	dpu_aclk: dpu_aclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <VENCODER_TIMING_CLK>;
		clock-output-names = "fpga:dpu_aclk";
	};

	dpu_pixel_clk: dpu-pixel-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <VENCODER_TIMING_CLK>;
		clock-output-names = "pxclk";
	};
#endif /* !TC_DPU_USE_SCMI_CLK */
};