feat(versal-net): add bufferless IPI Support
There exist inter-processor interrupts on Versal-Net that do not have
corresponding message buffers. These bufferless IPI's on Versal NET
SOC are added to static IPI Tables.
In hardware description there exists two IPI's called 'IPI6' without
buffers that have respective system interrupt values 95 and 101. For
these append the string '_95' or '_101' to denote the difference for
each.
Change-Id: I22bf1a68cb0ed68913eb868f1c197856fc7d82d5
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
diff --git a/plat/xilinx/versal_net/include/plat_ipi.h b/plat/xilinx/versal_net/include/plat_ipi.h
index 9f9947e..e0fe723 100644
--- a/plat/xilinx/versal_net/include/plat_ipi.h
+++ b/plat/xilinx/versal_net/include/plat_ipi.h
@@ -24,7 +24,15 @@
#define IPI_ID_3 5U
#define IPI_ID_4 6U
#define IPI_ID_5 7U
-#define IPI_ID_MAX 8U
+#define IPI_ID_PMC_NOBUF 8U
+#define IPI_ID_6_NOBUF_95 9U
+#define IPI_ID_1_NOBUF 10U
+#define IPI_ID_2_NOBUF 11U
+#define IPI_ID_3_NOBUF 12U
+#define IPI_ID_4_NOBUF 13U
+#define IPI_ID_5_NOBUF 14U
+#define IPI_ID_6_NOBUF_101 15U
+#define IPI_ID_MAX 16U
/*********************************************************************
* IPI message buffers
@@ -68,5 +76,21 @@
#define IPI4_TRIG_BIT (1 << 6)
#define IPI5_REG_BASE (0xEB380000U)
#define IPI5_TRIG_BIT (1 << 7)
+#define PMC_NOBUF_REG_BASE (0xEB390000U)
+#define PMC_NOBUF_TRIG_BIT (1 << 8)
+#define IPI6_NOBUF_95_REG_BASE (0xEB3A0000U)
+#define IPI6_NOBUF_95_TRIG_BIT (1 << 9)
+#define IPI1_NOBUF_REG_BASE (0xEB3B0000U)
+#define IPI1_NOBUF_TRIG_BIT (1 << 10)
+#define IPI2_NOBUF_REG_BASE (0xEB3B1000U)
+#define IPI2_NOBUF_TRIG_BIT (1 << 11)
+#define IPI3_NOBUF_REG_BASE (0xEB3B2000U)
+#define IPI3_NOBUF_TRIG_BIT (1 << 12)
+#define IPI4_NOBUF_REG_BASE (0xEB3B3000U)
+#define IPI4_NOBUF_TRIG_BIT (1 << 13)
+#define IPI5_NOBUF_REG_BASE (0xEB3B4000U)
+#define IPI5_NOBUF_TRIG_BIT (1 << 14)
+#define IPI6_NOBUF_101_REG_BASE (0xEB3B5000U)
+#define IPI6_NOBUF_101_TRIG_BIT (1 << 15)
#endif /* PLAT_IPI_H */
diff --git a/plat/xilinx/versal_net/versal_net_ipi.c b/plat/xilinx/versal_net/versal_net_ipi.c
index e8d8fb7..7c38921 100644
--- a/plat/xilinx/versal_net/versal_net_ipi.c
+++ b/plat/xilinx/versal_net/versal_net_ipi.c
@@ -63,6 +63,62 @@
.ipi_reg_base = IPI5_REG_BASE,
.secure_only = 0,
},
+
+ /* PMC_NOBUF IPI */
+ [IPI_ID_PMC_NOBUF] = {
+ .ipi_bit_mask = PMC_NOBUF_TRIG_BIT,
+ .ipi_reg_base = PMC_NOBUF_REG_BASE,
+ .secure_only = IPI_SECURE_MASK,
+ },
+
+ /* IPI6 IPI */
+ [IPI_ID_6_NOBUF_95] = {
+ .ipi_bit_mask = IPI6_NOBUF_95_TRIG_BIT,
+ .ipi_reg_base = IPI6_NOBUF_95_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI1 NO BUF IPI */
+ [IPI_ID_1_NOBUF] = {
+ .ipi_bit_mask = IPI1_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI1_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI2 NO BUF IPI */
+ [IPI_ID_2_NOBUF] = {
+ .ipi_bit_mask = IPI2_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI2_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI3 NO BUF IPI */
+ [IPI_ID_3_NOBUF] = {
+ .ipi_bit_mask = IPI3_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI3_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI4 NO BUF IPI */
+ [IPI_ID_4_NOBUF] = {
+ .ipi_bit_mask = IPI4_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI4_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI5 NO BUF IPI */
+ [IPI_ID_5_NOBUF] = {
+ .ipi_bit_mask = IPI5_NOBUF_TRIG_BIT,
+ .ipi_reg_base = IPI5_NOBUF_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI6 NO BUF IPI */
+ [IPI_ID_6_NOBUF_101] = {
+ .ipi_bit_mask = IPI6_NOBUF_101_TRIG_BIT,
+ .ipi_reg_base = IPI6_NOBUF_101_REG_BASE,
+ .secure_only = 0,
+ },
};
/* versal_net_ipi_config_table_init() - Initialize versal_net IPI configuration