intel: agilex: HMC driver calculate DDR size
Driver will calculate DDR size instead of using hardcoded value
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c
index f09238c..5f3cae7 100644
--- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c
+++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c
@@ -160,8 +160,6 @@
return status;
}
-/* mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, AGX_RSTMGR_BRGMODRST_DDRSCH);*/
-
status = mem_calibration();
if (status) {
ERROR("DDR: Memory Calibration Failed\n");
@@ -169,7 +167,6 @@
}
configure_hmc_adaptor_regs();
-/* configure_ddr_sched_ctrl_regs();*/
return 0;
}
@@ -359,16 +356,17 @@
mmio_write_32(AGX_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data);
/* Enable nonsecure access to DDR */
- mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT,
- AGX_DDR_SIZE - 1);
- mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT,
- 0x1f);
+ data = get_physical_dram_size();
- mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT,
- AGX_DDR_SIZE - 1);
+ if (data < AGX_DDR_SIZE)
+ data = AGX_DDR_SIZE;
- mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8));
+ mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, data - 1);
+ mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1f);
+ mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, data - 1);
+
+ mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8));
/* ECC enablement */
data = mmio_read_32(AGX_MPFE_IOHMC_REG_CTRLCFG1);