feat(imx8ulp): update the upower config for power optimization
Enable the AFBB by default for active mode when APD side wakeup
from low power mode to align with the first time boot up.
Update the power mode configs to force shutdown all the
necessary power switches to optimize the power consumption.
To reduce the pad power consumption, put all the pad into
OFF mode to save more power. the PTD's compensation should
also be disabled in low power mode to save more power.
when APD enters PD mode, the LDO1(used by DDR) can be shutdown
to save power. when APD enters DPD mode, the BUCK3(supply for
APD/LPAV) can be shutdown to save power.
In single boot mode, When APD enters DPD mode, buck3 will
shutdown, LDO1 should be off to save more power as the DDR
controller has lost power.
In dualboot mode, the LPAV is owned by RTD side. When APD enters
low power mode, APD side should not config those PMIC regulators
that used by the resource owned by RTD side.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie5e9b428f85345b81744313a8fb93bfc27e0dd71
diff --git a/plat/imx/imx8ulp/apd_context.c b/plat/imx/imx8ulp/apd_context.c
index 8f179e7..b484a66 100644
--- a/plat/imx/imx8ulp/apd_context.c
+++ b/plat/imx/imx8ulp/apd_context.c
@@ -142,6 +142,22 @@
};
static uint32_t iomuxc_ctx[258];
+#define PORTS_NUM 3U
+void apd_io_pad_off(void)
+{
+ unsigned int i, j;
+
+ /* off the PTD/E/F, need to be customized based on actual user case */
+ for (i = 0; i < PORTS_NUM; i++) {
+ for (j = 0; j < iomuxc_sections[i].reg_num; j++) {
+ mmio_write_32(iomuxc_sections[i].offset + j * 4, 0);
+ }
+ }
+
+ /* disable the PTD compensation */
+ mmio_write_32(IMX_SIM1_BASE + 0x48, 0x800);
+}
+
void iomuxc_save(void)
{
unsigned int i, j;
@@ -152,6 +168,8 @@
iomuxc_ctx[index++] = mmio_read_32(iomuxc_sections[i].offset + j * 4);
}
}
+
+ apd_io_pad_off();
}
void iomuxc_restore(void)