Merge "chore(tc): mark TC2 platform as deprecated in Makefile" into integration
diff --git a/plat/amd/versal2/plat_psci.c b/plat/amd/versal2/plat_psci.c
index a55042d..688b177 100644
--- a/plat/amd/versal2/plat_psci.c
+++ b/plat/amd/versal2/plat_psci.c
@@ -21,6 +21,7 @@
#define PM_RET_ERROR_NOFEATURE U(19)
#define ALWAYSTRUE true
+#define LINEAR_MODE BIT(1)
static uintptr_t _sec_entry;
@@ -166,7 +167,12 @@
switch (ioctl_id) {
case IOCTL_OSPI_MUX_SELECT:
- mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1);
+ if ((arg1 == 0) || (arg1 == 1)) {
+ mmio_clrsetbits_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, LINEAR_MODE,
+ (arg1 ? LINEAR_MODE : 0));
+ } else {
+ ret = PM_RET_ERROR_ARGS;
+ }
break;
case IOCTL_UFS_TXRX_CFGRDY_GET:
ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_TX_RX_CONFIG_RDY);
diff --git a/plat/mediatek/drivers/rng/mt8188/rng_plat.c b/plat/mediatek/drivers/rng/mt8188/rng_plat.c
new file mode 100644
index 0000000..361be22
--- /dev/null
+++ b/plat/mediatek/drivers/rng/mt8188/rng_plat.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2024, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/smccc.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <services/trng_svc.h>
+#include <smccc_helpers.h>
+
+#include "rng_plat.h"
+
+static void trng_external_swrst(void)
+{
+ /* External swrst to reset whole rng module */
+ mmio_setbits_32(TRNG_SWRST_SET_REG, RNG_SWRST_B);
+ mmio_setbits_32(TRNG_SWRST_CLR_REG, RNG_SWRST_B);
+
+ /* Disable irq */
+ mmio_clrbits_32(RNG_IRQ_CFG, IRQ_EN);
+ /* Set default cutoff value */
+ mmio_write_32(RNG_HTEST, RNG_DEFAULT_CUTOFF);
+ /* Enable rng */
+ mmio_setbits_32(RNG_EN, DRBG_EN | NRBG_EN);
+}
+
+static bool get_entropy_32(uint32_t *out)
+{
+ uint64_t time = timeout_init_us(MTK_TIMEOUT_POLL);
+ int retry_times = 0;
+
+ while (!(mmio_read_32(RNG_STATUS) & DRBG_VALID)) {
+ if (mmio_read_32(RNG_STATUS) & (RNG_ERROR | APB_ERROR)) {
+ mmio_clrbits_32(RNG_EN, DRBG_EN | NRBG_EN);
+
+ mmio_clrbits_32(RNG_SWRST, SWRST_B);
+ mmio_setbits_32(RNG_SWRST, SWRST_B);
+
+ mmio_setbits_32(RNG_EN, DRBG_EN | NRBG_EN);
+ }
+
+ if (timeout_elapsed(time)) {
+ trng_external_swrst();
+ time = timeout_init_us(MTK_TIMEOUT_POLL);
+ retry_times++;
+ }
+
+ if (retry_times > MTK_RETRY_CNT) {
+ ERROR("%s: trng NOT ready\n", __func__);
+ return false;
+ }
+ }
+
+ *out = mmio_read_32(RNG_OUT);
+
+ return true;
+}
+
+/* Get random number from HWRNG and return 8 bytes of entropy.
+ * Return 'true' when random value generated successfully, otherwise return
+ * 'false'.
+ */
+bool plat_get_entropy(uint64_t *out)
+{
+ uint32_t seed[2] = { 0 };
+ int i = 0;
+
+ assert(out);
+ assert(!check_uptr_overflow((uintptr_t)out, sizeof(*out)));
+
+ /* Disable interrupt mode */
+ mmio_clrbits_32(RNG_IRQ_CFG, IRQ_EN);
+ /* Set rng health test cutoff value */
+ mmio_write_32(RNG_HTEST, RNG_DEFAULT_CUTOFF);
+ /* Enable rng module */
+ mmio_setbits_32(RNG_EN, DRBG_EN | NRBG_EN);
+
+ for (i = 0; i < ARRAY_SIZE(seed); i++) {
+ if (!get_entropy_32(&seed[i]))
+ return false;
+ }
+
+ /* Output 8 bytes entropy by combining 2 32-bit random numbers. */
+ *out = ((uint64_t)seed[0] << 32) | seed[1];
+
+ return true;
+}
diff --git a/plat/mediatek/drivers/rng/mt8188/rng_plat.h b/plat/mediatek/drivers/rng/mt8188/rng_plat.h
new file mode 100644
index 0000000..37ef271
--- /dev/null
+++ b/plat/mediatek/drivers/rng/mt8188/rng_plat.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2024, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RNG_PLAT_H
+#define RNG_PLAT_H
+
+#include <lib/utils_def.h>
+
+#define MTK_TIMEOUT_POLL 1000
+
+#define MTK_RETRY_CNT 10
+
+#define RNG_DEFAULT_CUTOFF 0x04871C0B
+
+/*******************************************************************************
+ * TRNG related constants
+ ******************************************************************************/
+#define RNG_STATUS (TRNG_BASE + 0x0004)
+#define RNG_SWRST (TRNG_BASE + 0x0010)
+#define RNG_IRQ_CFG (TRNG_BASE + 0x0014)
+#define RNG_EN (TRNG_BASE + 0x0020)
+#define RNG_HTEST (TRNG_BASE + 0x0028)
+#define RNG_OUT (TRNG_BASE + 0x0030)
+#define RNG_RAW (TRNG_BASE + 0x0038)
+#define RNG_SRC (TRNG_BASE + 0x0050)
+
+#define RAW_VALID BIT(12)
+#define DRBG_VALID BIT(4)
+#define RAW_EN BIT(8)
+#define NRBG_EN BIT(4)
+#define DRBG_EN BIT(0)
+#define IRQ_EN BIT(0)
+#define SWRST_B BIT(0)
+/* Error conditions */
+#define RNG_ERROR GENMASK_32(28, 24)
+#define APB_ERROR BIT(16)
+
+/* External swrst */
+#define TRNG_SWRST_SET_REG (INFRACFG_AO_BASE + 0x150)
+#define TRNG_SWRST_CLR_REG (INFRACFG_AO_BASE + 0x154)
+#define RNG_SWRST_B BIT(13)
+
+#endif /* RNG_PLAT_H */
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 8e0f5f9..dccb052 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -190,6 +190,11 @@
#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000)
/*******************************************************************************
+ * TRNG related constants
+ ******************************************************************************/
+#define TRNG_BASE (IO_PHYS + 0x0020F000)
+
+/*******************************************************************************
* System counter frequency related constants
******************************************************************************/
#define SYS_COUNTER_FREQ_IN_HZ (13000000)
diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk
index 2e3392f..82ef7e8 100644
--- a/plat/mediatek/mt8188/plat_config.mk
+++ b/plat/mediatek/mt8188/plat_config.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2024, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -46,5 +46,8 @@
CPU_PM_TINYSYS_SUPPORT := y
MTK_PUBEVENT_ENABLE := y
+# True Random Number Generator firmware Interface
+TRNG_SUPPORT := 1
+
MACH_MT8188 := 1
$(eval $(call add_define,MACH_MT8188))
diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk
index 5096e15..b776447 100644
--- a/plat/mediatek/mt8188/platform.mk
+++ b/plat/mediatek/mt8188/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2024, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -39,6 +39,9 @@
MODULES-y += $(MTK_PLAT)/drivers/pmic
MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
MODULES-y += $(MTK_PLAT)/drivers/ptp3
+ifeq (${TRNG_SUPPORT},1)
+MODULES-y += $(MTK_PLAT)/drivers/rng
+endif
MODULES-y += $(MTK_PLAT)/drivers/rtc
MODULES-y += $(MTK_PLAT)/drivers/spm
MODULES-y += $(MTK_PLAT)/drivers/timer
diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c
index f69cc82..d7c70f3 100644
--- a/plat/xilinx/common/ipi.c
+++ b/plat/xilinx/common/ipi.c
@@ -144,11 +144,11 @@
uint32_t status;
status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
- if (status & IPI_BIT_MASK(remote)) {
+ if ((status & IPI_BIT_MASK(remote)) != 0U) {
ret |= IPI_MB_STATUS_SEND_PENDING;
}
status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
- if (status & IPI_BIT_MASK(remote)) {
+ if ((status & IPI_BIT_MASK(remote)) != 0U) {
ret |= IPI_MB_STATUS_RECV_PENDING;
}
@@ -170,11 +170,11 @@
mmio_write_32(IPI_REG_BASE(local) + IPI_TRIG_OFFSET,
IPI_BIT_MASK(remote));
- if (is_blocking) {
+ if (is_blocking != 0U) {
do {
status = mmio_read_32(IPI_REG_BASE(local) +
IPI_OBR_OFFSET);
- } while (status & IPI_BIT_MASK(remote));
+ } while ((status & IPI_BIT_MASK(remote)) != 0U);
}
}
diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
index 0ea51f0..9a0149b 100644
--- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
+++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
@@ -94,7 +94,7 @@
/* Validate IPI mailbox access */
ret = ipi_mb_validate(ipi_local_id, ipi_remote_id, is_secure);
- if (ret)
+ if (ret != 0)
SMC_RET1(handle, ret);
switch (GET_SMC_NUM(smc_fid)) {
@@ -128,7 +128,7 @@
enable_interrupt = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0;
ipi_mb_ack(ipi_local_id, ipi_remote_id);
- if (enable_interrupt)
+ if (enable_interrupt != 0)
ipi_mb_enable_irq(ipi_local_id, ipi_remote_id);
SMC_RET1(handle, 0);
}
diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index 425fdcb..c3872fc 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -217,6 +217,7 @@
enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count)
{
size_t i;
+ size_t local_count = count;
#if IPI_CRC_CHECK
uint32_t crc;
#endif
@@ -225,8 +226,8 @@
IPI_BUFFER_REQ_OFFSET;
enum pm_ret_status ret = PM_RET_SUCCESS;
- if (count > IPI_BUFFER_MAX_WORDS) {
- count = IPI_BUFFER_MAX_WORDS;
+ if (local_count > IPI_BUFFER_MAX_WORDS) {
+ local_count = IPI_BUFFER_MAX_WORDS;
}
for (i = 0; i < count; i++) {
@@ -240,7 +241,7 @@
/* Payload data is invalid as CRC validation failed
* Clear the payload to avoid leakage of data to upper layers
*/
- memset(value, 0, count);
+ memset(value, 0, local_count);
}
#endif
return ret;
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index d6d4e39..7571e9d 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -146,7 +146,7 @@
(void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope(), SECURE_FLAG);
- while (1) {
+ while (true) {
wfi();
}
}
@@ -185,7 +185,7 @@
(void)psci_cpu_off();
- while (1) {
+ while (true) {
wfi();
}
}
diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c
index 3c0bd63..d449f74 100644
--- a/plat/xilinx/versal/sip_svc_setup.c
+++ b/plat/xilinx/versal/sip_svc_setup.c
@@ -80,7 +80,7 @@
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4);
- if (smc_fid & SIP_FID_MASK) {
+ if ((smc_fid & SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index 12d3e3b..cf2368a 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -214,7 +214,7 @@
}
if (handler != NULL) {
- handler(intr_id, flags, handle, cookie);
+ (void)handler(intr_id, flags, handle, cookie);
}
return 0;
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index e89af71..a2bf0d9 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -42,7 +42,7 @@
return PSCI_E_INTERN_FAIL;
}
- pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U,
+ (void)pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U,
versal_net_sec_entry >> 32, 0, 0);
/* Clear power down request */
@@ -130,7 +130,7 @@
(void)psci_cpu_off();
- while (1) {
+ while (true) {
wfi();
}
}
@@ -166,7 +166,7 @@
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMC to suspend this core */
- pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry,
+ (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry,
SECURE_FLAG);
/* TODO: disable coherency */
@@ -223,10 +223,10 @@
static void __dead2 versal_net_system_off(void)
{
/* Send the power down request to the PMC */
- pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
+ (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope(), SECURE_FLAG);
- while (1) {
+ while (true) {
wfi();
}
}
@@ -257,7 +257,7 @@
}
/* We expect the 'state id' to be zero */
- if (psci_get_pstate_id(power_state)) {
+ if (psci_get_pstate_id(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}
diff --git a/plat/xilinx/versal_net/sip_svc_setup.c b/plat/xilinx/versal_net/sip_svc_setup.c
index c974810..bf06e2c 100644
--- a/plat/xilinx/versal_net/sip_svc_setup.c
+++ b/plat/xilinx/versal_net/sip_svc_setup.c
@@ -69,7 +69,7 @@
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4);
- if (smc_fid & SIP_FID_MASK) {
+ if ((smc_fid & SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index 526e215..58db2e4 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -58,7 +58,7 @@
pm_client_wakeup(proc);
/* Send request to PMU to wake up selected APU CPU core */
- pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING);
+ (void)pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING);
return PSCI_E_SUCCESS;
}
@@ -88,7 +88,7 @@
* invoking CPU_on function, during which resume address will
* be set.
*/
- pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
+ (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
}
static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
@@ -109,7 +109,7 @@
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMU to suspend this core */
- pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry);
+ (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry);
/* APU is to be turned off */
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
@@ -166,10 +166,10 @@
plat_arm_interconnect_exit_coherency();
/* Send the power down request to the PMU */
- pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN,
+ (void)pm_system_shutdown((uint32_t)PMF_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope());
- while (1) {
+ while (true) {
wfi();
}
}
@@ -180,10 +180,10 @@
plat_arm_interconnect_exit_coherency();
/* Send the system reset request to the PMU */
- pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
+ (void)pm_system_shutdown((uint32_t)PMF_SHUTDOWN_TYPE_RESET,
pm_get_shutdown_scope());
- while (1) {
+ while (true) {
wfi();
}
}
@@ -204,7 +204,7 @@
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
}
/* We expect the 'state id' to be zero */
- if (psci_get_pstate_id(power_state)) {
+ if (psci_get_pstate_id(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}
diff --git a/plat/xilinx/zynqmp/plat_zynqmp.c b/plat/xilinx/zynqmp/plat_zynqmp.c
index e3a979e..65faa2f 100644
--- a/plat/xilinx/zynqmp/plat_zynqmp.c
+++ b/plat/xilinx/zynqmp/plat_zynqmp.c
@@ -10,7 +10,7 @@
int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
{
- if (mpidr & MPIDR_CLUSTER_MASK) {
+ if ((mpidr & MPIDR_CLUSTER_MASK) != 0U) {
return -1;
}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index ee4f07d..91adb07 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2456,14 +2456,14 @@
void pm_api_clock_get_name(uint32_t clock_id, char *name)
{
if (clock_id == CLK_MAX) {
- memcpy(name, END_OF_CLK, ((sizeof(END_OF_CLK) > CLK_NAME_LEN) ?
+ (void)memcpy(name, END_OF_CLK, ((sizeof(END_OF_CLK) > CLK_NAME_LEN) ?
CLK_NAME_LEN : sizeof(END_OF_CLK)));
} else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) {
- memset(name, 0, CLK_NAME_LEN);
+ (void)memset(name, 0, CLK_NAME_LEN);
} else if (clock_id < CLK_MAX_OUTPUT_CLK) {
- memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
+ (void)memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
} else {
- memcpy(name, ext_clocks[clock_id - CLK_MAX_OUTPUT_CLK].name,
+ (void)memcpy(name, ext_clocks[clock_id - CLK_MAX_OUTPUT_CLK].name,
CLK_NAME_LEN);
}
}
@@ -2499,7 +2499,7 @@
return PM_RET_ERROR_NOTSUPPORTED;
}
- memset(topology, 0, CLK_TOPOLOGY_PAYLOAD_LEN);
+ (void)memset(topology, 0, CLK_TOPOLOGY_PAYLOAD_LEN);
clock_nodes = *clocks[clock_id].nodes;
num_nodes = clocks[clock_id].num_nodes;
@@ -2613,7 +2613,7 @@
return PM_RET_ERROR_ARGS;
}
- memset(parents, 0, CLK_PARENTS_PAYLOAD_LEN);
+ (void)memset(parents, 0, CLK_PARENTS_PAYLOAD_LEN);
/* Skip parent till index */
for (i = 0; i < index; i++) {
@@ -2684,8 +2684,8 @@
nodes = *clocks[clock_id].nodes;
for (i = 0; i < clocks[clock_id].num_nodes; i++) {
if (nodes[i].type == div_type) {
- if (CLK_DIVIDER_POWER_OF_TWO &
- nodes[i].typeflags) {
+ if ((CLK_DIVIDER_POWER_OF_TWO &
+ nodes[i].typeflags) != 0U) {
*max_div = (1U << (BIT(nodes[i].width) - 1U));
} else {
*max_div = BIT(nodes[i].width) - 1U;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index aea607c..0dbfa57 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -62,7 +62,7 @@
{
uint32_t val;
- if (mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) {
+ if ((mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) != 0U) {
return PM_RET_ERROR_ACCESS;
}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index b34369b..1477e25 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -2012,9 +2012,9 @@
void pm_api_pinctrl_get_function_name(uint32_t fid, char *name)
{
if (fid >= MAX_FUNCTION) {
- memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
+ (void)memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
} else {
- memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
+ (void)memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
}
}
@@ -2049,7 +2049,7 @@
return PM_RET_ERROR_ARGS;
}
- memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
+ (void)memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
grps = pinctrl_functions[fid].group_base;
end_of_grp_offset = grps + pinctrl_functions[fid].group_size;
@@ -2094,7 +2094,7 @@
return PM_RET_ERROR_ARGS;
}
- memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
+ (void)memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
grps = *zynqmp_pin_groups[pin].groups;
if (grps == NULL) {
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c
index 716ebb6..a517257 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.c
@@ -204,7 +204,7 @@
continue;
}
- while (reg) {
+ while (reg != 0U) {
enum pm_node_id node;
uint32_t idx, ret, irq, lowest_set = reg & (-reg);
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 5456689..079f89e 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -1115,7 +1115,7 @@
return status;
}
- if (enable) {
+ if (enable != 0U) {
api_id = PM_CLOCK_ENABLE;
} else {
api_id = PM_CLOCK_DISABLE;
@@ -1297,7 +1297,7 @@
return status;
}
- if (pm_clock_has_div(clock_id, PM_CLOCK_DIV0_ID)) {
+ if ((pm_clock_has_div(clock_id, PM_CLOCK_DIV0_ID)) != 0U) {
/* Send request to the PMU to get div0 */
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
PM_CLOCK_DIV0_ID);
@@ -1308,7 +1308,7 @@
*divider = val;
}
- if (pm_clock_has_div(clock_id, PM_CLOCK_DIV1_ID)) {
+ if ((pm_clock_has_div(clock_id, PM_CLOCK_DIV1_ID)) != 0U) {
/* Send request to the PMU to get div1 */
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
PM_CLOCK_DIV1_ID);
diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c
index f5990ca..1baefb3 100644
--- a/plat/xilinx/zynqmp/sip_svc_setup.c
+++ b/plat/xilinx/zynqmp/sip_svc_setup.c
@@ -81,7 +81,7 @@
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4);
- if (smc_fid & SIP_FID_MASK) {
+ if ((smc_fid & (uint32_t)SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}