Merge "fix(xilinx): map PMC_GPIO device node to interrupt for wakeup source" into integration
diff --git a/Makefile b/Makefile
index cb88758..e157022 100644
--- a/Makefile
+++ b/Makefile
@@ -1668,11 +1668,10 @@
for commit in `git rev-list --no-merges $$COMMON_COMMIT..HEAD`; \
do \
printf "\n[*] Checking style of '$$commit'\n\n"; \
- git log --format=email "$$commit~..$$commit" \
- -- ${CHECK_PATHS} | \
- ${CHECKPATCH} ${CHECKPATCH_OPTS} - || true; \
- git diff --format=email "$$commit~..$$commit" \
- -- ${CHECK_PATHS} | \
+ ( git log --format=email "$$commit~..$$commit" \
+ -- ${CHECK_PATHS} ; \
+ git diff --format=email "$$commit~..$$commit" \
+ -- ${CHECK_PATHS}; ) | \
${CHECKPATCH} ${CHECKPATCH_OPTS} - || true; \
done
diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst
index 29b89b2..c5dad14 100644
--- a/docs/components/ffa-manifest-binding.rst
+++ b/docs/components/ffa-manifest-binding.rst
@@ -228,6 +228,14 @@
then communicate the region properties (including the base address chosen
by the partition manager) to the partition.
+- load-address-relative-offset
+ - value type: <u64>
+ - Offset relative to the load address of the partition.
+ When this is provided in the partition manifest, it should be added to the
+ load address to get the base address of the region. The secure partition
+ manifest can have either "base-address" or "load-address-relative-offset".
+ It cannot have both.
+
- stream-ids
- value type: <prop-encoded-array>
- List of IDs belonging to a DMA capable peripheral device that has access to
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index 5fbd7fd..03703bc 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -52,7 +52,7 @@
- ``RES0``: Bit 31 of the version number is reserved 0 as to maintain
consistency with the versioning schemes used in other parts of RMM.
-This document specifies the 0.2 version of Boot Interface ABI and RMM-EL3
+This document specifies the 0.3 version of Boot Interface ABI and RMM-EL3
services specification and the 0.3 version of the Boot Manifest.
.. _rmm_el3_boot_interface:
@@ -238,6 +238,7 @@
``E_RMM_BAD_PAS``,Incorrect PAS,-3
``E_RMM_NOMEM``,Not enough memory to perform an operation,-4
``E_RMM_INVAL``,The value of an argument was invalid,-5
+ ``E_RMM_AGAIN``,The resource is busy. Try again.,-6
If multiple failure conditions are detected in an RMM to EL3 command, then EL3
is allowed to return an error code corresponding to any of the failure
@@ -442,7 +443,21 @@
RMM_ATTEST_GET_PLAT_TOKEN command
=================================
-Retrieve the Platform Token from EL3.
+Retrieve the Platform Token from EL3. If the entire token does not fit in the
+buffer, EL3 returns a hunk of the token (via ``tokenHunkSize`` parameter) and
+indicates the remaining bytes that are pending retrieval (via ``remainingSize``
+parameter). The challenge object for the platform token must be populated in
+the buffer for the first call of this command and the size of the object is
+indicated by ``c_size`` parameter. Subsequent calls to retrieve remaining hunks of
+the token must be made with ``c_size`` as 0.
+
+If ``c_size`` is not 0, this command could cause regeneration of platform token
+and will return token hunk corresponding to beginning of the token.
+
+It is valid for the calls of this command to return ``E_RMM_AGAIN`` error,
+which is an indication to the caller to retry this command again. Depending on the
+platform, this mechanism can be used to implement queuing to HES, if HES is
+involved in platform token generation.
FID
---
@@ -457,9 +472,9 @@
:widths: 1 1 1 1 5
fid,x0,[63:0],UInt64,Command FID
- buf_pa,x1,[63:0],Address,PA of the platform attestation token. The challenge object is passed in this buffer. The PA must belong to the shared buffer
+ buf_pa,x1,[63:0],Address,"PA of the platform attestation token. The challenge object must be passed in this buffer for the first call of this command. Any subsequent calls, if required to retrieve the full token, should not have this object. The PA must belong to the shared buffer."
buf_size,x2,[63:0],Size,Size in bytes of the platform attestation token buffer. ``bufPa + bufSize`` must lie within the shared buffer
- c_size,x3,[63:0],Size,Size in bytes of the challenge object. It corresponds to the size of one of the defined SHA algorithms
+ c_size,x3,[63:0],Size,"Size in bytes of the challenge object. It corresponds to the size of one of the defined SHA algorithms. Any subsequent calls, if required to retrieve the full token, should set this size to 0."
Output values
-------------
@@ -469,7 +484,8 @@
:widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
- tokenSize,x1,[63:0],Size,Size of the platform token
+ tokenHunkSize,x1,[63:0],Size,Size of the platform token hunk retrieved
+ remainingSize,x2,[63:0],Size,Remaining bytes of the token that are pending retrieval
Failure conditions
------------------
@@ -481,9 +497,11 @@
:header: "ID", "Condition"
:widths: 1 5
+ ``E_RMM_AGAIN``,Resource for Platform token retrieval is busy. Try again.
``E_RMM_BAD_ADDR``,``PA`` is outside the shared buffer
``E_RMM_INVAL``,``PA + BSize`` is outside the shared buffer
- ``E_RMM_INVAL``,``CSize`` does not represent the size of a supported SHA algorithm
+ ``E_RMM_INVAL``,``CSize`` does not represent the size of a supported SHA algorithm for the first call to this command
+ ``E_RMM_INVAL``,``CSize`` is not 0 for subsequent calls to retrieve remaining hunks of the token
``E_RMM_UNK``,An unknown error occurred whilst processing the command
``E_RMM_OK``,No errors detected
diff --git a/docs/design_documents/rse.rst b/docs/design_documents/rse.rst
index e0e0fb3..57467f3 100644
--- a/docs/design_documents/rse.rst
+++ b/docs/design_documents/rse.rst
@@ -482,101 +482,101 @@
INFO: Get platform token start
INFO: Get platform token succeeds, len: 1086
INFO: Platform attestation token:
- INFO: d2 84 44 a1 01 38 22 a0 59 05 7a a9 19 01 09 78
- INFO: 1c 68 74 74 70 3a 2f 2f 61 72 6d 2e 63 6f 6d 2f
- INFO: 43 43 41 2d 53 53 44 2f 31 2e 30 2e 30 0a 58 20
- INFO: b5 97 3c b6 8b aa 9f c5 55 58 78 6b 7e c6 7f 69
- INFO: e4 0d f5 ba 5a a9 21 cd 0c 27 f4 05 87 a0 11 ea
- INFO: 19 09 5c 58 20 7f 45 4c 46 02 01 01 00 00 00 00
- INFO: 00 00 00 00 00 03 00 3e 00 01 00 00 00 50 58 00
- INFO: 00 00 00 00 00 19 01 00 58 21 01 07 06 05 04 03
- INFO: 02 01 00 0f 0e 0d 0c 0b 0a 09 08 17 16 15 14 13
- INFO: 12 11 10 1f 1e 1d 1c 1b 1a 19 18 19 09 61 44 cf
- INFO: cf cf cf 19 09 5b 19 30 03 19 09 62 67 73 68 61
- INFO: 2d 32 35 36 19 09 60 78 3a 68 74 74 70 73 3a 2f
- INFO: 2f 76 65 72 61 69 73 6f 6e 2e 65 78 61 6d 70 6c
- INFO: 65 2f 2e 77 65 6c 6c 2d 6b 6e 6f 77 6e 2f 76 65
- INFO: 72 61 69 73 6f 6e 2f 76 65 72 69 66 69 63 61 74
- INFO: 69 6f 6e 19 09 5f 8d a4 01 69 52 53 45 5f 42 4c
- INFO: 31 5f 32 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
- INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
- INFO: c0 fa 97 3f 7a a3 02 58 20 9a 27 1f 2a 91 6b 0b
- INFO: 6e e6 ce cb 24 26 f0 b3 20 6e f0 74 57 8b e5 5d
- INFO: 9b c9 4f 6f 3f e3 ab 86 aa 06 67 73 68 61 2d 32
- INFO: 35 36 a4 01 67 52 53 45 5f 42 4c 32 05 58 20 53
- INFO: 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41
- INFO: 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02
- INFO: 58 20 53 c2 34 e5 e8 47 2b 6a c5 1c 1a e1 ca b3
- INFO: fe 06 fa d0 53 be b8 eb fd 89 77 b0 10 65 5b fd
- INFO: d3 c3 06 67 73 68 61 2d 32 35 36 a4 01 65 52 53
- INFO: 45 5f 53 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
- INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
- INFO: c0 fa 97 3f 7a a3 02 58 20 11 21 cf cc d5 91 3f
- INFO: 0a 63 fe c4 0a 6f fd 44 ea 64 f9 dc 13 5c 66 63
- INFO: 4b a0 01 d1 0b cf 43 02 a2 06 67 73 68 61 2d 32
- INFO: 35 36 a4 01 66 41 50 5f 42 4c 31 05 58 20 53 78
- INFO: 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41
- INFO: 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58
- INFO: 20 15 71 b5 ec 78 bd 68 51 2b f7 83 0b b6 a2 a4
- INFO: 4b 20 47 c7 df 57 bc e7 9e b8 a1 c0 e5 be a0 a5
- INFO: 01 06 67 73 68 61 2d 32 35 36 a4 01 66 41 50 5f
+ INFO: d2 84 44 a1 01 38 22 a0 59 05 81 a9 19 01 09 78
+ INFO: 23 74 61 67 3a 61 72 6d 2e 63 6f 6d 2c 32 30 32
+ INFO: 33 3a 63 63 61 5f 70 6c 61 74 66 6f 72 6d 23 31
+ INFO: 2e 30 2e 30 0a 58 20 0d 22 e0 8a 98 46 90 58 48
+ INFO: 63 18 28 34 89 bd b3 6f 09 db ef eb 18 64 df 43
+ INFO: 3f a6 e5 4e a2 d7 11 19 09 5c 58 20 7f 45 4c 46
+ INFO: 02 01 01 00 00 00 00 00 00 00 00 00 03 00 3e 00
+ INFO: 01 00 00 00 50 58 00 00 00 00 00 00 19 01 00 58
+ INFO: 21 01 07 06 05 04 03 02 01 00 0f 0e 0d 0c 0b 0a
+ INFO: 09 08 17 16 15 14 13 12 11 10 1f 1e 1d 1c 1b 1a
+ INFO: 19 18 19 09 61 44 cf cf cf cf 19 09 5b 19 30 03
+ INFO: 19 09 62 67 73 68 61 2d 32 35 36 19 09 60 78 3a
+ INFO: 68 74 74 70 73 3a 2f 2f 76 65 72 61 69 73 6f 6e
+ INFO: 2e 65 78 61 6d 70 6c 65 2f 2e 77 65 6c 6c 2d 6b
+ INFO: 6e 6f 77 6e 2f 76 65 72 61 69 73 6f 6e 2f 76 65
+ INFO: 72 69 66 69 63 61 74 69 6f 6e 19 09 5f 8d a4 01
+ INFO: 69 52 53 45 5f 42 4c 31 5f 32 05 58 20 53 78 79
+ INFO: 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c
+ INFO: 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20
+ INFO: 9a 27 1f 2a 91 6b 0b 6e e6 ce cb 24 26 f0 b3 20
+ INFO: 6e f0 74 57 8b e5 5d 9b c9 4f 6f 3f e3 ab 86 aa
+ INFO: 06 67 73 68 61 2d 32 35 36 a4 01 67 52 53 45 5f
INFO: 42 4c 32 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
- INFO: c0 fa 97 3f 7a a3 02 58 20 10 15 9b af 26 2b 43
- INFO: a9 2d 95 db 59 da e1 f7 2c 64 51 27 30 16 61 e0
- INFO: a3 ce 4e 38 b2 95 a9 7c 58 06 67 73 68 61 2d 32
- INFO: 35 36 a4 01 67 53 43 50 5f 42 4c 31 05 58 20 53
- INFO: 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41
- INFO: 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02
- INFO: 58 20 10 12 2e 85 6b 3f cd 49 f0 63 63 63 17 47
- INFO: 61 49 cb 73 0a 1a a1 cf aa d8 18 55 2b 72 f5 6d
- INFO: 6f 68 06 67 73 68 61 2d 32 35 36 a4 01 67 53 43
- INFO: 50 5f 42 4c 32 05 58 20 f1 4b 49 87 90 4b cb 58
- INFO: 14 e4 45 9a 05 7e d4 d2 0f 58 a6 33 15 22 88 a7
- INFO: 61 21 4d cd 28 78 0b 56 02 58 20 aa 67 a1 69 b0
- INFO: bb a2 17 aa 0a a8 8a 65 34 69 20 c8 4c 42 44 7c
- INFO: 36 ba 5f 7e a6 5f 42 2c 1f e5 d8 06 67 73 68 61
- INFO: 2d 32 35 36 a4 01 67 41 50 5f 42 4c 33 31 05 58
- INFO: 20 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc
- INFO: 56 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a
- INFO: a3 02 58 20 2e 6d 31 a5 98 3a 91 25 1b fa e5 ae
- INFO: fa 1c 0a 19 d8 ba 3c f6 01 d0 e8 a7 06 b4 cf a9
- INFO: 66 1a 6b 8a 06 67 73 68 61 2d 32 35 36 a4 01 63
- INFO: 52 4d 4d 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
+ INFO: c0 fa 97 3f 7a a3 02 58 20 53 c2 34 e5 e8 47 2b
+ INFO: 6a c5 1c 1a e1 ca b3 fe 06 fa d0 53 be b8 eb fd
+ INFO: 89 77 b0 10 65 5b fd d3 c3 06 67 73 68 61 2d 32
+ INFO: 35 36 a4 01 65 52 53 45 5f 53 05 58 20 53 78 79
+ INFO: 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c
+ INFO: 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20
+ INFO: 11 21 cf cc d5 91 3f 0a 63 fe c4 0a 6f fd 44 ea
+ INFO: 64 f9 dc 13 5c 66 63 4b a0 01 d1 0b cf 43 02 a2
+ INFO: 06 67 73 68 61 2d 32 35 36 a4 01 66 41 50 5f 42
+ INFO: 4c 31 05 58 20 53 78 79 63 07 53 5d f3 ec 8d 8b
+ INFO: 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38 c0
+ INFO: fa 97 3f 7a a3 02 58 20 15 71 b5 ec 78 bd 68 51
+ INFO: 2b f7 83 0b b6 a2 a4 4b 20 47 c7 df 57 bc e7 9e
+ INFO: b8 a1 c0 e5 be a0 a5 01 06 67 73 68 61 2d 32 35
+ INFO: 36 a4 01 66 41 50 5f 42 4c 32 05 58 20 53 78 79
+ INFO: 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c
+ INFO: 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20
+ INFO: 10 15 9b af 26 2b 43 a9 2d 95 db 59 da e1 f7 2c
+ INFO: 64 51 27 30 16 61 e0 a3 ce 4e 38 b2 95 a9 7c 58
+ INFO: 06 67 73 68 61 2d 32 35 36 a4 01 67 53 43 50 5f
+ INFO: 42 4c 31 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
- INFO: c0 fa 97 3f 7a a3 02 58 20 a1 fb 50 e6 c8 6f ae
- INFO: 16 79 ef 33 51 29 6f d6 71 34 11 a0 8c f8 dd 17
- INFO: 90 a4 fd 05 fa e8 68 81 64 06 67 73 68 61 2d 32
- INFO: 35 36 a4 01 69 48 57 5f 43 4f 4e 46 49 47 05 58
+ INFO: c0 fa 97 3f 7a a3 02 58 20 10 12 2e 85 6b 3f cd
+ INFO: 49 f0 63 63 63 17 47 61 49 cb 73 0a 1a a1 cf aa
+ INFO: d8 18 55 2b 72 f5 6d 6f 68 06 67 73 68 61 2d 32
+ INFO: 35 36 a4 01 67 53 43 50 5f 42 4c 32 05 58 20 f1
+ INFO: 4b 49 87 90 4b cb 58 14 e4 45 9a 05 7e d4 d2 0f
+ INFO: 58 a6 33 15 22 88 a7 61 21 4d cd 28 78 0b 56 02
+ INFO: 58 20 aa 67 a1 69 b0 bb a2 17 aa 0a a8 8a 65 34
+ INFO: 69 20 c8 4c 42 44 7c 36 ba 5f 7e a6 5f 42 2c 1f
+ INFO: e5 d8 06 67 73 68 61 2d 32 35 36 a4 01 67 41 50
+ INFO: 5f 42 4c 33 31 05 58 20 53 78 79 63 07 53 5d f3
+ INFO: ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3
+ INFO: 22 38 c0 fa 97 3f 7a a3 02 58 20 2e 6d 31 a5 98
+ INFO: 3a 91 25 1b fa e5 ae fa 1c 0a 19 d8 ba 3c f6 01
+ INFO: d0 e8 a7 06 b4 cf a9 66 1a 6b 8a 06 67 73 68 61
+ INFO: 2d 32 35 36 a4 01 63 52 4d 4d 05 58 20 53 78 79
+ INFO: 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c
+ INFO: 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20
+ INFO: a1 fb 50 e6 c8 6f ae 16 79 ef 33 51 29 6f d6 71
+ INFO: 34 11 a0 8c f8 dd 17 90 a4 fd 05 fa e8 68 81 64
+ INFO: 06 67 73 68 61 2d 32 35 36 a4 01 69 48 57 5f 43
+ INFO: 4f 4e 46 49 47 05 58 20 53 78 79 63 07 53 5d f3
+ INFO: ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3
+ INFO: 22 38 c0 fa 97 3f 7a a3 02 58 20 1a 25 24 02 97
+ INFO: 2f 60 57 fa 53 cc 17 2b 52 b9 ff ca 69 8e 18 31
+ INFO: 1f ac d0 f3 b0 6e ca ae f7 9e 17 06 67 73 68 61
+ INFO: 2d 32 35 36 a4 01 69 46 57 5f 43 4f 4e 46 49 47
+ INFO: 05 58 20 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2
+ INFO: e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97
+ INFO: 3f 7a a3 02 58 20 9a 92 ad bc 0c ee 38 ef 65 8c
+ INFO: 71 ce 1b 1b f8 c6 56 68 f1 66 bf b2 13 64 4c 89
+ INFO: 5c cb 1a d0 7a 25 06 67 73 68 61 2d 32 35 36 a4
+ INFO: 01 6c 54 42 5f 46 57 5f 43 4f 4e 46 49 47 05 58
INFO: 20 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc
INFO: 56 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a
- INFO: a3 02 58 20 1a 25 24 02 97 2f 60 57 fa 53 cc 17
- INFO: 2b 52 b9 ff ca 69 8e 18 31 1f ac d0 f3 b0 6e ca
- INFO: ae f7 9e 17 06 67 73 68 61 2d 32 35 36 a4 01 69
- INFO: 46 57 5f 43 4f 4e 46 49 47 05 58 20 53 78 79 63
- INFO: 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d
- INFO: 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20 9a
- INFO: 92 ad bc 0c ee 38 ef 65 8c 71 ce 1b 1b f8 c6 56
- INFO: 68 f1 66 bf b2 13 64 4c 89 5c cb 1a d0 7a 25 06
- INFO: 67 73 68 61 2d 32 35 36 a4 01 6c 54 42 5f 46 57
- INFO: 5f 43 4f 4e 46 49 47 05 58 20 53 78 79 63 07 53
- INFO: 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60
- INFO: cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20 23 89 03
- INFO: 18 0c c1 04 ec 2c 5d 8b 3f 20 c5 bc 61 b3 89 ec
- INFO: 0a 96 7d f8 cc 20 8c dc 7c d4 54 17 4f 06 67 73
- INFO: 68 61 2d 32 35 36 a4 01 6d 53 4f 43 5f 46 57 5f
- INFO: 43 4f 4e 46 49 47 05 58 20 53 78 79 63 07 53 5d
- INFO: f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf
- INFO: e3 22 38 c0 fa 97 3f 7a a3 02 58 20 e6 c2 1e 8d
- INFO: 26 0f e7 18 82 de bd b3 39 d2 40 2a 2c a7 64 85
- INFO: 29 bc 23 03 f4 86 49 bc e0 38 00 17 06 67 73 68
- INFO: 61 2d 32 35 36 58 60 21 51 20 92 d6 d0 2a e6 be
- INFO: 2f e3 93 0e a5 1f d6 98 96 32 24 56 e9 df c7 32
- INFO: 5e 0b 78 68 b6 90 73 2a 0c 0f 07 77 c1 15 40 4b
- INFO: e1 fc 83 9b 7d 30 4f 4f e6 fa 46 ae 12 a3 08 3a
- INFO: cf 24 06 67 91 06 bf ae 50 31 79 dd 50 33 49 12
- INFO: bf c6 da 33 6d d6 18 25 43 54 4d b5 88 d6 ae 67
- INFO: 35 7a fd b0 5f 95 b7
+ INFO: a3 02 58 20 23 89 03 18 0c c1 04 ec 2c 5d 8b 3f
+ INFO: 20 c5 bc 61 b3 89 ec 0a 96 7d f8 cc 20 8c dc 7c
+ INFO: d4 54 17 4f 06 67 73 68 61 2d 32 35 36 a4 01 6d
+ INFO: 53 4f 43 5f 46 57 5f 43 4f 4e 46 49 47 05 58 20
+ INFO: 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56
+ INFO: 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3
+ INFO: 02 58 20 e6 c2 1e 8d 26 0f e7 18 82 de bd b3 39
+ INFO: d2 40 2a 2c a7 64 85 29 bc 23 03 f4 86 49 bc e0
+ INFO: 38 00 17 06 67 73 68 61 2d 32 35 36 58 60 31 d0
+ INFO: 4d 52 cc de 95 2c 1e 32 cb a1 81 88 5a 40 b8 cc
+ INFO: 38 e0 52 8c 1e 89 58 98 07 64 2a a5 e3 f2 bc 37
+ INFO: f9 53 74 50 6b ff 4d 2e 4b e7 06 3c 4d 72 41 92
+ INFO: 70 c7 22 e8 d4 d9 3e e8 b6 c9 fa ce 3b 43 c9 76
+ INFO: 1a 49 94 1a b6 f3 8f fd ff 49 6a d4 63 b4 cb fa
+ INFO: 11 d8 3e 23 e3 1f 7f 62 32 9d e3 0c 1c c8
INFO: DELEGATED ATTEST TEST END
JSON format:
@@ -584,8 +584,8 @@
.. code-block:: JSON
{
- "CCA_ATTESTATION_PROFILE": "http://arm.com/CCA-SSD/1.0.0",
- "CCA_PLATFORM_CHALLENGE": "b'B5973CB68BAA9FC55558786B7EC67F69E40DF5BA5AA921CD0C27F40587A011EA'",
+ "CCA_ATTESTATION_PROFILE": "tag:arm.com,2023:cca_platform#1.0.0",
+ "CCA_PLATFORM_CHALLENGE": "b'0D22E08A98469058486318283489BDB36F09DBEFEB1864DF433FA6E54EA2D711'",
"CCA_PLATFORM_IMPLEMENTATION_ID": "b'7F454C4602010100000000000000000003003E00010000005058000000000000'",
"CCA_PLATFORM_INSTANCE_ID": "b'0107060504030201000F0E0D0C0B0A090817161514131211101F1E1D1C1B1A1918'",
"CCA_PLATFORM_CONFIG": "b'CFCFCFCF'",
@@ -738,5 +738,5 @@
--------------
-*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
*Copyright (c) 2024, Linaro Limited. All rights reserved.*
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 5d4ab4e..87bb6a5 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst
@@ -85,7 +85,8 @@
Boot with FIP
~~~~~~~~~~~~~
-You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) before building FIP binary.
+You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) and retrieve
+DDR PHY firmware before building FIP binary.
U-Boot
______
@@ -106,9 +107,24 @@
ARCH=arm PLATFORM=stm32mp2 \
CFG_EMBED_DTB_SOURCE_FILE=stm32mp257f-ev1.dts
-TF-A BL2 & BL31
-_______________
-To build TF-A BL2 with its STM32 header and BL31 for SD-card boot:
+DDR PHY firmware
+________________
+DDR PHY firmware files may not be delivered inside TF-A repository, especially
+if you build directly from trustedfirmware.org repository. It then needs to be
+retrieved from `STMicroelectronics DDR PHY github`_.
+
+You can either clone the repository to the default directory:
+
+.. code:: bash
+
+ git clone https://github.com/STMicroelectronics/stm32-ddr-phy-binary.git drivers/st/ddr/phy/firmware/bin
+
+Or clone it somewhere else, and add ``STM32MP_DDR_FW_PATH=`` in your make command
+line when building FIP.
+
+TF-A BL2
+________
+To build TF-A BL2 with its STM32 header for SD-card boot:
.. code:: bash
@@ -136,5 +152,6 @@
.. _STM32MP2 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
.. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
+.. _STMicroelectronics DDR PHY github: https://github.com/STMicroelectronics/stm32-ddr-phy-binary
*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 5643ea1..e672ad7 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -2248,26 +2248,35 @@
::
- Argument : uintptr_t, size_t *, uintptr_t, size_t
+ Argument : uintptr_t, size_t *, uintptr_t, size_t, size_t *
Return : int
-This function returns the Platform attestation token.
+This function returns the Platform attestation token. If the full token does
+not fit in the buffer, the function will return a hunk of the token and
+indicate how many bytes were copied and how many are pending. Multiple calls
+to this function may be needed to retrieve the entire token.
The parameters of the function are:
arg0 - A pointer to the buffer where the Platform token should be copied by
- this function. The buffer must be big enough to hold the Platform
- token.
+ this function. If the platform token does not completely fit in the
+ buffer, the function may return a piece of the token only.
- arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
- function returns the platform token length in this parameter.
+ arg1 - Contains the size (in bytes) of the buffer passed in arg0. In
+ addition, this parameter is used by the function to return the size
+ of the platform token length hunk copied to the buffer.
arg2 - A pointer to the buffer where the challenge object is stored.
arg3 - The length of the challenge object in bytes. Possible values are 32,
- 48 and 64.
+ 48 and 64. This argument must be zero for subsequent calls to
+ retrieve the remaining hunks of the token.
+
+ arg4 - Returns the remaining length of the token (in bytes) that is yet to
+ be returned in further calls.
-The function returns 0 on success, -EINVAL on failure.
+The function returns 0 on success, -EINVAL on failure and -EAGAIN if the
+resource associated with the platform token retrieval is busy.
Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/fdts/stm32mp25-bl2.dtsi b/fdts/stm32mp25-bl2.dtsi
index 769aab2..e250e3f 100644
--- a/fdts/stm32mp25-bl2.dtsi
+++ b/fdts/stm32mp25-bl2.dtsi
@@ -21,6 +21,9 @@
st-io_policies {
fip-handles {
compatible = "st,io-fip-handle";
+#if STM32MP_DDR_FIP_IO_STORAGE
+ ddr_fw_uuid = "b11249be-92dd-4b10-867c-2c6a4b47a7fb";
+#endif
fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e";
bl31_uuid = "47d4086d-4cfe-9846-9b95-2950cbbd5a00";
bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38";
diff --git a/fdts/stm32mp25-fw-config.dtsi b/fdts/stm32mp25-fw-config.dtsi
index b187ad2..102980d 100644
--- a/fdts/stm32mp25-fw-config.dtsi
+++ b/fdts/stm32mp25-fw-config.dtsi
@@ -25,6 +25,12 @@
id = <BL33_IMAGE_ID>;
};
+ soc_fw {
+ load-address = <0x0 STM32MP_SYSRAM_BASE>;
+ max-size = <STM32MP_BL31_SIZE>;
+ id = <BL31_IMAGE_ID>;
+ };
+
tos_fw {
id = <BL32_IMAGE_ID>;
};
diff --git a/include/drivers/st/stm32mp_risab_regs.h b/include/drivers/st/stm32mp_risab_regs.h
new file mode 100644
index 0000000..1f49bf6
--- /dev/null
+++ b/include/drivers/st/stm32mp_risab_regs.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_RISAB_REGS_H
+#define STM32MP_RISAB_REGS_H
+
+#define RISAB_CR U(0x00)
+#define RISAB_IASR U(0x08)
+#define RISAB_IACR U(0x0C)
+#define RISAB_RIFLOCKR U(0x10)
+#define RISAB_IAESR U(0x20)
+#define RISAB_IADDR U(0x24)
+#define RISAB_PG0_SECCFGR U(0x100)
+#define RISAB_PG1_SECCFGR U(0x104)
+#define RISAB_PG2_SECCFGR U(0x108)
+#define RISAB_PG3_SECCFGR U(0x10C)
+#define RISAB_PG4_SECCFGR U(0x110)
+#define RISAB_PG5_SECCFGR U(0x114)
+#define RISAB_PG6_SECCFGR U(0x118)
+#define RISAB_PG7_SECCFGR U(0x11C)
+#define RISAB_PG8_SECCFGR U(0x120)
+#define RISAB_PG9_SECCFGR U(0x124)
+#define RISAB_PG10_SECCFGR U(0x128)
+#define RISAB_PG11_SECCFGR U(0x12C)
+#define RISAB_PG12_SECCFGR U(0x130)
+#define RISAB_PG13_SECCFGR U(0x134)
+#define RISAB_PG14_SECCFGR U(0x138)
+#define RISAB_PG15_SECCFGR U(0x13C)
+#define RISAB_PG16_SECCFGR U(0x140)
+#define RISAB_PG17_SECCFGR U(0x144)
+#define RISAB_PG18_SECCFGR U(0x148)
+#define RISAB_PG19_SECCFGR U(0x14C)
+#define RISAB_PG20_SECCFGR U(0x150)
+#define RISAB_PG21_SECCFGR U(0x154)
+#define RISAB_PG22_SECCFGR U(0x158)
+#define RISAB_PG23_SECCFGR U(0x15C)
+#define RISAB_PG24_SECCFGR U(0x160)
+#define RISAB_PG25_SECCFGR U(0x164)
+#define RISAB_PG26_SECCFGR U(0x168)
+#define RISAB_PG27_SECCFGR U(0x16C)
+#define RISAB_PG28_SECCFGR U(0x170)
+#define RISAB_PG29_SECCFGR U(0x174)
+#define RISAB_PG30_SECCFGR U(0x178)
+#define RISAB_PG31_SECCFGR U(0x17C)
+#define RISAB_PG0_PRIVCFGR U(0x200)
+#define RISAB_PG1_PRIVCFGR U(0x204)
+#define RISAB_PG2_PRIVCFGR U(0x208)
+#define RISAB_PG3_PRIVCFGR U(0x20C)
+#define RISAB_PG4_PRIVCFGR U(0x210)
+#define RISAB_PG5_PRIVCFGR U(0x214)
+#define RISAB_PG6_PRIVCFGR U(0x218)
+#define RISAB_PG7_PRIVCFGR U(0x21C)
+#define RISAB_PG8_PRIVCFGR U(0x220)
+#define RISAB_PG9_PRIVCFGR U(0x224)
+#define RISAB_PG10_PRIVCFGR U(0x228)
+#define RISAB_PG11_PRIVCFGR U(0x22C)
+#define RISAB_PG12_PRIVCFGR U(0x230)
+#define RISAB_PG13_PRIVCFGR U(0x234)
+#define RISAB_PG14_PRIVCFGR U(0x238)
+#define RISAB_PG15_PRIVCFGR U(0x23C)
+#define RISAB_PG16_PRIVCFGR U(0x240)
+#define RISAB_PG17_PRIVCFGR U(0x244)
+#define RISAB_PG18_PRIVCFGR U(0x248)
+#define RISAB_PG19_PRIVCFGR U(0x24C)
+#define RISAB_PG20_PRIVCFGR U(0x250)
+#define RISAB_PG21_PRIVCFGR U(0x254)
+#define RISAB_PG22_PRIVCFGR U(0x258)
+#define RISAB_PG23_PRIVCFGR U(0x25C)
+#define RISAB_PG24_PRIVCFGR U(0x260)
+#define RISAB_PG25_PRIVCFGR U(0x264)
+#define RISAB_PG26_PRIVCFGR U(0x268)
+#define RISAB_PG27_PRIVCFGR U(0x26C)
+#define RISAB_PG28_PRIVCFGR U(0x270)
+#define RISAB_PG29_PRIVCFGR U(0x274)
+#define RISAB_PG30_PRIVCFGR U(0x278)
+#define RISAB_PG31_PRIVCFGR U(0x27C)
+#define RISAB_PG0_C2PRIVCFGR U(0x600)
+#define RISAB_PG1_C2PRIVCFGR U(0x604)
+#define RISAB_PG2_C2PRIVCFGR U(0x608)
+#define RISAB_PG3_C2PRIVCFGR U(0x60C)
+#define RISAB_PG4_C2PRIVCFGR U(0x610)
+#define RISAB_PG5_C2PRIVCFGR U(0x614)
+#define RISAB_PG6_C2PRIVCFGR U(0x618)
+#define RISAB_PG7_C2PRIVCFGR U(0x61C)
+#define RISAB_PG8_C2PRIVCFGR U(0x620)
+#define RISAB_PG9_C2PRIVCFGR U(0x624)
+#define RISAB_PG10_C2PRIVCFGR U(0x628)
+#define RISAB_PG11_C2PRIVCFGR U(0x62C)
+#define RISAB_PG12_C2PRIVCFGR U(0x630)
+#define RISAB_PG13_C2PRIVCFGR U(0x634)
+#define RISAB_PG14_C2PRIVCFGR U(0x638)
+#define RISAB_PG15_C2PRIVCFGR U(0x63C)
+#define RISAB_PG16_C2PRIVCFGR U(0x640)
+#define RISAB_PG17_C2PRIVCFGR U(0x644)
+#define RISAB_PG18_C2PRIVCFGR U(0x648)
+#define RISAB_PG19_C2PRIVCFGR U(0x64C)
+#define RISAB_PG20_C2PRIVCFGR U(0x650)
+#define RISAB_PG21_C2PRIVCFGR U(0x654)
+#define RISAB_PG22_C2PRIVCFGR U(0x658)
+#define RISAB_PG23_C2PRIVCFGR U(0x65C)
+#define RISAB_PG24_C2PRIVCFGR U(0x660)
+#define RISAB_PG25_C2PRIVCFGR U(0x664)
+#define RISAB_PG26_C2PRIVCFGR U(0x668)
+#define RISAB_PG27_C2PRIVCFGR U(0x66C)
+#define RISAB_PG28_C2PRIVCFGR U(0x670)
+#define RISAB_PG29_C2PRIVCFGR U(0x674)
+#define RISAB_PG30_C2PRIVCFGR U(0x678)
+#define RISAB_PG31_C2PRIVCFGR U(0x67C)
+#define RISAB_CID0PRIVCFGR U(0x800)
+#define RISAB_CID0RDCFGR U(0x808)
+#define RISAB_CID0WRCFGR U(0x810)
+#define RISAB_CID1PRIVCFGR U(0x820)
+#define RISAB_CID1RDCFGR U(0x828)
+#define RISAB_CID1WRCFGR U(0x830)
+#define RISAB_CID2PRIVCFGR U(0x840)
+#define RISAB_CID2RDCFGR U(0x848)
+#define RISAB_CID2WRCFGR U(0x850)
+#define RISAB_CID3PRIVCFGR U(0x860)
+#define RISAB_CID3RDCFGR U(0x868)
+#define RISAB_CID3WRCFGR U(0x870)
+#define RISAB_CID4PRIVCFGR U(0x880)
+#define RISAB_CID4RDCFGR U(0x888)
+#define RISAB_CID4WRCFGR U(0x890)
+#define RISAB_CID5PRIVCFGR U(0x8A0)
+#define RISAB_CID5RDCFGR U(0x8A8)
+#define RISAB_CID5WRCFGR U(0x8B0)
+#define RISAB_CID6PRIVCFGR U(0x8C0)
+#define RISAB_CID6RDCFGR U(0x8C8)
+#define RISAB_CID6WRCFGR U(0x8D0)
+#define RISAB_PG0_CIDCFGR U(0xA00)
+#define RISAB_PG1_CIDCFGR U(0xA04)
+#define RISAB_PG2_CIDCFGR U(0xA08)
+#define RISAB_PG3_CIDCFGR U(0xA0C)
+#define RISAB_PG4_CIDCFGR U(0xA10)
+#define RISAB_PG5_CIDCFGR U(0xA14)
+#define RISAB_PG6_CIDCFGR U(0xA18)
+#define RISAB_PG7_CIDCFGR U(0xA1C)
+#define RISAB_PG8_CIDCFGR U(0xA20)
+#define RISAB_PG9_CIDCFGR U(0xA24)
+#define RISAB_PG10_CIDCFGR U(0xA28)
+#define RISAB_PG11_CIDCFGR U(0xA2C)
+#define RISAB_PG12_CIDCFGR U(0xA30)
+#define RISAB_PG13_CIDCFGR U(0xA34)
+#define RISAB_PG14_CIDCFGR U(0xA38)
+#define RISAB_PG15_CIDCFGR U(0xA3C)
+#define RISAB_PG16_CIDCFGR U(0xA40)
+#define RISAB_PG17_CIDCFGR U(0xA44)
+#define RISAB_PG18_CIDCFGR U(0xA48)
+#define RISAB_PG19_CIDCFGR U(0xA4C)
+#define RISAB_PG20_CIDCFGR U(0xA50)
+#define RISAB_PG21_CIDCFGR U(0xA54)
+#define RISAB_PG22_CIDCFGR U(0xA58)
+#define RISAB_PG23_CIDCFGR U(0xA5C)
+#define RISAB_PG24_CIDCFGR U(0xA60)
+#define RISAB_PG25_CIDCFGR U(0xA64)
+#define RISAB_PG26_CIDCFGR U(0xA68)
+#define RISAB_PG27_CIDCFGR U(0xA6C)
+#define RISAB_PG28_CIDCFGR U(0xA70)
+#define RISAB_PG29_CIDCFGR U(0xA74)
+#define RISAB_PG30_CIDCFGR U(0xA78)
+#define RISAB_PG31_CIDCFGR U(0xA7C)
+#define RISAB_HWCFGR3 U(0xFE8)
+#define RISAB_HWCFGR2 U(0xFEC)
+#define RISAB_HWCFGR1 U(0xFF0)
+#define RISAB_VERR U(0xFF4)
+#define RISAB_IPIDR U(0xFF8)
+#define RISAB_SIDR U(0xFFC)
+
+/* RISAB_CR register fields */
+#define RISAB_CR_GLOCK BIT(0)
+#define RISAB_CR_SRWIAD BIT(31)
+
+/* RISAB_IASR register fields */
+#define RISAB_IASR_CAEF BIT(0)
+#define RISAB_IASR_IAEF BIT(1)
+
+/* RISAB_IACR register fields */
+#define RISAB_IACR_CAEF BIT(0)
+#define RISAB_IACR_IAEF BIT(1)
+
+/* RISAB_RIFLOCKR register fields */
+#define RISAB_RIFLOCKR_RLOCK0 BIT(0)
+#define RISAB_RIFLOCKR_RLOCK1 BIT(1)
+#define RISAB_RIFLOCKR_RLOCK2 BIT(2)
+#define RISAB_RIFLOCKR_RLOCK3 BIT(3)
+#define RISAB_RIFLOCKR_RLOCK4 BIT(4)
+#define RISAB_RIFLOCKR_RLOCK5 BIT(5)
+#define RISAB_RIFLOCKR_RLOCK6 BIT(6)
+#define RISAB_RIFLOCKR_RLOCK7 BIT(7)
+#define RISAB_RIFLOCKR_RLOCK8 BIT(8)
+#define RISAB_RIFLOCKR_RLOCK9 BIT(9)
+#define RISAB_RIFLOCKR_RLOCK10 BIT(10)
+#define RISAB_RIFLOCKR_RLOCK11 BIT(11)
+#define RISAB_RIFLOCKR_RLOCK12 BIT(12)
+#define RISAB_RIFLOCKR_RLOCK13 BIT(13)
+#define RISAB_RIFLOCKR_RLOCK14 BIT(14)
+#define RISAB_RIFLOCKR_RLOCK15 BIT(15)
+#define RISAB_RIFLOCKR_RLOCK16 BIT(16)
+#define RISAB_RIFLOCKR_RLOCK17 BIT(17)
+#define RISAB_RIFLOCKR_RLOCK18 BIT(18)
+#define RISAB_RIFLOCKR_RLOCK19 BIT(19)
+#define RISAB_RIFLOCKR_RLOCK20 BIT(20)
+#define RISAB_RIFLOCKR_RLOCK21 BIT(21)
+#define RISAB_RIFLOCKR_RLOCK22 BIT(22)
+#define RISAB_RIFLOCKR_RLOCK23 BIT(23)
+#define RISAB_RIFLOCKR_RLOCK24 BIT(24)
+#define RISAB_RIFLOCKR_RLOCK25 BIT(25)
+#define RISAB_RIFLOCKR_RLOCK26 BIT(26)
+#define RISAB_RIFLOCKR_RLOCK27 BIT(27)
+#define RISAB_RIFLOCKR_RLOCK28 BIT(28)
+#define RISAB_RIFLOCKR_RLOCK29 BIT(29)
+#define RISAB_RIFLOCKR_RLOCK30 BIT(30)
+#define RISAB_RIFLOCKR_RLOCK31 BIT(31)
+
+/* RISAB_IAESR register fields */
+#define RISAB_IAESR_IACID_MASK GENMASK(2, 0)
+#define RISAB_IAESR_IACID_SHIFT 0
+#define RISAB_IAESR_IAPRIV BIT(4)
+#define RISAB_IAESR_IASEC BIT(5)
+#define RISAB_IAESR_IANRW BIT(7)
+
+/* RISAB_PGx_SECCFGR register fields */
+#define RISAB_PGx_SECCFGR_SEC(_y) BIT(_y)
+
+/* RISAB_PGx_PRIVCFGR register fields */
+#define RISAB_PGx_PRIVCFGR_PRIV(_y) BIT(_y)
+
+/* RISAB_PGx_CmPRIVCFGR register fields */
+#define RISAB_PGx_CmPRIVCFGR_PRIV(_y) BIT(_y)
+
+/* RISAB_CIDxPRIVCFGR register fields */
+#define RISAB_CIDxPRIVCFGR_PPRIV(_y) BIT(_y)
+
+/* RISAB_CIDxRDCFGR register fields */
+#define RISAB_CIDxRDCFGR_PRDEN(_y) BIT(_y)
+
+/* RISAB_CIDxWRCFGR register fields */
+#define RISAB_CIDxWRCFGR_PWREN(_y) BIT(_y)
+
+/* RISAB_PGx_CIDCFGR register fields */
+#define RISAB_PGx_CIDCFGR_CFEN BIT(0)
+#define RISAB_PGx_CIDCFGR_DCEN BIT(2)
+#define RISAB_PGx_CIDCFGR_DCCID_MASK GENMASK(6, 4)
+#define RISAB_PGx_CIDCFGR_DCCID_SHIFT 4
+
+/* RISAB_HWCFGR1 register fields */
+#define RISAB_HWCFGR1_CFG1_MASK GENMASK(3, 0)
+#define RISAB_HWCFGR1_CFG1_SHIFT 0
+#define RISAB_HWCFGR1_CFG2_MASK GENMASK(7, 4)
+#define RISAB_HWCFGR1_CFG2_SHIFT 4
+#define RISAB_HWCFGR1_CFG3_MASK GENMASK(11, 8)
+#define RISAB_HWCFGR1_CFG3_SHIFT 8
+#define RISAB_HWCFGR1_CFG4_MASK GENMASK(15, 12)
+#define RISAB_HWCFGR1_CFG4_SHIFT 12
+#define RISAB_HWCFGR1_CFG5_MASK GENMASK(19, 16)
+#define RISAB_HWCFGR1_CFG5_SHIFT 16
+#define RISAB_HWCFGR1_CFG6_MASK GENMASK(23, 20)
+#define RISAB_HWCFGR1_CFG6_SHIFT 20
+#define RISAB_HWCFGR1_CFG7_MASK GENMASK(27, 24)
+#define RISAB_HWCFGR1_CFG7_SHIFT 24
+
+/* RISAB_VERR register fields */
+#define RISAB_VERR_MINREV_MASK GENMASK(3, 0)
+#define RISAB_VERR_MINREV_SHIFT 0
+#define RISAB_VERR_MAJREV_MASK GENMASK(7, 4)
+#define RISAB_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP_RISAB_REGS_H */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 1015fca..ae5aa23 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -370,8 +370,10 @@
* Mandatory BL31 functions when ENABLE_RME=1
******************************************************************************/
#if ENABLE_RME
+
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
- uintptr_t hash, size_t hash_size);
+ uintptr_t hash, size_t hash_size,
+ uint64_t *remaining_len);
int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
unsigned int type);
size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared);
diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h
index a567d28..4615ffb 100644
--- a/include/services/rmmd_svc.h
+++ b/include/services/rmmd_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -90,6 +90,7 @@
#define E_RMM_BAD_PAS -3
#define E_RMM_NOMEM -4
#define E_RMM_INVAL -5
+#define E_RMM_AGAIN -6
/* Return error codes from RMI SMCs */
#define RMI_SUCCESS 0
@@ -156,7 +157,7 @@
* Increase this when a bug is fixed, or a feature is added without
* breaking compatibility.
*/
-#define RMM_EL3_IFC_VERSION_MINOR (U(2))
+#define RMM_EL3_IFC_VERSION_MINOR (U(3))
#define RMM_EL3_INTERFACE_VERSION \
(((RMM_EL3_IFC_VERSION_MAJOR << 16) & 0x7FFFF) | \
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index d028fce..79c4ea5 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -495,7 +495,7 @@
*
* Parameters
* l0_mem_base Base address of memory used for L0 tables.
- * l1_mem_size Size of memory available for L0 tables.
+ * l0_mem_size Size of memory available for L0 tables.
*
* Return
* Negative Linux error code in the event of a failure, 0 for success.
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index ceff4ba..675779f 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -310,7 +310,7 @@
ifeq ($(CTX_INCLUDE_MTE_REGS),1)
$(warning CTX_INCLUDE_MTE_REGS option is deprecated, Check ENABLE_FEAT_MTE2 usage)
endif
-ifeq ($(ENABLE_FEAT_MTE),1)
+ifneq ($(ENABLE_FEAT_MTE),)
$(warning ENABLE_FEAT_MTE option is deprecated, Check ENABLE_FEAT_MTE2 usage)
endif
diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c
index 83b52fc..0894bf7 100644
--- a/plat/arm/board/fvp/fvp_plat_attest_token.c
+++ b/plat/arm/board/fvp/fvp_plat_attest_token.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2024, Linaro Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -16,213 +16,244 @@
*/
static const uint8_t sample_platform_token[] = {
0xd2, 0x84, 0x44, 0xa1, 0x01, 0x38, 0x22, 0xa0,
- 0x59, 0x05, 0x7a, 0xa9, 0x19, 0x01, 0x09, 0x78,
- 0x1c, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f,
- 0x61, 0x72, 0x6d, 0x2e, 0x63, 0x6f, 0x6d, 0x2f,
- 0x43, 0x43, 0x41, 0x2d, 0x53, 0x53, 0x44, 0x2f,
- 0x31, 0x2e, 0x30, 0x2e, 0x30, 0x0a, 0x58, 0x20,
- 0xb5, 0x97, 0x3c, 0xb6, 0x8b, 0xaa, 0x9f, 0xc5,
- 0x55, 0x58, 0x78, 0x6b, 0x7e, 0xc6, 0x7f, 0x69,
- 0xe4, 0x0d, 0xf5, 0xba, 0x5a, 0xa9, 0x21, 0xcd,
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- 0xae, 0xf7, 0x9e, 0x17, 0x06, 0x67, 0x73, 0x68,
- 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x69,
- 0x46, 0x57, 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49,
- 0x47, 0x05, 0x58, 0x20, 0x53, 0x78, 0x79, 0x63,
- 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15,
- 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d,
- 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa,
- 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x9a,
- 0x92, 0xad, 0xbc, 0x0c, 0xee, 0x38, 0xef, 0x65,
- 0x8c, 0x71, 0xce, 0x1b, 0x1b, 0xf8, 0xc6, 0x56,
- 0x68, 0xf1, 0x66, 0xbf, 0xb2, 0x13, 0x64, 0x4c,
- 0x89, 0x5c, 0xcb, 0x1a, 0xd0, 0x7a, 0x25, 0x06,
- 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36,
- 0xa4, 0x01, 0x6c, 0x54, 0x42, 0x5f, 0x46, 0x57,
- 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05,
- 0x58, 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53,
- 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2,
- 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60,
- 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f,
- 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x23, 0x89, 0x03,
- 0x18, 0x0c, 0xc1, 0x04, 0xec, 0x2c, 0x5d, 0x8b,
- 0x3f, 0x20, 0xc5, 0xbc, 0x61, 0xb3, 0x89, 0xec,
- 0x0a, 0x96, 0x7d, 0xf8, 0xcc, 0x20, 0x8c, 0xdc,
- 0x7c, 0xd4, 0x54, 0x17, 0x4f, 0x06, 0x67, 0x73,
- 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01,
- 0x6d, 0x53, 0x4f, 0x43, 0x5f, 0x46, 0x57, 0x5f,
+ 0x5f, 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20, 0xf1,
+ 0x4b, 0x49, 0x87, 0x90, 0x4b, 0xcb, 0x58, 0x14,
+ 0xe4, 0x45, 0x9a, 0x05, 0x7e, 0xd4, 0xd2, 0x0f,
+ 0x58, 0xa6, 0x33, 0x15, 0x22, 0x88, 0xa7, 0x61,
+ 0x21, 0x4d, 0xcd, 0x28, 0x78, 0x0b, 0x56, 0x02,
+ 0x58, 0x20, 0xaa, 0x67, 0xa1, 0x69, 0xb0, 0xbb,
+ 0xa2, 0x17, 0xaa, 0x0a, 0xa8, 0x8a, 0x65, 0x34,
+ 0x69, 0x20, 0xc8, 0x4c, 0x42, 0x44, 0x7c, 0x36,
+ 0xba, 0x5f, 0x7e, 0xa6, 0x5f, 0x42, 0x2c, 0x1f,
+ 0xe5, 0xd8, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d,
+ 0x32, 0x35, 0x36, 0xa4, 0x01, 0x67, 0x41, 0x50,
+ 0x5f, 0x42, 0x4c, 0x33, 0x31, 0x05, 0x58, 0x20,
+ 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3,
+ 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56,
+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0x2e, 0x6d, 0x31, 0xa5, 0x98,
+ 0x3a, 0x91, 0x25, 0x1b, 0xfa, 0xe5, 0xae, 0xfa,
+ 0x1c, 0x0a, 0x19, 0xd8, 0xba, 0x3c, 0xf6, 0x01,
+ 0xd0, 0xe8, 0xa7, 0x06, 0xb4, 0xcf, 0xa9, 0x66,
+ 0x1a, 0x6b, 0x8a, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x63, 0x52,
+ 0x4d, 0x4d, 0x05, 0x58, 0x20, 0x53, 0x78, 0x79,
+ 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b,
+ 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c,
+ 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0,
+ 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20,
+ 0xa1, 0xfb, 0x50, 0xe6, 0xc8, 0x6f, 0xae, 0x16,
+ 0x79, 0xef, 0x33, 0x51, 0x29, 0x6f, 0xd6, 0x71,
+ 0x34, 0x11, 0xa0, 0x8c, 0xf8, 0xdd, 0x17, 0x90,
+ 0xa4, 0xfd, 0x05, 0xfa, 0xe8, 0x68, 0x81, 0x64,
+ 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35,
+ 0x36, 0xa4, 0x01, 0x69, 0x48, 0x57, 0x5f, 0x43,
+ 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58, 0x20,
+ 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3,
+ 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56,
+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0x1a, 0x25, 0x24, 0x02, 0x97,
+ 0x2f, 0x60, 0x57, 0xfa, 0x53, 0xcc, 0x17, 0x2b,
+ 0x52, 0xb9, 0xff, 0xca, 0x69, 0x8e, 0x18, 0x31,
+ 0x1f, 0xac, 0xd0, 0xf3, 0xb0, 0x6e, 0xca, 0xae,
+ 0xf7, 0x9e, 0x17, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x69, 0x46,
+ 0x57, 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47,
+ 0x05, 0x58, 0x20, 0x53, 0x78, 0x79, 0x63, 0x07,
+ 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2,
+ 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30,
+ 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97,
+ 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x9a, 0x92,
+ 0xad, 0xbc, 0x0c, 0xee, 0x38, 0xef, 0x65, 0x8c,
+ 0x71, 0xce, 0x1b, 0x1b, 0xf8, 0xc6, 0x56, 0x68,
+ 0xf1, 0x66, 0xbf, 0xb2, 0x13, 0x64, 0x4c, 0x89,
+ 0x5c, 0xcb, 0x1a, 0xd0, 0x7a, 0x25, 0x06, 0x67,
+ 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4,
+ 0x01, 0x6c, 0x54, 0x42, 0x5f, 0x46, 0x57, 0x5f,
0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58,
0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
- 0xa3, 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d,
- 0x26, 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3,
- 0x39, 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85,
- 0x29, 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc,
- 0xe0, 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68,
- 0x61, 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x21,
- 0x51, 0x20, 0x92, 0xd6, 0xd0, 0x2a, 0xe6, 0xbe,
- 0x2f, 0xe3, 0x93, 0x0e, 0xa5, 0x1f, 0xd6, 0x98,
- 0x96, 0x32, 0x24, 0x56, 0xe9, 0xdf, 0xc7, 0x32,
- 0x5e, 0x0b, 0x78, 0x68, 0xb6, 0x90, 0x73, 0x2a,
- 0x0c, 0x0f, 0x07, 0x77, 0xc1, 0x15, 0x40, 0x4b,
- 0xe1, 0xfc, 0x83, 0x9b, 0x7d, 0x30, 0x4f, 0x4f,
- 0xe6, 0xfa, 0x46, 0xae, 0x12, 0xa3, 0x08, 0x3a,
- 0xcf, 0x24, 0x06, 0x67, 0x91, 0x06, 0xbf, 0xae,
- 0x50, 0x31, 0x79, 0xdd, 0x50, 0x33, 0x49, 0x12,
- 0xbf, 0xc6, 0xda, 0x33, 0x6d, 0xd6, 0x18, 0x25,
- 0x43, 0x54, 0x4d, 0xb5, 0x88, 0xd6, 0xae, 0x67,
- 0x35, 0x7a, 0xfd, 0xb0, 0x5f, 0x95, 0xb7
+ 0xa3, 0x02, 0x58, 0x20, 0x23, 0x89, 0x03, 0x18,
+ 0x0c, 0xc1, 0x04, 0xec, 0x2c, 0x5d, 0x8b, 0x3f,
+ 0x20, 0xc5, 0xbc, 0x61, 0xb3, 0x89, 0xec, 0x0a,
+ 0x96, 0x7d, 0xf8, 0xcc, 0x20, 0x8c, 0xdc, 0x7c,
+ 0xd4, 0x54, 0x17, 0x4f, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x6d,
+ 0x53, 0x4f, 0x43, 0x5f, 0x46, 0x57, 0x5f, 0x43,
+ 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58, 0x20,
+ 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3,
+ 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56,
+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d, 0x26,
+ 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3, 0x39,
+ 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85, 0x29,
+ 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc, 0xe0,
+ 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x31, 0xd0,
+ 0x4d, 0x52, 0xcc, 0xde, 0x95, 0x2c, 0x1e, 0x32,
+ 0xcb, 0xa1, 0x81, 0x88, 0x5a, 0x40, 0xb8, 0xcc,
+ 0x38, 0xe0, 0x52, 0x8c, 0x1e, 0x89, 0x58, 0x98,
+ 0x07, 0x64, 0x2a, 0xa5, 0xe3, 0xf2, 0xbc, 0x37,
+ 0xf9, 0x53, 0x74, 0x50, 0x6b, 0xff, 0x4d, 0x2e,
+ 0x4b, 0xe7, 0x06, 0x3c, 0x4d, 0x72, 0x41, 0x92,
+ 0x70, 0xc7, 0x22, 0xe8, 0xd4, 0xd9, 0x3e, 0xe8,
+ 0xb6, 0xc9, 0xfa, 0xce, 0x3b, 0x43, 0xc9, 0x76,
+ 0x1a, 0x49, 0x94, 0x1a, 0xb6, 0xf3, 0x8f, 0xfd,
+ 0xff, 0x49, 0x6a, 0xd4, 0x63, 0xb4, 0xcb, 0xfa,
+ 0x11, 0xd8, 0x3e, 0x23, 0xe3, 0x1f, 0x7f, 0x62,
+ 0x32, 0x9d, 0xe3, 0x0c, 0x1c, 0xc8
};
+static uint64_t platform_token_offset;
/*
* Get the hardcoded platform attestation token as FVP does not support
* RSE.
+ *
+ * Note: This implementation caters for retrieval of the platform token
+ * in hunks to facilitate EL3-RMM interface testing. For most platforms,
+ * since the shared buffer size is known, the implementation can be more
+ * optimized.
*/
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
- uintptr_t hash, size_t hash_size)
+ uintptr_t hash, size_t hash_size,
+ size_t *remaining_len)
{
(void)hash;
(void)hash_size;
+ size_t platform_token_size = sizeof(sample_platform_token);
+ size_t local_hunk_len;
+ size_t local_remaining_len;
- if (*len < sizeof(sample_platform_token)) {
+ if (hash_size != 0) {
+ platform_token_offset = 0;
+ } else if (platform_token_offset == 0) {
return -EINVAL;
}
+ local_hunk_len = *len;
+ local_remaining_len = platform_token_size - platform_token_offset;
+
+ /*
+ * If the buffer is enough to fit the remaining bytes of the token,
+ * return only the remaining bytes of the token.
+ */
+ if (local_hunk_len >= local_remaining_len) {
+ local_hunk_len = local_remaining_len;
+ }
+ /* Update remaining bytes according to hunk size */
+ local_remaining_len -= local_hunk_len;
+
+ (void)memcpy((void *)buf,
+ (const void *)sample_platform_token
+ + platform_token_offset,
+ local_hunk_len);
+
- (void)memcpy((void *)buf, (const void *)sample_platform_token,
- sizeof(sample_platform_token));
- *len = sizeof(sample_platform_token);
+ platform_token_offset += local_hunk_len;
+ *len = local_hunk_len;
+ *remaining_len = local_remaining_len;
return 0;
}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 56de8b8..a900a9b 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -297,7 +297,9 @@
* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
-# define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000)
+# define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
+ ARM_SHARED_RAM_SIZE - \
+ ARM_FW_CONFIGS_SIZE)
#endif /* RESET_TO_SP_MIN */
#endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 340eb38..bbd9141 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -76,6 +76,7 @@
ENABLE_FEAT_S1PIE := 2
ENABLE_FEAT_S2POE := 2
ENABLE_FEAT_S1POE := 2
+ENABLE_FEAT_MTE2 := 2
# The FVP platform depends on this macro to build with correct GIC driver.
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c
index 188a09f..5584662 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c
@@ -4,23 +4,32 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
#include <errno.h>
#include <stdint.h>
#include <cca_attestation.h>
#include <common/debug.h>
+#include <plat/common/common_def.h>
#include <psa/error.h>
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
- uintptr_t hash, size_t hash_size)
+ uintptr_t hash, size_t hash_size,
+ size_t *remaining_len)
{
psa_status_t ret;
+ assert(*len == SZ_4K);
+
ret = cca_attestation_get_plat_token(buf, len, hash, hash_size);
if (ret != PSA_SUCCESS) {
ERROR("Unable to fetch CCA attestation token\n");
return -1;
}
+ assert(*len <= SZ_4K);
+
+ *remaining_len = 0;
+
return 0;
}
diff --git a/plat/mediatek/common/mtk_smc_handlers.c b/plat/mediatek/common/mtk_smc_handlers.c
index 5a3ad1f..beb06da 100644
--- a/plat/mediatek/common/mtk_smc_handlers.c
+++ b/plat/mediatek/common/mtk_smc_handlers.c
@@ -99,13 +99,13 @@
{
const struct smc_descriptor *p_smc_desc;
- INFO("print smc descriptor pool\n");
+ VERBOSE("print smc descriptor pool\n");
for (p_smc_desc = &pool[0];
(char *)p_smc_desc < (char *)MTK_SMC_POOL_END_UNALIGNED;
p_smc_desc++) {
- INFO("descriptor name:%s\n", p_smc_desc->smc_name);
- INFO("descriptor index:%d\n", *p_smc_desc->smc_descriptor_index);
- INFO("smc id 32:0x%x, smc id 64:0x%x\n",
+ VERBOSE("descriptor name:%s\n", p_smc_desc->smc_name);
+ VERBOSE("descriptor index:%d\n", *p_smc_desc->smc_descriptor_index);
+ VERBOSE("smc id 32:0x%x, smc id 64:0x%x\n",
p_smc_desc->smc_id_aarch32, p_smc_desc->smc_id_aarch64);
}
}
diff --git a/plat/qemu/common/qemu_plat_attest_token.c b/plat/qemu/common/qemu_plat_attest_token.c
index 141ff57..7b54271 100644
--- a/plat/qemu/common/qemu_plat_attest_token.c
+++ b/plat/qemu/common/qemu_plat_attest_token.c
@@ -16,194 +16,195 @@
*/
static const uint8_t sample_platform_token[] = {
0xd2, 0x84, 0x44, 0xa1, 0x01, 0x38, 0x22, 0xa0,
- 0x59, 0x05, 0x7a, 0xa9, 0x19, 0x01, 0x09, 0x78,
- 0x1c, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f,
- 0x61, 0x72, 0x6d, 0x2e, 0x63, 0x6f, 0x6d, 0x2f,
- 0x43, 0x43, 0x41, 0x2d, 0x53, 0x53, 0x44, 0x2f,
- 0x31, 0x2e, 0x30, 0x2e, 0x30, 0x0a, 0x58, 0x20,
- 0xb5, 0x97, 0x3c, 0xb6, 0x8b, 0xaa, 0x9f, 0xc5,
- 0x55, 0x58, 0x78, 0x6b, 0x7e, 0xc6, 0x7f, 0x69,
- 0xe4, 0x0d, 0xf5, 0xba, 0x5a, 0xa9, 0x21, 0xcd,
- 0x0c, 0x27, 0xf4, 0x05, 0x87, 0xa0, 0x11, 0xea,
- 0x19, 0x09, 0x5c, 0x58, 0x20, 0x7f, 0x45, 0x4c,
- 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3e,
- 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
- 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
- 0x02, 0x01, 0x00, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b,
- 0x0a, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
- 0x12, 0x11, 0x10, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b,
- 0x1a, 0x19, 0x18, 0x19, 0x09, 0x61, 0x44, 0xcf,
- 0xcf, 0xcf, 0xcf, 0x19, 0x09, 0x5b, 0x19, 0x30,
- 0x03, 0x19, 0x09, 0x62, 0x67, 0x73, 0x68, 0x61,
- 0x2d, 0x32, 0x35, 0x36, 0x19, 0x09, 0x60, 0x78,
- 0x3a, 0x68, 0x74, 0x74, 0x70, 0x73, 0x3a, 0x2f,
- 0x2f, 0x76, 0x65, 0x72, 0x61, 0x69, 0x73, 0x6f,
- 0x6e, 0x2e, 0x65, 0x78, 0x61, 0x6d, 0x70, 0x6c,
- 0x65, 0x2f, 0x2e, 0x77, 0x65, 0x6c, 0x6c, 0x2d,
- 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x2f, 0x76, 0x65,
- 0x72, 0x61, 0x69, 0x73, 0x6f, 0x6e, 0x2f, 0x76,
- 0x65, 0x72, 0x69, 0x66, 0x69, 0x63, 0x61, 0x74,
- 0x69, 0x6f, 0x6e, 0x19, 0x09, 0x5f, 0x8d, 0xa4,
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- 0x0a, 0x96, 0x7d, 0xf8, 0xcc, 0x20, 0x8c, 0xdc,
- 0x7c, 0xd4, 0x54, 0x17, 0x4f, 0x06, 0x67, 0x73,
- 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01,
- 0x6d, 0x53, 0x4f, 0x43, 0x5f, 0x46, 0x57, 0x5f,
+ 0x5f, 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20, 0xf1,
+ 0x4b, 0x49, 0x87, 0x90, 0x4b, 0xcb, 0x58, 0x14,
+ 0xe4, 0x45, 0x9a, 0x05, 0x7e, 0xd4, 0xd2, 0x0f,
+ 0x58, 0xa6, 0x33, 0x15, 0x22, 0x88, 0xa7, 0x61,
+ 0x21, 0x4d, 0xcd, 0x28, 0x78, 0x0b, 0x56, 0x02,
+ 0x58, 0x20, 0xaa, 0x67, 0xa1, 0x69, 0xb0, 0xbb,
+ 0xa2, 0x17, 0xaa, 0x0a, 0xa8, 0x8a, 0x65, 0x34,
+ 0x69, 0x20, 0xc8, 0x4c, 0x42, 0x44, 0x7c, 0x36,
+ 0xba, 0x5f, 0x7e, 0xa6, 0x5f, 0x42, 0x2c, 0x1f,
+ 0xe5, 0xd8, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d,
+ 0x32, 0x35, 0x36, 0xa4, 0x01, 0x67, 0x41, 0x50,
+ 0x5f, 0x42, 0x4c, 0x33, 0x31, 0x05, 0x58, 0x20,
+ 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3,
+ 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56,
+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0x2e, 0x6d, 0x31, 0xa5, 0x98,
+ 0x3a, 0x91, 0x25, 0x1b, 0xfa, 0xe5, 0xae, 0xfa,
+ 0x1c, 0x0a, 0x19, 0xd8, 0xba, 0x3c, 0xf6, 0x01,
+ 0xd0, 0xe8, 0xa7, 0x06, 0xb4, 0xcf, 0xa9, 0x66,
+ 0x1a, 0x6b, 0x8a, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x63, 0x52,
+ 0x4d, 0x4d, 0x05, 0x58, 0x20, 0x53, 0x78, 0x79,
+ 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b,
+ 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c,
+ 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0,
+ 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20,
+ 0xa1, 0xfb, 0x50, 0xe6, 0xc8, 0x6f, 0xae, 0x16,
+ 0x79, 0xef, 0x33, 0x51, 0x29, 0x6f, 0xd6, 0x71,
+ 0x34, 0x11, 0xa0, 0x8c, 0xf8, 0xdd, 0x17, 0x90,
+ 0xa4, 0xfd, 0x05, 0xfa, 0xe8, 0x68, 0x81, 0x64,
+ 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35,
+ 0x36, 0xa4, 0x01, 0x69, 0x48, 0x57, 0x5f, 0x43,
+ 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58, 0x20,
+ 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3,
+ 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56,
+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0x1a, 0x25, 0x24, 0x02, 0x97,
+ 0x2f, 0x60, 0x57, 0xfa, 0x53, 0xcc, 0x17, 0x2b,
+ 0x52, 0xb9, 0xff, 0xca, 0x69, 0x8e, 0x18, 0x31,
+ 0x1f, 0xac, 0xd0, 0xf3, 0xb0, 0x6e, 0xca, 0xae,
+ 0xf7, 0x9e, 0x17, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x69, 0x46,
+ 0x57, 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47,
+ 0x05, 0x58, 0x20, 0x53, 0x78, 0x79, 0x63, 0x07,
+ 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2,
+ 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30,
+ 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97,
+ 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x9a, 0x92,
+ 0xad, 0xbc, 0x0c, 0xee, 0x38, 0xef, 0x65, 0x8c,
+ 0x71, 0xce, 0x1b, 0x1b, 0xf8, 0xc6, 0x56, 0x68,
+ 0xf1, 0x66, 0xbf, 0xb2, 0x13, 0x64, 0x4c, 0x89,
+ 0x5c, 0xcb, 0x1a, 0xd0, 0x7a, 0x25, 0x06, 0x67,
+ 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4,
+ 0x01, 0x6c, 0x54, 0x42, 0x5f, 0x46, 0x57, 0x5f,
0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58,
0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
- 0xa3, 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d,
- 0x26, 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3,
- 0x39, 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85,
- 0x29, 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc,
- 0xe0, 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68,
- 0x61, 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x21,
- 0x51, 0x20, 0x92, 0xd6, 0xd0, 0x2a, 0xe6, 0xbe,
- 0x2f, 0xe3, 0x93, 0x0e, 0xa5, 0x1f, 0xd6, 0x98,
- 0x96, 0x32, 0x24, 0x56, 0xe9, 0xdf, 0xc7, 0x32,
- 0x5e, 0x0b, 0x78, 0x68, 0xb6, 0x90, 0x73, 0x2a,
- 0x0c, 0x0f, 0x07, 0x77, 0xc1, 0x15, 0x40, 0x4b,
- 0xe1, 0xfc, 0x83, 0x9b, 0x7d, 0x30, 0x4f, 0x4f,
- 0xe6, 0xfa, 0x46, 0xae, 0x12, 0xa3, 0x08, 0x3a,
- 0xcf, 0x24, 0x06, 0x67, 0x91, 0x06, 0xbf, 0xae,
- 0x50, 0x31, 0x79, 0xdd, 0x50, 0x33, 0x49, 0x12,
- 0xbf, 0xc6, 0xda, 0x33, 0x6d, 0xd6, 0x18, 0x25,
- 0x43, 0x54, 0x4d, 0xb5, 0x88, 0xd6, 0xae, 0x67,
- 0x35, 0x7a, 0xfd, 0xb0, 0x5f, 0x95, 0xb7
+ 0xa3, 0x02, 0x58, 0x20, 0x23, 0x89, 0x03, 0x18,
+ 0x0c, 0xc1, 0x04, 0xec, 0x2c, 0x5d, 0x8b, 0x3f,
+ 0x20, 0xc5, 0xbc, 0x61, 0xb3, 0x89, 0xec, 0x0a,
+ 0x96, 0x7d, 0xf8, 0xcc, 0x20, 0x8c, 0xdc, 0x7c,
+ 0xd4, 0x54, 0x17, 0x4f, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x6d,
+ 0x53, 0x4f, 0x43, 0x5f, 0x46, 0x57, 0x5f, 0x43,
+ 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58, 0x20,
+ 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3,
+ 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56,
+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d, 0x26,
+ 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3, 0x39,
+ 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85, 0x29,
+ 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc, 0xe0,
+ 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x31, 0xd0,
+ 0x4d, 0x52, 0xcc, 0xde, 0x95, 0x2c, 0x1e, 0x32,
+ 0xcb, 0xa1, 0x81, 0x88, 0x5a, 0x40, 0xb8, 0xcc,
+ 0x38, 0xe0, 0x52, 0x8c, 0x1e, 0x89, 0x58, 0x98,
+ 0x07, 0x64, 0x2a, 0xa5, 0xe3, 0xf2, 0xbc, 0x37,
+ 0xf9, 0x53, 0x74, 0x50, 0x6b, 0xff, 0x4d, 0x2e,
+ 0x4b, 0xe7, 0x06, 0x3c, 0x4d, 0x72, 0x41, 0x92,
+ 0x70, 0xc7, 0x22, 0xe8, 0xd4, 0xd9, 0x3e, 0xe8,
+ 0xb6, 0xc9, 0xfa, 0xce, 0x3b, 0x43, 0xc9, 0x76,
+ 0x1a, 0x49, 0x94, 0x1a, 0xb6, 0xf3, 0x8f, 0xfd,
+ 0xff, 0x49, 0x6a, 0xd4, 0x63, 0xb4, 0xcb, 0xfa,
+ 0x11, 0xd8, 0x3e, 0x23, 0xe3, 0x1f, 0x7f, 0x62,
+ 0x32, 0x9d, 0xe3, 0x0c, 0x1c, 0xc8
};
/*
@@ -211,18 +212,21 @@
* RSE.
*/
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
- uintptr_t hash, size_t hash_size)
+ uintptr_t hash, size_t hash_size,
+ size_t *remaining_len)
{
+ const size_t token_size = sizeof(sample_platform_token);
(void)hash;
(void)hash_size;
- if (*len < sizeof(sample_platform_token)) {
+ /* Shouldn't happen because RMM uses the whole 4kB shared buffer */
+ if (*len < token_size) {
return -EINVAL;
}
- (void)memcpy((void *)buf, (const void *)sample_platform_token,
- sizeof(sample_platform_token));
- *len = sizeof(sample_platform_token);
+ memcpy((void *)buf, sample_platform_token, token_size);
+ *len = token_size;
+ *remaining_len = 0;
return 0;
}
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 6ed09d9..1aecece 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -76,14 +76,28 @@
#define DEFAULT_UUID_NUMBER U(7)
+#ifdef __aarch64__
+#define BL31_UUID_NUMBER U(1)
+#else
+#define BL31_UUID_NUMBER U(0)
+#endif
+
#if TRUSTED_BOARD_BOOT
#define TBBR_UUID_NUMBER U(6)
#else
#define TBBR_UUID_NUMBER U(0)
#endif
+#if STM32MP_DDR_FIP_IO_STORAGE
+#define DDR_FW_UUID_NUMBER U(1)
+#else
+#define DDR_FW_UUID_NUMBER U(0)
+#endif
+
#define FCONF_ST_IO_UUID_NUMBER (DEFAULT_UUID_NUMBER + \
- TBBR_UUID_NUMBER)
+ BL31_UUID_NUMBER + \
+ TBBR_UUID_NUMBER + \
+ DDR_FW_UUID_NUMBER)
static io_uuid_spec_t fconf_stm32mp_uuids[FCONF_ST_IO_UUID_NUMBER];
static OBJECT_POOL_ARRAY(fconf_stm32mp_uuids_pool, fconf_stm32mp_uuids);
@@ -95,7 +109,13 @@
/* image id to property name table */
static const struct policies_load_info load_info[FCONF_ST_IO_UUID_NUMBER] = {
+#if STM32MP_DDR_FIP_IO_STORAGE
+ {DDR_FW_ID, "ddr_fw_uuid"},
+#endif
{FW_CONFIG_ID, "fw_cfg_uuid"},
+#ifdef __aarch64__
+ {BL31_IMAGE_ID, "bl31_uuid"},
+#endif
{BL32_IMAGE_ID, "bl32_uuid"},
{BL32_EXTRA1_IMAGE_ID, "bl32_extra1_uuid"},
{BL32_EXTRA2_IMAGE_ID, "bl32_extra2_uuid"},
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index edada72..50d19ab 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -6,6 +6,7 @@
#include <assert.h>
#include <cdefs.h>
+#include <errno.h>
#include <stdint.h>
#include <common/debug.h>
@@ -14,6 +15,7 @@
#include <drivers/mmc.h>
#include <drivers/st/regulator_fixed.h>
#include <drivers/st/stm32mp2_ddr_helpers.h>
+#include <drivers/st/stm32mp_risab_regs.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <lib/mmio.h>
@@ -195,6 +197,17 @@
panic();
}
+#if STM32MP_DDR_FIP_IO_STORAGE
+ /*
+ * RISAB3 setup (dedicated for SRAM1)
+ *
+ * Allow secure read/writes data accesses to non-secure
+ * blocks or pages, all RISAB registers are writable.
+ * DDR firmwares are saved there before being loaded in DDRPHY memory.
+ */
+ mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD);
+#endif
+
stm32_save_boot_info(boot_context);
if (stm32mp_uart_console_setup() != 0) {
@@ -229,7 +242,12 @@
int bl2_plat_handle_post_image_load(unsigned int image_id)
{
int err = 0;
- bl_mem_params_node_t *bl_mem_params __maybe_unused = get_bl_mem_params_node(image_id);
+ bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+ const struct dyn_cfg_dtb_info_t *config_info;
+ unsigned int i;
+ const unsigned int image_ids[] = {
+ BL31_IMAGE_ID,
+ };
assert(bl_mem_params != NULL);
@@ -253,6 +271,30 @@
FW_CONFIG_ID);
fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
+ /* Iterate through all the fw config IDs */
+ for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
+ bl_mem_params = get_bl_mem_params_node(image_ids[i]);
+ assert(bl_mem_params != NULL);
+
+ config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
+ if (config_info == NULL) {
+ continue;
+ }
+
+ bl_mem_params->image_info.image_base = config_info->config_addr;
+ bl_mem_params->image_info.image_max_size = config_info->config_max_size;
+
+ bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
+
+ switch (image_ids[i]) {
+ case BL31_IMAGE_ID:
+ bl_mem_params->ep_info.pc = config_info->config_addr;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
/*
* After this step, the BL2 device tree area will be overwritten
* with BL31 binary, no other data should be read from BL2 DT.
diff --git a/plat/st/stm32mp2/bl31_plat_setup.c b/plat/st/stm32mp2/bl31_plat_setup.c
new file mode 100644
index 0000000..dbf1371
--- /dev/null
+++ b/plat/st/stm32mp2/bl31_plat_setup.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <common/bl_common.h>
+#include <drivers/st/stm32_console.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ bl_params_t *params_from_bl2;
+ int ret;
+
+ /*
+ * Invalidate remaining data from second half of SYSRAM (used by BL2) as this area will
+ * be later used as non-secure.
+ */
+ inv_dcache_range(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
+ STM32MP_SYSRAM_SIZE / 2U);
+
+ mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
+ BL_CODE_END - BL_CODE_BASE,
+ MT_CODE | MT_SECURE);
+
+#if USE_COHERENT_MEM
+ /* Map coherent memory */
+ mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+ MT_DEVICE | MT_RW | MT_SECURE);
+#endif
+
+ configure_mmu();
+
+ /*
+ * Map upper SYSRAM where bl_params_t are stored in BL2
+ */
+ ret = mmap_add_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
+ STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
+ STM32MP_SYSRAM_SIZE / 2U, MT_RO_DATA | MT_SECURE);
+ if (ret < 0) {
+ ERROR("BL2 params area mapping: %d\n", ret);
+ panic();
+ }
+
+ assert(arg0 != 0UL);
+ params_from_bl2 = (bl_params_t *)arg0;
+ assert(params_from_bl2 != NULL);
+ assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
+ assert(params_from_bl2->h.version >= VERSION_2);
+
+ bl_params_node_t *bl_params = params_from_bl2->head;
+
+ while (bl_params != NULL) {
+ bl_params = bl_params->next_params_info;
+ }
+
+ ret = mmap_remove_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
+ STM32MP_SYSRAM_SIZE / 2U);
+ if (ret < 0) {
+ ERROR("BL2 params area unmapping: %d\n", ret);
+ panic();
+ }
+}
+
+void bl31_plat_arch_setup(void)
+{
+}
+
+void bl31_platform_setup(void)
+{
+}
+
+entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
+{
+ return NULL;
+}
diff --git a/plat/st/stm32mp2/include/plat_tbbr_img_def.h b/plat/st/stm32mp2/include/plat_tbbr_img_def.h
index 5dfd41f..830bf88 100644
--- a/plat/st/stm32mp2/include/plat_tbbr_img_def.h
+++ b/plat/st/stm32mp2/include/plat_tbbr_img_def.h
@@ -40,8 +40,16 @@
#define STM32MP_CONFIG_CERT_ID U(24)
#define GPT_IMAGE_ID U(25)
+#if STM32MP_DDR_FIP_IO_STORAGE
+#define DDR_FW_ID U(26)
+/* Increase the MAX_NUMBER_IDS to match the authentication pool required */
+#define MAX_NUMBER_IDS U(27)
+
+#else
/* Increase the MAX_NUMBER_IDS to match the authentication pool required */
#define MAX_NUMBER_IDS U(26)
+#endif
+
#endif /* PLAT_TBBR_IMG_DEF_H */
diff --git a/plat/st/stm32mp2/include/platform_def.h b/plat/st/stm32mp2/include/platform_def.h
index 0f22a93..89ca032 100644
--- a/plat/st/stm32mp2/include/platform_def.h
+++ b/plat/st/stm32mp2/include/platform_def.h
@@ -8,6 +8,7 @@
#define PLATFORM_DEF_H
#include <arch.h>
+#include <drivers/arm/gic_common.h>
#include <lib/utils_def.h>
#include <plat/common/common_def.h>
@@ -32,9 +33,9 @@
#define PLATFORM_CORE_COUNT U(2)
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
-#define PLAT_MAX_PWR_LVL U(5)
-#define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5)
-#define PLAT_NUM_PWR_DOMAINS U(7)
+#define PLAT_MAX_PWR_LVL U(3)
+#define PLAT_MIN_SUSPEND_PWR_LVL U(2)
+#define PLAT_NUM_PWR_DOMAINS U(6)
/* Local power state for power domains in Run state. */
#define STM32MP_LOCAL_STATE_RUN U(0)
@@ -98,4 +99,59 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
+/*
+ * Secure Interrupt: based on the standard ARM mapping
+ */
+#define ARM_IRQ_SEC_PHY_TIMER U(29)
+
+#define ARM_IRQ_NON_SEC_SGI_0 U(0)
+
+#define ARM_IRQ_SEC_SGI_0 U(8)
+#define ARM_IRQ_SEC_SGI_1 U(9)
+#define ARM_IRQ_SEC_SGI_2 U(10)
+#define ARM_IRQ_SEC_SGI_3 U(11)
+#define ARM_IRQ_SEC_SGI_4 U(12)
+#define ARM_IRQ_SEC_SGI_5 U(13)
+#define ARM_IRQ_SEC_SGI_6 U(14)
+#define ARM_IRQ_SEC_SGI_7 U(15)
+
+/* Platform IRQ Priority */
+#define STM32MP_IRQ_SEC_SPI_PRIO U(0x10)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLATFORM_G1S_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+#define PLATFORM_G0_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
index 0ef522e..f845560 100644
--- a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
+++ b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
@@ -19,6 +19,24 @@
* the next executable image id.
******************************************************************************/
static bl_mem_params_node_t bl2_mem_params_descs[] = {
+#if STM32MP_DDR_FIP_IO_STORAGE
+ /* Fill FW_DDR related information if it exists */
+ {
+ .image_id = DDR_FW_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t,
+ 0),
+
+ .image_info.image_base = STM32MP_DDR_FW_BASE,
+ .image_info.image_max_size = STM32MP_DDR_FW_MAX_SIZE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+#endif
+
/* Fill FW_CONFIG related information if it exists */
{
.image_id = FW_CONFIG_ID,
@@ -34,6 +52,23 @@
.next_handoff_image_id = INVALID_IMAGE_ID,
},
+
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index eacbd96..32d6235 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -27,6 +27,23 @@
# Set load address for serial boot devices
DWL_BUFFER_BASE ?= 0x87000000
+# DDR types
+STM32MP_DDR3_TYPE ?= 0
+STM32MP_DDR4_TYPE ?= 0
+STM32MP_LPDDR4_TYPE ?= 0
+ifeq (${STM32MP_DDR3_TYPE},1)
+DDR_TYPE := ddr3
+endif
+ifeq (${STM32MP_DDR4_TYPE},1)
+DDR_TYPE := ddr4
+endif
+ifeq (${STM32MP_LPDDR4_TYPE},1)
+DDR_TYPE := lpddr4
+endif
+
+# DDR features
+STM32MP_DDR_FIP_IO_STORAGE := 1
+
# Device tree
BL2_DTSI := stm32mp25-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
@@ -38,13 +55,26 @@
STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
+ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
+STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
+STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin
+STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME}
+endif
FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
+ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
+# Add the FW_DDR to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
+endif
# Enable flags for C files
$(eval $(call assert_booleans,\
$(sort \
+ STM32MP_DDR_FIP_IO_STORAGE \
+ STM32MP_DDR3_TYPE \
+ STM32MP_DDR4_TYPE \
+ STM32MP_LPDDR4_TYPE \
STM32MP25 \
)))
@@ -58,9 +88,14 @@
$(eval $(call add_defines,\
$(sort \
DWL_BUFFER_BASE \
+ PLAT_DEF_FIP_UUID \
PLAT_PARTITION_MAX_ENTRIES \
PLAT_TBBR_IMG_DEF \
STM32_TF_A_COPIES \
+ STM32MP_DDR_FIP_IO_STORAGE \
+ STM32MP_DDR3_TYPE \
+ STM32MP_DDR4_TYPE \
+ STM32MP_LPDDR4_TYPE \
STM32MP25 \
)))
@@ -98,5 +133,35 @@
BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c
+# BL31 sources
+BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
+
+BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \
+ plat/st/stm32mp2/stm32mp2_pm.c \
+ plat/st/stm32mp2/stm32mp2_topology.c
+# Generic GIC v2
+include drivers/arm/gic/v2/gicv2.mk
+
+BL31_SOURCES += ${GICV2_SOURCES} \
+ plat/common/plat_gicv2.c \
+ plat/st/common/stm32mp_gic.c
+
+# Generic PSCI
+BL31_SOURCES += plat/common/plat_psci_common.c
+
# Compilation rules
+.PHONY: check_ddr_type
+.SUFFIXES:
+
+bl2: check_ddr_type
+
+check_ddr_type:
+ $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \
+ $(STM32MP_DDR4_TYPE) + \
+ $(STM32MP_LPDDR4_TYPE)))))
+ @if [ ${DDR_TYPE} != 1 ]; then \
+ echo "One and only one DDR type must be defined"; \
+ false; \
+ fi
+
include plat/st/common/common_rules.mk
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 81fdaae..d3290c3 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -71,6 +71,9 @@
******************************************************************************/
#define STM32MP_SYSRAM_BASE U(0x0E000000)
#define STM32MP_SYSRAM_SIZE U(0x00040000)
+#define SRAM1_BASE U(0x0E040000)
+#define SRAM1_SIZE_FOR_TFA U(0x00010000)
+#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
/* DDR configuration */
#define STM32MP_DDR_BASE U(0x80000000)
@@ -106,6 +109,10 @@
#define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
#define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
+/* Allocate remaining sysram to BL31 */
+#define STM32MP_BL31_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
+ STM32MP_BL2_SIZE)
+
#define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
@@ -139,6 +146,11 @@
#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
#endif
+#if STM32MP_DDR_FIP_IO_STORAGE
+#define STM32MP_DDR_FW_BASE SRAM1_BASE
+#define STM32MP_DDR_FW_MAX_SIZE U(0x8800)
+#endif
+
#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE
#define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE
@@ -359,6 +371,11 @@
#define SYSCFG_BASE U(0x44230000)
/*******************************************************************************
+ * STM32MP RIF
+ ******************************************************************************/
+#define RISAB3_BASE U(0x42110000)
+
+/*******************************************************************************
* STM32MP CA35SSC
******************************************************************************/
#define A35SSC_BASE U(0x48800000)
diff --git a/plat/st/stm32mp2/stm32mp2_pm.c b/plat/st/stm32mp2/stm32mp2_pm.c
new file mode 100644
index 0000000..5bb381d
--- /dev/null
+++ b/plat/st/stm32mp2/stm32mp2_pm.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/st/stm32mp_reset.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+static uintptr_t stm32_sec_entrypoint;
+
+static void stm32_cpu_standby(plat_local_state_t cpu_state)
+{
+}
+
+static int stm32_pwr_domain_on(u_register_t mpidr)
+{
+ return PSCI_E_INTERN_FAIL;
+}
+
+static void stm32_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ /* Nothing to do */
+}
+
+static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state)
+{
+ /* Nothing to do, power domain is not disabled */
+}
+
+static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+}
+
+/*******************************************************************************
+ * STM32MP2 handler called when a power domain has just been powered on after
+ * having been suspended earlier. The target_state encodes the low power state
+ * that each level has woken up from.
+ ******************************************************************************/
+static void stm32_pwr_domain_suspend_finish(const psci_power_state_t
+ *target_state)
+{
+ /* Nothing to do, power domain is not disabled */
+}
+
+static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t
+ *target_state)
+{
+ ERROR("stm32mp2 Power Down WFI: operation not handled.\n");
+ panic();
+}
+
+static void __dead2 stm32_system_off(void)
+{
+ ERROR("stm32mp2 System Off: operation not handled.\n");
+ panic();
+}
+
+static void __dead2 stm32_system_reset(void)
+{
+ stm32mp_system_reset();
+}
+
+static int stm32_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ return PSCI_E_INVALID_PARAMS;
+}
+
+static int stm32_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ /* The non-secure entry point must be in DDR */
+ if (entrypoint < STM32MP_DDR_BASE) {
+ return PSCI_E_INVALID_ADDRESS;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+static void stm32_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+}
+
+/*******************************************************************************
+ * Export the platform handlers. The ARM Standard platform layer will take care
+ * of registering the handlers with PSCI.
+ ******************************************************************************/
+static const plat_psci_ops_t stm32_psci_ops = {
+ .cpu_standby = stm32_cpu_standby,
+ .pwr_domain_on = stm32_pwr_domain_on,
+ .pwr_domain_off = stm32_pwr_domain_off,
+ .pwr_domain_suspend = stm32_pwr_domain_suspend,
+ .pwr_domain_on_finish = stm32_pwr_domain_on_finish,
+ .pwr_domain_suspend_finish = stm32_pwr_domain_suspend_finish,
+ .pwr_domain_pwr_down_wfi = stm32_pwr_domain_pwr_down_wfi,
+ .system_off = stm32_system_off,
+ .system_reset = stm32_system_reset,
+ .validate_power_state = stm32_validate_power_state,
+ .validate_ns_entrypoint = stm32_validate_ns_entrypoint,
+ .get_sys_suspend_power_state = stm32_get_sys_suspend_power_state,
+};
+
+/*******************************************************************************
+ * Export the platform specific power ops.
+ ******************************************************************************/
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ stm32_sec_entrypoint = sec_entrypoint;
+ *psci_ops = &stm32_psci_ops;
+
+ return 0;
+}
diff --git a/plat/st/stm32mp2/stm32mp2_private.c b/plat/st/stm32mp2/stm32mp2_private.c
index 2801a7f..99f6be2 100644
--- a/plat/st/stm32mp2/stm32mp2_private.c
+++ b/plat/st/stm32mp2/stm32mp2_private.c
@@ -12,12 +12,31 @@
#define BKPR_BOOT_MODE 96U
+#if defined(IMAGE_BL31)
+/* BL31 only uses the first half of the SYSRAM */
+#define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
+ STM32MP_SYSRAM_SIZE / 2U, \
+ MT_MEMORY | \
+ MT_RW | \
+ MT_SECURE | \
+ MT_EXECUTE_NEVER)
+#else
#define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
STM32MP_SYSRAM_SIZE, \
MT_MEMORY | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
+#endif
+
+#if STM32MP_DDR_FIP_IO_STORAGE
+#define MAP_SRAM1 MAP_REGION_FLAT(SRAM1_BASE, \
+ SRAM1_SIZE_FOR_TFA, \
+ MT_MEMORY | \
+ MT_RW | \
+ MT_SECURE | \
+ MT_EXECUTE_NEVER)
+#endif
#define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \
STM32MP_DEVICE_SIZE, \
@@ -29,6 +48,16 @@
#if defined(IMAGE_BL2)
static const mmap_region_t stm32mp2_mmap[] = {
MAP_SYSRAM,
+#if STM32MP_DDR_FIP_IO_STORAGE
+ MAP_SRAM1,
+#endif
+ MAP_DEVICE,
+ {0}
+};
+#endif
+#if defined(IMAGE_BL31)
+static const mmap_region_t stm32mp2_mmap[] = {
+ MAP_SYSRAM,
MAP_DEVICE,
{0}
};
diff --git a/plat/st/stm32mp2/stm32mp2_topology.c b/plat/st/stm32mp2/stm32mp2_topology.c
new file mode 100644
index 0000000..cc2d58c
--- /dev/null
+++ b/plat/st/stm32mp2/stm32mp2_topology.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+/* 1 cluster, all cores into */
+static const unsigned char stm32mp2_power_domain_tree_desc[] = {
+ PLATFORM_CLUSTER_COUNT,
+ PLATFORM_CORE_COUNT,
+};
+
+/* This function returns the platform topology */
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return stm32mp2_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+ u_register_t mpidr_copy = mpidr;
+
+ mpidr_copy &= MPIDR_AFFINITY_MASK;
+
+ if ((mpidr_copy & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0U) {
+ return -1;
+ }
+
+ cluster_id = (mpidr_copy >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+ if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
+ return -1;
+ }
+
+ /*
+ * Validate cpu_id by checking whether it represents a CPU in one
+ * of the two clusters present on the platform.
+ */
+ if (cpu_id >= PLATFORM_CORE_COUNT) {
+ return -1;
+ }
+
+ return (int)cpu_id;
+}
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index ebcc31b..4ad7b2d 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -86,6 +86,18 @@
}
#endif
+#if defined(XILINX_OF_BOARD_DTB_ADDR)
+static int check_fdt_reserved_memory(void *dtb, const char *node_name)
+{
+ int offset = fdt_path_offset(dtb, "/reserved-memory");
+
+ if (offset >= 0) {
+ offset = fdt_subnode_offset(dtb, offset, node_name);
+ }
+ return offset;
+}
+#endif
+
void prepare_dtb(void)
{
#if defined(XILINX_OF_BOARD_DTB_ADDR)
@@ -112,12 +124,19 @@
WARN("Failed to add PSCI cpu enable methods in DT\n");
}
- /* Reserve memory used by Trusted Firmware. */
- ret = fdt_add_reserved_memory(dtb, "tf-a",
- BL31_BASE,
- BL31_LIMIT - BL31_BASE);
+ /* Check reserved memory set in DT*/
+ ret = check_fdt_reserved_memory(dtb, "tf-a");
if (ret < 0) {
- WARN("Failed to add reserved memory nodes for BL31 to DT.\n");
+ /* Reserve memory used by Trusted Firmware. */
+ ret = fdt_add_reserved_memory(dtb, "tf-a",
+ BL31_BASE,
+ BL31_LIMIT - BL31_BASE);
+ if (ret < 0) {
+ WARN("Failed to add reserved memory nodes for BL31 to DT.\n");
+ }
+
+ } else {
+ WARN("Reserved memory pre-exists in DT.\n");
}
ret = fdt_pack(dtb);
diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c
index 9e8134a..4236d8a 100644
--- a/plat/xilinx/versal/aarch64/versal_common.c
+++ b/plat/xilinx/versal/aarch64/versal_common.c
@@ -58,6 +58,10 @@
platform_id = FIELD_GET(PLATFORM_MASK, plat_info[1]);
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, plat_info[1]);
+
+ if (platform_id == VERSAL_COSIM) {
+ platform_id = VERSAL_QEMU;
+ }
}
const char *board_name_decode(void)
@@ -96,8 +100,6 @@
uart_clock = 212000;
break;
case VERSAL_QEMU:
- uart_clock = 25000000;
- break;
case VERSAL_SILICON:
uart_clock = 100000000;
break;
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 0e4ec1c..57377a9 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -93,9 +93,6 @@
cpu_clock = 212000;
break;
case VERSAL_QEMU:
- /* Random values now */
- cpu_clock = 2720000;
- break;
case VERSAL_SILICON:
cpu_clock = 100000000;
break;
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index b7691ad..c50df7e 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -30,6 +30,7 @@
#define VERSAL_SPP U(1)
#define VERSAL_EMU U(2)
#define VERSAL_QEMU U(3)
+#define VERSAL_COSIM U(7)
/* Firmware Image Package */
#define VERSAL_PRIMARY_CPU 0
diff --git a/services/std_svc/rmmd/rmmd_attest.c b/services/std_svc/rmmd/rmmd_attest.c
index 25adf50..f73236c 100644
--- a/services/std_svc/rmmd/rmmd_attest.c
+++ b/services/std_svc/rmmd/rmmd_attest.c
@@ -1,8 +1,9 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <stdint.h>
#include <string.h>
@@ -85,7 +86,8 @@
}
int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_size,
- uint64_t c_size)
+ uint64_t c_size,
+ uint64_t *remaining_len)
{
int err;
uint8_t temp_buf[SHA512_DIGEST_SIZE];
@@ -110,9 +112,19 @@
/* Get the platform token. */
err = plat_rmmd_get_cca_attest_token((uintptr_t)buf_pa,
- buf_size, (uintptr_t)temp_buf, c_size);
+ buf_size, (uintptr_t)temp_buf, c_size, remaining_len);
- if (err != 0) {
+ switch (err) {
+ case 0:
+ err = E_RMM_OK;
+ break;
+ case -EAGAIN:
+ err = E_RMM_AGAIN;
+ break;
+ case -EINVAL:
+ err = E_RMM_INVAL;
+ break;
+ default:
ERROR("Failed to get platform token: %d.\n", err);
err = E_RMM_UNK;
}
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 15b3724..153bb01 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -448,6 +448,7 @@
uint64_t x3, uint64_t x4, void *cookie,
void *handle, uint64_t flags)
{
+ uint64_t remaining_len = 0;
uint32_t src_sec_state;
int ret;
@@ -473,8 +474,8 @@
ret = gpt_undelegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM);
SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1));
case RMM_ATTEST_GET_PLAT_TOKEN:
- ret = rmmd_attest_get_platform_token(x1, &x2, x3);
- SMC_RET2(handle, ret, x2);
+ ret = rmmd_attest_get_platform_token(x1, &x2, x3, &remaining_len);
+ SMC_RET3(handle, ret, x2, remaining_len);
case RMM_ATTEST_GET_REALM_KEY:
ret = rmmd_attest_get_signing_key(x1, &x2, x3);
SMC_RET2(handle, ret, x2);
diff --git a/services/std_svc/rmmd/rmmd_private.h b/services/std_svc/rmmd/rmmd_private.h
index 4954a43..6d3b5ec 100644
--- a/services/std_svc/rmmd/rmmd_private.h
+++ b/services/std_svc/rmmd/rmmd_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,7 +47,8 @@
/* Functions implementing attestation utilities for RMM */
int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_size,
- uint64_t c_size);
+ uint64_t c_size,
+ uint64_t *remaining_len);
int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_size,
uint64_t ecc_curve);