feat(gicv5): assign interrupt sources to appropriate security states
Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux to fully boot.
This is expected to be fully replaced with context management when
adding world switching support as some of these are expected to be
shared between worlds.
Change-Id: I59a7b5a63f878c9a717ef81e977be7133a402f3f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 5f68b27..b607945 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -91,6 +91,17 @@
#define SERROR_EXCEPTION 0x180
/*******************************************************************************
+ * Encodings for GICv5 EL3 system registers
+ ******************************************************************************/
+#define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4
+#define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5
+#define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6
+#define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7
+
+#define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3)
+#define ICC_PPI_DOMAINR_COUNT (32)
+
+/*******************************************************************************
* Definitions for CPU system register interface to GICv3
******************************************************************************/
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index c885424..a59c531 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -559,6 +559,12 @@
DEFINE_SYSREG_RW_FUNCS(dacr32_el2)
DEFINE_SYSREG_RW_FUNCS(ifsr32_el2)
+/* GICv5 System Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr0_el3, ICC_PPI_DOMAINR0_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr1_el3, ICC_PPI_DOMAINR1_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr2_el3, ICC_PPI_DOMAINR2_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr3_el3, ICC_PPI_DOMAINR3_EL3)
+
/* GICv3 System Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
diff --git a/include/drivers/arm/gicv5.h b/include/drivers/arm/gicv5.h
index ff3c61c..caee11c 100644
--- a/include/drivers/arm/gicv5.h
+++ b/include/drivers/arm/gicv5.h
@@ -24,8 +24,34 @@
#define TM_EDGE 0
#define TM_LEVEL 1
+/* Architected PPI numbers */
+#define PPI_TRBIRQ 31
+#define PPI_CNTP 30
+#define PPI_CNTPS 29
+#define PPI_CNTHV 28
+#define PPI_CNTV 27
+#define PPI_CNTHP 26
+#define PPI_GICMNT 25
+#define PPI_CTIIRQ 24
+#define PPI_PMUIRQ 23
+#define PPI_COMMIRQ 22
+#define PPI_PMBIRQ 21
+#define PPI_CNTHPS 20
+#define PPI_CNTHVS 19
+#define PPI_DB_NS 2
+#define PPI_DB_RL 1
+#define PPI_DB_S 0
+
#ifndef __ASSEMBLER__
+#define _PPI_FIELD_SHIFT(_REG, _ppi_id) \
+ ((_ppi_id % (ICC_PPI_##_REG##_COUNT)) * (64 / ICC_PPI_##_REG##_COUNT))
+
+#define write_icc_ppi_domainr(_var, _ppi_id, _value) \
+ do { \
+ _var |= (uint64_t)_value << _PPI_FIELD_SHIFT(DOMAINR, _ppi_id);\
+ } while (false)
+
struct gicv5_driver_data {
};
@@ -34,5 +60,6 @@
void gicv5_driver_init();
uint8_t gicv5_get_pending_interrupt_type(void);
bool gicv5_has_interrupt_type(unsigned int type);
+void gicv5_enable_ppis();
#endif /* __ASSEMBLER__ */
#endif /* GICV5_H */