refactor(drivers/marvell/comphy-3700): unify Generation Settings register values
Generation Settings registers have the same layout for different
generations and same setting (i.e. Generation 2 Settings 2 register has
the same layout as Generation 3 Settings 2).
So it does not make sense to prefix the constants for Settings 2 with
G3.
Instead change the prefixes to GSx_ for settings register x.
For Settings 2 of Gen 2 and Gen 3 we have some definitions in the first
and some in the second. Move them all to the first defined register (in
this case Gen 2, since the constant for Gen 1 is not defined because it
is not used).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I15c337eb58aa37fd99fe388fd59373aa325a3a92
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index df4c4fd..6fba60b 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -98,28 +98,24 @@
#define COMPHY_GEN2_SET2 0x3e
#define GEN2_SET2_ADDR(unit) (COMPHY_GEN2_SET2 * PHY_SHFT(unit))
-#define G2_TX_SSC_AMP_VALUE_20 BIT(14)
-#define G2_TX_SSC_AMP_OFF 9
-#define G2_TX_SSC_AMP_LEN 7
-#define G2_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
- G2_TX_SSC_AMP_OFF)
+#define GS2_TX_SSC_AMP_VALUE_20 BIT(14)
+#define GS2_TX_SSC_AMP_OFF 9
+#define GS2_TX_SSC_AMP_LEN 7
+#define GS2_TX_SSC_AMP_MASK (((1 << GS2_TX_SSC_AMP_LEN) - 1) << \
+ GS2_TX_SSC_AMP_OFF)
+#define GS2_VREG_RXTX_MAS_ISET_OFF 7
+#define GS2_VREG_RXTX_MAS_ISET_60U (0 << GS2_VREG_RXTX_MAS_ISET_OFF)
+#define GS2_VREG_RXTX_MAS_ISET_80U (1 << GS2_VREG_RXTX_MAS_ISET_OFF)
+#define GS2_VREG_RXTX_MAS_ISET_100U (2 << GS2_VREG_RXTX_MAS_ISET_OFF)
+#define GS2_VREG_RXTX_MAS_ISET_120U (3 << GS2_VREG_RXTX_MAS_ISET_OFF)
+#define GS2_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
+#define GS2_RSVD_6_0_OFF 0
+#define GS2_RSVD_6_0_LEN 7
+#define GS2_RSVD_6_0_MASK (((1 << GS2_RSVD_6_0_LEN) - 1) << \
+ GS2_RSVD_6_0_OFF)
#define COMPHY_GEN3_SET2 0x3f
#define GEN3_SET2_ADDR(unit) (COMPHY_GEN3_SET2 * PHY_SHFT(unit))
-#define G3_TX_SSC_AMP_OFF 9
-#define G3_TX_SSC_AMP_LEN 7
-#define G3_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
- G2_TX_SSC_AMP_OFF)
-#define G3_VREG_RXTX_MAS_ISET_OFF 7
-#define G3_VREG_RXTX_MAS_ISET_60U (0 << G3_VREG_RXTX_MAS_ISET_OFF)
-#define G3_VREG_RXTX_MAS_ISET_80U (1 << G3_VREG_RXTX_MAS_ISET_OFF)
-#define G3_VREG_RXTX_MAS_ISET_100U (2 << G3_VREG_RXTX_MAS_ISET_OFF)
-#define G3_VREG_RXTX_MAS_ISET_120U (3 << G3_VREG_RXTX_MAS_ISET_OFF)
-#define G3_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
-#define RSVD_PH03FH_6_0_OFF 0
-#define RSVD_PH03FH_6_0_LEN 7
-#define RSVD_PH03FH_6_0_MASK (((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
- RSVD_PH03FH_6_0_OFF)
#define COMPHY_UNIT_CTRL 0x48
#define UNIT_CTRL_ADDR(unit) (COMPHY_UNIT_CTRL * PHY_SHFT(unit))
@@ -139,8 +135,8 @@
#define SEL_BITS_PCIE_FORCE BIT(15)
#define COMPHY_GEN2_SET3 0x112
-#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF
-#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF
+#define GS3_FFE_CAP_SEL_MASK 0xF
+#define GS3_FFE_CAP_SEL_VALUE 0xF
#define COMPHY_LANE_CFG0 0x180
#define LANE_CFG0_ADDR(unit) (COMPHY_LANE_CFG0 * PHY_SHFT(unit))