diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 2d91cb2..5555f5d 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -159,69 +159,7 @@
  */
 void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
 {
-	uint32_t index;
-	uint32_t total_128kb_blocks = size_in_bytes >> 17;
-	uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
-	uint32_t val;
-
-	INFO("Configuring TrustZone SRAM Memory Carveout\n");
-
-	/*
-	 * Reset the access configuration registers to restrict access
-	 * to the TZRAM aperture
-	 */
-	for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0;
-	     index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
-	     index += 4U) {
-		tegra_mc_write_32(index, 0);
-	}
-
-	/*
-	 * Enable CPU access configuration registers to access the TZRAM aperture
-	 */
-	if (!tegra_chipid_is_t186()) {
-		val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0);
-		val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW;
-		tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val);
-	}
-
-	/*
-	 * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
-	 */
-	assert((phys_base & (uint64_t)0xFFF) == 0U);
-	tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
-	tegra_mc_write_32(MC_TZRAM_BASE_HI,
-		(uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
-
-	/*
-	 * Set the TZRAM size
-	 *
-	 * total size = (number of 128KB blocks) + (number of remaining 4KB
-	 * blocks)
-	 *
-	 */
-	val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
-	      total_128kb_blocks;
-	tegra_mc_write_32(MC_TZRAM_SIZE, val);
-
-	/*
-	 * Lock the configuration settings by disabling TZ-only lock
-	 * and locking the configuration against any future changes
-	 * at all.
-	 */
-	val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
-	val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
-	val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
-	if (!tegra_chipid_is_t186()) {
-		val |= MC_GSC_ENABLE_CPU_SECURE_BIT;
-	}
-	tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
-
-	/*
-	 * MCE propagates the security configuration values across the
-	 * CCPLEX.
-	 */
-	mce_update_gsc_tzram();
+	; /* do nothing */
 }
 
 /*
diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h
index 4470b6b..5f1bb4f 100644
--- a/plat/nvidia/tegra/include/drivers/mce.h
+++ b/plat/nvidia/tegra/include/drivers/mce.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -69,7 +69,6 @@
 int mce_update_reset_vector(void);
 int mce_update_gsc_videomem(void);
 int mce_update_gsc_tzdram(void);
-int mce_update_gsc_tzram(void);
 __dead2 void mce_enter_ccplex_state(uint32_t state_idx);
 void mce_update_cstate_info(const mce_cstate_info_t *cstate);
 void mce_verify_firmware_version(void);
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index 9e42b2b..54d3b2c 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -386,14 +387,6 @@
 }
 
 /*******************************************************************************
- * Handler to update carveout values for TZ SysRAM aperture
- ******************************************************************************/
-int32_t mce_update_gsc_tzram(void)
-{
-	return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM);
-}
-
-/*******************************************************************************
  * Handler to shutdown/reset the entire system
  ******************************************************************************/
 __dead2 void mce_enter_ccplex_state(uint32_t state_idx)
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
index 00c671b..7edd7a0 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
@@ -116,25 +116,6 @@
 }
 
 /*******************************************************************************
- * Handler to update carveout values for TZ SysRAM aperture
- ******************************************************************************/
-int32_t mce_update_gsc_tzram(void)
-{
-	int32_t ret;
-
-	/*
-	 * MCE firmware is not running on simulation platforms.
-	 */
-	if (mce_firmware_not_supported()) {
-		ret = -EINVAL;
-	} else {
-		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
-	}
-
-	return ret;
-}
-
-/*******************************************************************************
  * Handler to issue the UPDATE_CSTATE_INFO request
  ******************************************************************************/
 void mce_update_cstate_info(const mce_cstate_info_t *cstate)