Tegra: memctrl_v2: remove support to secure TZSRAM
This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.
Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 2d91cb2..5555f5d 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -159,69 +159,7 @@
*/
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
{
- uint32_t index;
- uint32_t total_128kb_blocks = size_in_bytes >> 17;
- uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
- uint32_t val;
-
- INFO("Configuring TrustZone SRAM Memory Carveout\n");
-
- /*
- * Reset the access configuration registers to restrict access
- * to the TZRAM aperture
- */
- for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0;
- index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
- index += 4U) {
- tegra_mc_write_32(index, 0);
- }
-
- /*
- * Enable CPU access configuration registers to access the TZRAM aperture
- */
- if (!tegra_chipid_is_t186()) {
- val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0);
- val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW;
- tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val);
- }
-
- /*
- * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
- */
- assert((phys_base & (uint64_t)0xFFF) == 0U);
- tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
- tegra_mc_write_32(MC_TZRAM_BASE_HI,
- (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
-
- /*
- * Set the TZRAM size
- *
- * total size = (number of 128KB blocks) + (number of remaining 4KB
- * blocks)
- *
- */
- val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
- total_128kb_blocks;
- tegra_mc_write_32(MC_TZRAM_SIZE, val);
-
- /*
- * Lock the configuration settings by disabling TZ-only lock
- * and locking the configuration against any future changes
- * at all.
- */
- val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
- val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
- val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
- if (!tegra_chipid_is_t186()) {
- val |= MC_GSC_ENABLE_CPU_SECURE_BIT;
- }
- tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
-
- /*
- * MCE propagates the security configuration values across the
- * CCPLEX.
- */
- mce_update_gsc_tzram();
+ ; /* do nothing */
}
/*