Tegra: fix trivial misra issues
Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/drivers/pmc.h b/plat/nvidia/tegra/include/drivers/pmc.h
index c0616d0..a5ab8f1 100644
--- a/plat/nvidia/tegra/include/drivers/pmc.h
+++ b/plat/nvidia/tegra/include/drivers/pmc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -34,19 +34,19 @@
#include <mmio.h>
#include <tegra_def.h>
-#define PMC_CONFIG 0x0
-#define PMC_PWRGATE_STATUS 0x38
-#define PMC_PWRGATE_TOGGLE 0x30
-#define PMC_TOGGLE_START 0x100
-#define PMC_SCRATCH39 0x138
-#define PMC_SECURE_DISABLE2 0x2c4
-#define PMC_SECURE_DISABLE2_WRITE22_ON (1 << 28)
-#define PMC_SECURE_SCRATCH22 0x338
-#define PMC_SECURE_DISABLE3 0x2d8
-#define PMC_SECURE_DISABLE3_WRITE34_ON (1 << 20)
-#define PMC_SECURE_DISABLE3_WRITE35_ON (1 << 22)
-#define PMC_SECURE_SCRATCH34 0x368
-#define PMC_SECURE_SCRATCH35 0x36c
+#define PMC_CONFIG 0x0U
+#define PMC_PWRGATE_STATUS 0x38U
+#define PMC_PWRGATE_TOGGLE 0x30U
+#define PMC_TOGGLE_START 0x100U
+#define PMC_SCRATCH39 0x138U
+#define PMC_SECURE_DISABLE2 0x2c4U
+#define PMC_SECURE_DISABLE2_WRITE22_ON (1U << 28)
+#define PMC_SECURE_SCRATCH22 0x338U
+#define PMC_SECURE_DISABLE3 0x2d8U
+#define PMC_SECURE_DISABLE3_WRITE34_ON (1U << 20)
+#define PMC_SECURE_DISABLE3_WRITE35_ON (1U << 22)
+#define PMC_SECURE_SCRATCH34 0x368U
+#define PMC_SECURE_SCRATCH35 0x36cU
static inline uint32_t tegra_pmc_read_32(uint32_t off)
{