rockchip: support the suspend/resume for rk3399
This patch adds to support the suspend/resume for rk3399 SoCs.
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index f8d66c2..5b7613d 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -55,6 +55,9 @@
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(RK3399_UART2_BASE, RK3399_UART2_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(PMUGRF_BASE, PMUGRF_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+
{ 0 }
};
@@ -313,12 +316,13 @@
{
mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
CRU_PMU_SGRF_RST_RLS);
+
+ mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON,
+ CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK);
}
void __dead2 soc_global_soft_reset(void)
{
- uint32_t temp_val;
-
set_pll_slow_mode(VPLL_ID);
set_pll_slow_mode(NPLL_ID);
set_pll_slow_mode(GPLL_ID);
@@ -326,9 +330,9 @@
set_pll_slow_mode(PPLL_ID);
set_pll_slow_mode(ABPLL_ID);
set_pll_slow_mode(ALPLL_ID);
- temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) |
- PMU_RST_BY_FIRST_SFT;
- mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val);
+
+ dsb();
+
mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL);
/*
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.h b/plat/rockchip/rk3399/drivers/soc/soc.h
index 9100d02..e48f2f0 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.h
+++ b/plat/rockchip/rk3399/drivers/soc/soc.h
@@ -52,14 +52,16 @@
#define NO_PLL_BYPASS (0x00)
#define NO_PLL_PWRDN (0x00)
-#define PLL_SLOW_MODE BITS_WITH_WMASK(PLL_MODE_MSK,\
- SLOW_MODE, PLL_MODE_SHIFT)
-#define PLL_BYPASS_MODE BITS_WITH_WMASK(PLL_BYPASS_MSK,\
- PLL_BYPASS, PLL_BYPASS_SHIFT)
-#define PLL_NO_BYPASS_MODE BITS_WITH_WMASK(PLL_BYPASS_MSK,\
- NO_PLL_BYPASS, PLL_BYPASS_SHIFT)
-#define PLL_NOMAL_MODE BITS_WITH_WMASK(PLL_MODE_MSK,\
- NORMAL_MODE, PLL_MODE_SHIFT)
+#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
+ PLL_MODE_MSK, PLL_MODE_SHIFT)
+#define PLL_BYPASS_MODE BITS_WITH_WMASK(PLL_BYPASS,\
+ PLL_BYPASS_MSK,\
+ PLL_BYPASS_SHIFT)
+#define PLL_NO_BYPASS_MODE BITS_WITH_WMASK(NO_PLL_BYPASS,\
+ PLL_BYPASS_MSK,\
+ PLL_BYPASS_SHIFT)
+#define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\
+ PLL_MODE_MSK, PLL_MODE_SHIFT)
#define PLL_CON_COUNT 0x06
#define CRU_CLKSEL_COUNT 0x108
@@ -100,6 +102,9 @@
uint32_t cru_clksel_con[CRU_CLKSEL_COUNT];
};
+#define CYCL_24M_CNT_US(us) (24 * us)
+#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
+
/**************************************************
* secure timer
**************************************************/
@@ -155,6 +160,13 @@
#define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6)
/* reset hold release*/
#define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6)
+
+#define CRU_PMU_WDTRST_MSK (0x1 << 4)
+#define CRU_PMU_WDTRST_EN 0x0
+
+#define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2)
+#define CRU_PMU_FIRST_SFTRST_EN 0x0
+
/**************************************************
* sgrf reg, offset
**************************************************/