Merge pull request #1264 from fengbaopeng/integration
drivers:ufs: fix hynix ufs bug with quirk on hi36xx SoC
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 57c065c..60be932 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -390,12 +390,12 @@
* content). Either way, we aren't leaking any secure information
* through them.
*/
- mov w0, #SMC_UNK
+ mov x0, #SMC_UNK
b restore_gp_registers_callee_eret
smc_prohibited:
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
- mov w0, #SMC_UNK
+ mov x0, #SMC_UNK
eret
rt_svc_fw_critical_error:
diff --git a/bl31/ehf.c b/bl31/ehf.c
index 65f2df5..39ee635 100644
--- a/bl31/ehf.c
+++ b/bl31/ehf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -201,7 +201,7 @@
else
old_mask = plat_ic_set_priority_mask(priority);
- if (old_mask >= priority) {
+ if (old_mask > priority) {
ERROR("Deactivation priority (0x%x) lower than Priority Mask (0x%x)\n",
priority, old_mask);
panic();
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 8cf15b8..c9e8748 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -1582,6 +1582,7 @@
<path-to>/Foundation_Platform \
--cores=4 \
+ --arm-v8.0 \
--secure-memory \
--visualization \
--gicv3 \
@@ -1600,6 +1601,12 @@
and enable the GICv3 device in the model. Note that without this option,
the Foundation FVP defaults to legacy (Versatile Express) memory map which
is not supported by ARM Trusted Firmware.
+- In order for the Arm Trusted Firmware to run correctly on the Foundation
+ Model the architecture versions must match. The Foundation FVP defaults to
+ the highest v8.x version it supports but the default build for Arm Trusted
+ Firmware is for v8.0. To avoid issues either start the Foundation Model to
+ use v8.0 architecture using the ``--arm-v8.0`` option or build Arm Trusted
+ Firmware with an appropriate value for ``ARM_ARCH_MINOR``.
Running on the AEMv8 Base FVP with reset to BL1 entrypoint
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index b817487..34462a9 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -205,13 +205,16 @@
for (filter = 0; filter < tzc400.num_filters; filter++) {
state = _tzc400_get_gate_keeper(tzc400.base, filter);
if (state) {
- /* The TZC filter is already configured. Changing the
+ /*
+ * The TZC filter is already configured. Changing the
* programmer's view in an active system can cause
* unpredictable behavior therefore panic for now rather
* than try to determine whether this is safe in this
- * instance. See:
- * http://infocenter.arm.com/help/index.jsp?\
- * topic=/com.arm.doc.ddi0504c/CJHHECBF.html */
+ * instance.
+ *
+ * See the 'ARM (R) CoreLink TM TZC-400 TrustZone (R)
+ * Address Space Controller' Technical Reference Manual.
+ */
ERROR("TZC-400 : Filter %d Gatekeeper already"
" enabled.\n", filter);
panic();
diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h
index f092cf1..89156ed 100644
--- a/drivers/arm/tzc/tzc_common_private.h
+++ b/drivers/arm/tzc/tzc_common_private.h
@@ -169,8 +169,6 @@
nsaid_permissions); \
}
-#if ENABLE_ASSERTIONS
-
static inline unsigned int _tzc_read_peripheral_id(uintptr_t base)
{
unsigned int id;
@@ -182,6 +180,7 @@
return id;
}
+#if ENABLE_ASSERTIONS
#ifdef AARCH32
static inline unsigned long long _tzc_get_max_top_addr(int addr_width)
{
diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c
index abb3511..a23940d 100644
--- a/drivers/io/io_fip.c
+++ b/drivers/io/io_fip.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,10 +28,6 @@
x.node[4], x.node[5]
typedef struct {
- /* Put file_pos above the struct to allow {0} on static init.
- * It is a workaround for a known bug in GCC
- * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
- */
unsigned int file_pos;
fip_toc_entry_t entry;
} file_state_t;
diff --git a/include/lib/smcc.h b/include/lib/smcc.h
index a273b3a..0a2d927 100644
--- a/include/lib/smcc.h
+++ b/include/lib/smcc.h
@@ -35,13 +35,13 @@
#define SMC_64 U(1)
#define SMC_32 U(0)
#define SMC_OK U(0)
-#define SMC_UNK U(0xffffffff)
+#define SMC_UNK -1
#define SMC_TYPE_FAST ULL(1)
#if !ERROR_DEPRECATED
#define SMC_TYPE_STD ULL(0)
#endif
#define SMC_TYPE_YIELD U(0)
-#define SMC_PREEMPTED U(0xfffffffe)
+#define SMC_PREEMPTED -2
/*******************************************************************************
* Owning entity number definitions inside the function id as per the SMC
* calling convention
@@ -99,7 +99,7 @@
*/
#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \
_n0, _n1, _n2, _n3, _n4, _n5) \
- CASSERT(_tl != SMC_UNK, invalid_svc_uuid);\
+ CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
static const uuid_t _name = { \
_tl, _tm, _th, _cl, _ch, \
{ _n0, _n1, _n2, _n3, _n4, _n5 } \
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 72e42c6..ddc0808 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -206,7 +206,8 @@
*/
.globl print_errata_status
func print_errata_status
- push {r4, lr}
+ /* r12 is pushed only for the sake of 8-byte stack alignment */
+ push {r4, r5, r12, lr}
#ifdef IMAGE_BL1
/*
* BL1 doesn't have per-CPU data. So retrieve the CPU operations
@@ -241,6 +242,6 @@
blxne r4
1:
#endif
- pop {r4, pc}
+ pop {r4, r5, r12, pc}
endfunc print_errata_status
#endif
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index 87e52bd..ac51265 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -140,6 +140,15 @@
optee_header = (optee_header_t *)header_ep->pc;
assert(optee_header);
+ /* Print the OPTEE header information */
+ INFO("OPTEE ep=0x%x\n", (unsigned int)header_ep->pc);
+ INFO("OPTEE header info:\n");
+ INFO(" magic=0x%x\n", optee_header->magic);
+ INFO(" version=0x%x\n", optee_header->version);
+ INFO(" arch=0x%x\n", optee_header->arch);
+ INFO(" flags=0x%x\n", optee_header->flags);
+ INFO(" nb_images=0x%x\n", optee_header->nb_images);
+
/*
* OPTEE image has 3 types:
*
@@ -167,15 +176,6 @@
return 0;
}
- /* Print the OPTEE header information */
- INFO("OPTEE ep=0x%x\n", (unsigned int)header_ep->pc);
- INFO("OPTEE header info:\n");
- INFO(" magic=0x%x\n", optee_header->magic);
- INFO(" version=0x%x\n", optee_header->version);
- INFO(" arch=0x%x\n", optee_header->arch);
- INFO(" flags=0x%x\n", optee_header->flags);
- INFO(" nb_images=0x%x\n", optee_header->nb_images);
-
/* Parse OPTEE image */
for (num = 0; num < optee_header->nb_images; num++) {
if (optee_header->optee_image[num].image_id ==
diff --git a/plat/arm/common/aarch32/arm_helpers.S b/plat/arm/common/aarch32/arm_helpers.S
index f56b215..c4cfa8a 100644
--- a/plat/arm/common/aarch32/arm_helpers.S
+++ b/plat/arm/common/aarch32/arm_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -68,10 +68,10 @@
* Function to force a write of all buffered
* data that hasn't been output.
* Out : return -1 on error else return 0.
- * Clobber list : r0 - r1
+ * Clobber list : r0
* ---------------------------------------------
*/
func plat_crash_console_flush
- ldr r1, =PLAT_ARM_CRASH_UART_BASE
+ ldr r0, =PLAT_ARM_CRASH_UART_BASE
b console_core_flush
endfunc plat_crash_console_flush
diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S
index 9d3a108..760a53a 100644
--- a/plat/arm/common/aarch64/arm_helpers.S
+++ b/plat/arm/common/aarch64/arm_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -70,11 +70,11 @@
* Function to force a write of all buffered
* data that hasn't been output.
* Out : return -1 on error else return 0.
- * Clobber list : r0 - r1
+ * Clobber list : r0
* ---------------------------------------------
*/
func plat_crash_console_flush
- mov_imm x1, PLAT_ARM_CRASH_UART_BASE
+ mov_imm x0, PLAT_ARM_CRASH_UART_BASE
b console_core_flush
endfunc plat_crash_console_flush
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 5d83118..906ed19 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -24,6 +24,20 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
+/*
+ * Check that BL2_BASE is atleast a page over ARM_BL_RAM_BASE. The page is for
+ * `meminfo_t` data structure and TB_FW_CONFIG passed from BL1. Not needed
+ * when BL2 is compiled for BL_AT_EL3 as BL2 doesn't need any info from BL1 and
+ * BL2 is loaded at base of usable SRAM.
+ */
+#if BL2_AT_EL3
+#define BL1_MEMINFO_OFFSET 0x0
+#else
+#define BL1_MEMINFO_OFFSET PAGE_SIZE
+#endif
+
+CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows);
+
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl2_early_platform_setup
#pragma weak bl2_platform_setup
diff --git a/plat/arm/common/sp_min/arm_sp_min.mk b/plat/arm/common/sp_min/arm_sp_min.mk
index e6792ca..edab884 100644
--- a/plat/arm/common/sp_min/arm_sp_min.mk
+++ b/plat/arm/common/sp_min/arm_sp_min.mk
@@ -5,6 +5,13 @@
#
# SP MIN source files common to ARM standard platforms
+
+# Skip building BL1 and BL2 if RESET_TO_SP_MIN flag is set.
+ifeq (${RESET_TO_SP_MIN},1)
+ BL1_SOURCES =
+ BL2_SOURCES =
+endif
+
BL32_SOURCES += plat/arm/common/arm_pm.c \
plat/arm/common/arm_topology.c \
plat/arm/common/sp_min/arm_sp_min_setup.c \
diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c
index 38e1a61..ca6c03b 100644
--- a/plat/common/plat_gicv2.c
+++ b/plat/common/plat_gicv2.c
@@ -134,6 +134,8 @@
type == INTR_TYPE_EL3 ||
type == INTR_TYPE_NS);
+ assert(sec_state_is_valid(security_state));
+
/* Non-secure interrupts are signaled on the IRQ line always */
if (type == INTR_TYPE_NS)
return __builtin_ctz(SCR_IRQ_BIT);
diff --git a/plat/hisilicon/hikey960/hikey960_pm.c b/plat/hisilicon/hikey960/hikey960_pm.c
index 6609530..22963c4 100644
--- a/plat/hisilicon/hikey960/hikey960_pm.c
+++ b/plat/hisilicon/hikey960/hikey960_pm.c
@@ -29,6 +29,7 @@
#define DMAC_GLB_REG_SEC 0x694
#define AXI_CONF_BASE 0x820
+static unsigned int uart_base;
static uintptr_t hikey960_sec_entrypoint;
static void hikey960_pwr_domain_standby(plat_local_state_t cpu_state)
@@ -263,7 +264,7 @@
if (hisi_test_ap_suspend_flag(cluster)) {
hikey960_sr_dma_reinit();
gicv2_cpuif_enable();
- console_init(PL011_UART6_BASE, PL011_UART_CLK_IN_HZ,
+ console_init(uart_base, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE);
}
@@ -295,6 +296,19 @@
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
+ unsigned int id = 0;
+ int ret;
+
+ ret = hikey960_read_boardid(&id);
+ if (ret == 0) {
+ if (id == 5300U)
+ uart_base = PL011_UART5_BASE;
+ else
+ uart_base = PL011_UART6_BASE;
+ } else {
+ uart_base = PL011_UART6_BASE;
+ }
+
hikey960_sec_entrypoint = sec_entrypoint;
INFO("%s: sec_entrypoint=0x%lx\n", __func__,
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index ec7a277..7a06455 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -10,7 +10,7 @@
#include <arch.h>
#include <platform_def.h>
#include <psci.h>
-#include <xlat_tables.h>
+#include <xlat_tables_v2.h>
/*******************************************************************************
* Tegra DRAM memory base address
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index 2419965..4cbb3cc 100644
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -8,7 +8,7 @@
#include <bl_common.h>
#include <tegra_def.h>
#include <tegra_private.h>
-#include <xlat_tables.h>
+#include <xlat_tables_v2.h>
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index ba24579..fad6a59 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -20,7 +20,7 @@
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
-#include <xlat_tables.h>
+#include <xlat_tables_v2.h>
DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
extern uint64_t tegra_enable_l2_ecc_parity_prot;
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index b058bed..c3fc7b4 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -9,7 +9,7 @@
#include <console.h>
#include <tegra_def.h>
#include <tegra_private.h>
-#include <xlat_tables.h>
+#include <xlat_tables_v2.h>
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 334fbe4..26633c2 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -150,12 +150,12 @@
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/common/gic_common.c \
+ plat/common/plat_gicv2.c \
plat/common/plat_psci_common.c \
plat/qemu/qemu_pm.c \
plat/qemu/topology.c \
plat/qemu/aarch64/plat_helpers.S \
- plat/qemu/qemu_bl31_setup.c \
- plat/qemu/qemu_gic.c
+ plat/qemu/qemu_bl31_setup.c
endif
# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
diff --git a/plat/qemu/qemu_gic.c b/plat/qemu/qemu_gic.c
deleted file mode 100644
index 41b5eb4..0000000
--- a/plat/qemu/qemu_gic.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <bl_common.h>
-#include <gicv2.h>
-#include <interrupt_mgmt.h>
-
-uint32_t plat_ic_get_pending_interrupt_id(void)
-{
- return gicv2_get_pending_interrupt_id();
-}
-
-uint32_t plat_ic_get_pending_interrupt_type(void)
-{
- return gicv2_get_pending_interrupt_type();
-}
-
-uint32_t plat_ic_acknowledge_interrupt(void)
-{
- return gicv2_acknowledge_interrupt();
-}
-
-uint32_t plat_ic_get_interrupt_type(uint32_t id)
-{
- uint32_t group;
-
- group = gicv2_get_interrupt_group(id);
-
- /* Assume that all secure interrupts are S-EL1 interrupts */
- if (!group)
- return INTR_TYPE_S_EL1;
- else
- return INTR_TYPE_NS;
-
-}
-
-void plat_ic_end_of_interrupt(uint32_t id)
-{
- gicv2_end_of_interrupt(id);
-}
-
-uint32_t plat_interrupt_type_to_line(uint32_t type,
- uint32_t security_state)
-{
- assert(type == INTR_TYPE_S_EL1 ||
- type == INTR_TYPE_EL3 ||
- type == INTR_TYPE_NS);
-
- assert(sec_state_is_valid(security_state));
-
- /* Non-secure interrupts are signalled on the IRQ line always */
- if (type == INTR_TYPE_NS)
- return __builtin_ctz(SCR_IRQ_BIT);
-
- /*
- * Secure interrupts are signalled using the IRQ line if the FIQ_EN
- * bit is not set else they are signalled using the FIQ line.
- */
- if (gicv2_is_fiq_enabled())
- return __builtin_ctz(SCR_FIQ_BIT);
- else
- return __builtin_ctz(SCR_IRQ_BIT);
-}
-
diff --git a/plat/qemu/sp_min/sp_min-qemu.mk b/plat/qemu/sp_min/sp_min-qemu.mk
index 5e8875b..e93a0c2 100644
--- a/plat/qemu/sp_min/sp_min-qemu.mk
+++ b/plat/qemu/sp_min/sp_min-qemu.mk
@@ -6,7 +6,6 @@
BL32_SOURCES += plat/qemu/sp_min/sp_min_setup.c \
plat/qemu/aarch32/plat_helpers.S \
- plat/qemu/qemu_gic.c \
plat/qemu/qemu_pm.c \
plat/qemu/topology.c
@@ -14,7 +13,8 @@
lib/cpus/aarch32/cortex_a15.S
BL32_SOURCES += plat/common/aarch32/platform_mp_stack.S \
- plat/common/plat_psci_common.c
+ plat/common/plat_psci_common.c \
+ plat/common/plat_gicv2.c
BL32_SOURCES += drivers/arm/gic/v2/gicv2_helpers.c \
diff --git a/services/std_svc/sdei/sdei_state.c b/services/std_svc/sdei/sdei_state.c
index 3f60dfd..c1f099f 100644
--- a/services/std_svc/sdei/sdei_state.c
+++ b/services/std_svc/sdei/sdei_state.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -46,9 +46,7 @@
/*
* SDEI handler state machine: refer to sections 6.1 and 6.1.2 of the SDEI v1.0
- * specification:
- *
- * http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
+ * specification (ARM DEN0054A).
*
* Not all calls contribute to handler state transition. This table is also used
* to validate whether a call is permissible at a given handler state: