Disable secure self-hosted debug via MDCR_EL3/SDCR
Trusted Firmware currently has no support for secure self-hosted
debug. To avoid unexpected exceptions, disable software debug
exceptions, other than software breakpoint instruction exceptions,
from all exception levels in secure state. This applies to both
AArch32 and AArch64 EL3 initialization.
Change-Id: Id097e54a6bbcd0ca6a2be930df5d860d8d09e777
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S
index 463a080..f6b7527 100644
--- a/include/common/aarch32/el3_common_macros.S
+++ b/include/common/aarch32/el3_common_macros.S
@@ -98,6 +98,11 @@
orr r0, r0, #FPEXC_EN_BIT
vmsr FPEXC, r0
isb
+
+ /* Disable secure self-hosted invasive debug. */
+ ldr r0, =SDCR_DEF_VAL
+ stcopr r0, SDCR
+
.endm
/* -----------------------------------------------------------------------------
diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S
index cbfa6ee..d8fd625 100644
--- a/include/common/aarch64/el3_common_macros.S
+++ b/include/common/aarch64/el3_common_macros.S
@@ -79,10 +79,11 @@
msr scr_el3, x0
/* ---------------------------------------------------------------------
- * Reset registers that may have architecturally unknown reset values
+ * Disable secure self-hosted invasive debug.
* ---------------------------------------------------------------------
*/
- msr mdcr_el3, xzr
+ mov_imm x0, MDCR_DEF_VAL
+ msr mdcr_el3, x0
/* ---------------------------------------------------------------------
* Enable External Aborts and SError Interrupts now that the exception