commit 594919f3948fb3d115af01f782981e3e5d95b5ab
author Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Mon Nov 30 20:36:09 2020 +0900
committer Marek Vasut <marek.vasut+renesas@gmail.com> Sat Jul 10 17:35:15 2021 +0200
tree 8f488af48fb0d92fb4bc6c258d69eee43e6d715e
parent 9601d5a2d9c8a519220233669a02a20aced53360

fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition

emmc_registers.h contains redefinition of
CPG_CPGWPR from bl2_cpg_register.h

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ie13590100df08f32193653e50191e66ed42d2b28

drivers/renesas/common/emmc/emmc_registers.h

diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h
index 7fae5e4..370cc1c 100644
--- a/drivers/renesas/common/emmc/emmc_registers.h
+++ b/drivers/renesas/common/emmc/emmc_registers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -60,8 +60,6 @@
 #define CPG_SD2CKCR	(CPG_BASE + 0x0268U)
 /* SDHI3 clock frequency control register */
 #define CPG_SD3CKCR	(CPG_BASE + 0x026CU)
-/* CPG Write Protect Register */
-#define CPG_CPGWPR	(CPG_BASE + 0x0900U)
 
 #if USE_MMC_CH == MMC_CH0
 #define CPG_SDxCKCR		(CPG_SD2CKCR)	/* SDHI2/MMC0 */