plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
diff --git a/plat/intel/soc/stratix10/include/plat_macros.S b/plat/intel/soc/stratix10/include/plat_macros.S
new file mode 100644
index 0000000..667f6c8
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/plat_macros.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_MACROS_S__
+#define __PLAT_MACROS_S__
+
+#include <platform_def.h>
+
+ /* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ mov_imm x17, PLAT_GICC_BASE
+ mov_imm x16, PLAT_GICD_BASE
+ arm_print_gic_regs
+ .endm
+
+#endif /* __PLAT_MACROS_S__ */
diff --git a/plat/intel/soc/stratix10/include/platform_private.h b/plat/intel/soc/stratix10/include/platform_private.h
new file mode 100644
index 0000000..db0c103
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/platform_private.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLATFORM_PRIVATE_H__
+#define __PLATFORM_PRIVATE_H__
+#include <common/bl_common.h>
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_configure_mmu_el3(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit,
+ unsigned long coh_start,
+ unsigned long coh_limit);
+
+
+void plat_configure_mmu_el1(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit,
+ unsigned long coh_start,
+ unsigned long coh_limit);
+
+void plat_gic_driver_init(void);
+
+void plat_arm_gic_init(void);
+
+void plat_delay_timer_init(void);
+
+unsigned long plat_get_ns_image_entrypoint(void);
+
+uint32_t plat_get_spsr_for_bl32_entry(void);
+
+uint32_t plat_get_spsr_for_bl33_entry(void);
+
+#endif /* __PLATFORM_PRIVATE_H__ */
diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h
new file mode 100644
index 0000000..28192fa
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __CLOCKMANAGER_H__
+#define __CLOCKMANAGER_H__
+
+#include "s10_handoff.h"
+
+#define ALT_CLKMGR 0xffd10000
+
+#define ALT_CLKMGR_CTRL 0x0
+#define ALT_CLKMGR_STAT 0x4
+#define ALT_CLKMGR_INTRCLR 0x14
+#define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004
+#define ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008
+
+#define ALT_CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001
+#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
+#define ALT_CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0)
+#define ALT_CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8)
+#define ALT_CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00000200) >> 9)
+
+#define ALT_CLKMGR_MAINPLL 0xffd10030
+#define ALT_CLKMGR_MAINPLL_EN 0x0
+#define ALT_CLKMGR_MAINPLL_BYPASS 0xc
+#define ALT_CLKMGR_MAINPLL_MPUCLK 0x18
+#define ALT_CLKMGR_MAINPLL_NOCCLK 0x1c
+#define ALT_CLKMGR_MAINPLL_CNTR2CLK 0x20
+#define ALT_CLKMGR_MAINPLL_CNTR3CLK 0x24
+#define ALT_CLKMGR_MAINPLL_CNTR4CLK 0x28
+#define ALT_CLKMGR_MAINPLL_CNTR5CLK 0x2c
+#define ALT_CLKMGR_MAINPLL_CNTR6CLK 0x30
+#define ALT_CLKMGR_MAINPLL_CNTR7CLK 0x34
+#define ALT_CLKMGR_MAINPLL_CNTR8CLK 0x38
+#define ALT_CLKMGR_MAINPLL_CNTR9CLK 0x3c
+#define ALT_CLKMGR_MAINPLL_NOCDIV 0x40
+#define ALT_CLKMGR_MAINPLL_PLLGLOB 0x44
+#define ALT_CLKMGR_MAINPLL_FDBCK 0x48
+#define ALT_CLKMGR_MAINPLL_PLLC0 0x54
+#define ALT_CLKMGR_MAINPLL_PLLC1 0x58
+#define ALT_CLKMGR_MAINPLL_VCOCALIB 0x5c
+#define ALT_CLKMGR_MAINPLL_EN_RESET 0x000000ff
+#define ALT_CLKMGR_MAINPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24)
+#define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001
+#define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
+#define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002
+#define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff)
+#define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00)
+
+#define ALT_CLKMGR_PERPLL 0xffd100a4
+#define ALT_CLKMGR_PERPLL_EN 0x0
+#define ALT_CLKMGR_PERPLL_BYPASS 0xc
+#define ALT_CLKMGR_PERPLL_CNTR2CLK 0x18
+#define ALT_CLKMGR_PERPLL_CNTR3CLK 0x1c
+#define ALT_CLKMGR_PERPLL_CNTR4CLK 0x20
+#define ALT_CLKMGR_PERPLL_CNTR5CLK 0x24
+#define ALT_CLKMGR_PERPLL_CNTR6CLK 0x28
+#define ALT_CLKMGR_PERPLL_CNTR7CLK 0x2c
+#define ALT_CLKMGR_PERPLL_CNTR8CLK 0x30
+#define ALT_CLKMGR_PERPLL_CNTR9CLK 0x34
+#define ALT_CLKMGR_PERPLL_GPIODIV 0x3c
+#define ALT_CLKMGR_PERPLL_EMACCTL 0x38
+#define ALT_CLKMGR_PERPLL_PLLGLOB 0x40
+#define ALT_CLKMGR_PERPLL_FDBCK 0x44
+#define ALT_CLKMGR_PERPLL_PLLC0 0x50
+#define ALT_CLKMGR_PERPLL_PLLC1 0x54
+#define ALT_CLKMGR_PERPLL_EN_RESET 0x00000fff
+#define ALT_CLKMGR_PERPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24)
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff)
+#define ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001
+#define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
+#define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_SET(x) (((x) << 8) & 0x00003f00)
+#define ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002
+#define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff)
+#define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00)
+#define ALT_CLKMGR_PERPLL_VCOCALIB 0x58
+
+void config_clkmgr_handoff(handoff *hoff_ptr);
+
+#endif
diff --git a/plat/intel/soc/stratix10/include/s10_handoff.h b/plat/intel/soc/stratix10/include/s10_handoff.h
new file mode 100644
index 0000000..1cc8d09
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/s10_handoff.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HANDOFF_H_
+#define _HANDOFF_H_
+
+#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
+#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
+#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
+#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
+#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
+#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
+#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
+
+typedef struct handoff_t {
+ /* header */
+ uint32_t header_magic;
+ uint32_t header_device;
+ uint32_t _pad_0x08_0x10[2];
+
+ /* pinmux configuration - select */
+ uint32_t pinmux_sel_magic;
+ uint32_t pinmux_sel_length;
+ uint32_t _pad_0x18_0x20[2];
+ uint32_t pinmux_sel_array[96]; /* offset, value */
+
+ /* pinmux configuration - io control */
+ uint32_t pinmux_io_magic;
+ uint32_t pinmux_io_length;
+ uint32_t _pad_0x1a8_0x1b0[2];
+ uint32_t pinmux_io_array[96]; /* offset, value */
+
+ /* pinmux configuration - use fpga switch */
+ uint32_t pinmux_fpga_magic;
+ uint32_t pinmux_fpga_length;
+ uint32_t _pad_0x338_0x340[2];
+ uint32_t pinmux_fpga_array[42]; /* offset, value */
+ uint32_t _pad_0x3e8_0x3f0[2];
+
+ /* pinmux configuration - io delay */
+ uint32_t pinmux_delay_magic;
+ uint32_t pinmux_delay_length;
+ uint32_t _pad_0x3f8_0x400[2];
+ uint32_t pinmux_iodelay_array[96]; /* offset, value */
+
+ /* clock configuration */
+ uint32_t clock_magic;
+ uint32_t clock_length;
+ uint32_t _pad_0x588_0x590[2];
+ uint32_t main_pll_mpuclk;
+ uint32_t main_pll_nocclk;
+ uint32_t main_pll_cntr2clk;
+ uint32_t main_pll_cntr3clk;
+ uint32_t main_pll_cntr4clk;
+ uint32_t main_pll_cntr5clk;
+ uint32_t main_pll_cntr6clk;
+ uint32_t main_pll_cntr7clk;
+ uint32_t main_pll_cntr8clk;
+ uint32_t main_pll_cntr9clk;
+ uint32_t main_pll_nocdiv;
+ uint32_t main_pll_pllglob;
+ uint32_t main_pll_fdbck;
+ uint32_t main_pll_pllc0;
+ uint32_t main_pll_pllc1;
+ uint32_t _pad_0x5cc_0x5d0[1];
+ uint32_t per_pll_cntr2clk;
+ uint32_t per_pll_cntr3clk;
+ uint32_t per_pll_cntr4clk;
+ uint32_t per_pll_cntr5clk;
+ uint32_t per_pll_cntr6clk;
+ uint32_t per_pll_cntr7clk;
+ uint32_t per_pll_cntr8clk;
+ uint32_t per_pll_cntr9clk;
+ uint32_t per_pll_emacctl;
+ uint32_t per_pll_gpiodiv;
+ uint32_t per_pll_pllglob;
+ uint32_t per_pll_fdbck;
+ uint32_t per_pll_pllc0;
+ uint32_t per_pll_pllc1;
+ uint32_t hps_osc_clk_h;
+ uint32_t fpga_clk_hz;
+
+ /* misc configuration */
+ uint32_t misc_magic;
+ uint32_t misc_length;
+ uint32_t _pad_0x618_0x620[2];
+ uint32_t boot_source;
+} handoff;
+
+int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
+int s10_get_handoff(handoff *hoff_ptr);
+
+#endif
+
+
diff --git a/plat/intel/soc/stratix10/include/s10_memory_controller.h b/plat/intel/soc/stratix10/include/s10_memory_controller.h
new file mode 100644
index 0000000..f2a3e19
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/s10_memory_controller.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __S10_MEMORYCONTROLLER_H__
+#define __S10_MEMORYCONTROLLER_H__
+
+#define S10_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8
+#define S10_MPFE_IOHMC_CTRLCFG0 0xf8010028
+#define S10_MPFE_IOHMC_CTRLCFG1 0xf801002c
+#define S10_MPFE_IOHMC_DRAMADDRW 0xf80100a8
+#define S10_MPFE_IOHMC_DRAMTIMING0 0xf8010050
+#define S10_MPFE_IOHMC_CALTIMING0 0xf801007c
+#define S10_MPFE_IOHMC_CALTIMING1 0xf8010080
+#define S10_MPFE_IOHMC_CALTIMING2 0xf8010084
+#define S10_MPFE_IOHMC_CALTIMING3 0xf8010088
+#define S10_MPFE_IOHMC_CALTIMING4 0xf801008c
+#define S10_MPFE_IOHMC_CALTIMING9 0xf80100a0
+#define S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0)
+#define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \
+ (((value) & 0x00000060) >> 5)
+
+#define S10_RSTMGR_BRGMODRST 0xffd1102c
+#define S10_RSTMGR_BRGMODRST_DDRSCH 0x00000040
+
+#define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
+#define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
+#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
+#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff
+#define S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214
+
+
+#define S10_MPFE_IOHMC_REG_CTRLCFG1 0xf801002c
+
+#define S10_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0xf8010110
+
+#define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0)
+#define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5)
+#define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16)
+#define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14)
+#define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10)
+
+#define S10_MPFE_DDR(x) (0xf8000000 + x)
+#define S10_MPFE_HMC_ADP_DDRCALSTAT 0xf801100c
+#define S10_MPFE_DDR_MAIN_SCHED 0xf8000400
+#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF 0xf8000408
+#define S10_MPFE_DDR_MAIN_SCHED_DDRTIMING 0xf800040c
+#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f
+#define S10_MPFE_DDR_MAIN_SCHED_DDRMODE 0xf8000410
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV 0xf800043c
+#define S10_MPFE_DDR_MAIN_SCHED_READLATENCY 0xf8000414
+#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE 0xf8000438
+#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10
+#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST 4
+#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST 0
+#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f)
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST 0
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST 2
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST 4
+
+#define S10_MPFE_HMC_ADP(x) (0xf8011000 + (x))
+#define S10_MPFE_HMC_ADP_HPSINTFCSEL 0xf8011210
+#define S10_MPFE_HMC_ADP_DDRIOCTRL 0xf8011008
+#define HMC_ADP_DDRIOCTRL 0x8
+#define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
+#define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x) (((x) & 0x00003e00) >> 9)
+#define ADP_DRAMADDRWIDTH 0xe0
+
+#define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18)
+#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12)
+#define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0)
+#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12)
+
+/* timing 2 */
+#define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6)
+#define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24)
+#define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18)
+#define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6)
+
+/* timing 3 */
+#define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12)
+#define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6)
+
+/* timing 4 */
+#define PCH_TO_VALID(value) (((value) & 0x00000fc0) >> 6)
+
+#define DDRTIMING_BWRATIO_OFST 31
+#define DDRTIMING_WRTORD_OFST 26
+#define DDRTIMING_RDTOWR_OFST 21
+#define DDRTIMING_BURSTLEN_OFST 18
+#define DDRTIMING_WRTOMISS_OFST 12
+#define DDRTIMING_RDTOMISS_OFST 6
+#define DDRTIMING_ACTTOACT_OFST 0
+
+#define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
+
+#define DDRMODE_AUTOPRECHARGE_OFST 1
+#define DDRMODE_BWRATIOEXTENDED_OFST 0
+
+
+#define S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x0000007f) >> 0)
+#define S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x) (((x) & 0x0000000f) >> 0)
+
+#define S10_CCU_CPU0_MPRT_DDR 0xf7004400
+#define S10_CCU_CPU0_MPRT_MEM0 0xf70045c0
+#define S10_CCU_CPU0_MPRT_MEM1A 0xf70045e0
+#define S10_CCU_CPU0_MPRT_MEM1B 0xf7004600
+#define S10_CCU_CPU0_MPRT_MEM1C 0xf7004620
+#define S10_CCU_CPU0_MPRT_MEM1D 0xf7004640
+#define S10_CCU_CPU0_MPRT_MEM1E 0xf7004660
+#define S10_CCU_IOM_MPRT_MEM0 0xf7018560
+#define S10_CCU_IOM_MPRT_MEM1A 0xf7018580
+#define S10_CCU_IOM_MPRT_MEM1B 0xf70185a0
+#define S10_CCU_IOM_MPRT_MEM1C 0xf70185c0
+#define S10_CCU_IOM_MPRT_MEM1D 0xf70185e0
+#define S10_CCU_IOM_MPRT_MEM1E 0xf7018600
+
+#define S10_NOC_FW_DDR_SCR 0xf8020100
+#define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0xf802011c
+#define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT 0xf8020118
+#define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0xf802019c
+#define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020198
+
+#define S10_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020100
+#define S10_CCU_NOC_DI_SET_MSK 0x10
+
+#define S10_SYSMGR_CORE_HMC_CLK 0xffd120b4
+#define S10_SYSMGR_CORE_HMC_CLK_STATUS 0x00000001
+
+#define S10_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x) (((x) & 0x0000ffff) >> 0)
+#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
+#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST 0
+#define S10_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE 0x001f1f1f
+#define S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST 7
+
+#define S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
+#define S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100
+#define S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001
+
+#define S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001
+#define S10_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
+#define S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100
+#define S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(value) (((value) & 0x00000001) >> 0)
+
+
+#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
+#define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10)
+#define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14)
+#define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0)
+#define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16)
+#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5)
+
+#define S10_SDRAM_0_LB_ADDR 0x0
+
+int init_hard_memory_controller(void);
+
+#endif
diff --git a/plat/intel/soc/stratix10/include/s10_noc.h b/plat/intel/soc/stratix10/include/s10_noc.h
new file mode 100644
index 0000000..3e1e527
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/s10_noc.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define AXI_AP (1<<0)
+#define FPGA2SOC (1<<16)
+#define MPU (1<<24)
+#define S10_NOC_PER_SCR_NAND 0xffd21000
+#define S10_NOC_PER_SCR_NAND_DATA 0xffd21004
+#define S10_NOC_PER_SCR_USB0 0xffd2100c
+#define S10_NOC_PER_SCR_USB1 0xffd21010
+#define S10_NOC_PER_SCR_SPI_M0 0xffd2101c
+#define S10_NOC_PER_SCR_SPI_M1 0xffd21020
+#define S10_NOC_PER_SCR_SPI_S0 0xffd21024
+#define S10_NOC_PER_SCR_SPI_S1 0xffd21028
+#define S10_NOC_PER_SCR_EMAC0 0xffd2102c
+#define S10_NOC_PER_SCR_EMAC1 0xffd21030
+#define S10_NOC_PER_SCR_EMAC2 0xffd21034
+#define S10_NOC_PER_SCR_SDMMC 0xffd21040
+#define S10_NOC_PER_SCR_GPIO0 0xffd21044
+#define S10_NOC_PER_SCR_GPIO1 0xffd21048
+#define S10_NOC_PER_SCR_I2C0 0xffd21050
+#define S10_NOC_PER_SCR_I2C1 0xffd21058
+#define S10_NOC_PER_SCR_I2C2 0xffd2105c
+#define S10_NOC_PER_SCR_I2C3 0xffd21060
+#define S10_NOC_PER_SCR_SP_TIMER0 0xffd21064
+#define S10_NOC_PER_SCR_SP_TIMER1 0xffd21068
+#define S10_NOC_PER_SCR_UART0 0xffd2106c
+#define S10_NOC_PER_SCR_UART1 0xffd21070
+
+
+#define S10_NOC_SYS_SCR_DMA_ECC 0xffd21108
+#define S10_NOC_SYS_SCR_EMAC0RX_ECC 0xffd2110c
+#define S10_NOC_SYS_SCR_EMAC0TX_ECC 0xffd21110
+#define S10_NOC_SYS_SCR_EMAC1RX_ECC 0xffd21114
+#define S10_NOC_SYS_SCR_EMAC1TX_ECC 0xffd21118
+#define S10_NOC_SYS_SCR_EMAC2RX_ECC 0xffd2111c
+#define S10_NOC_SYS_SCR_EMAC2TX_ECC 0xffd21120
+#define S10_NOC_SYS_SCR_NAND_ECC 0xffd2112c
+#define S10_NOC_SYS_SCR_NAND_READ_ECC 0xffd21130
+#define S10_NOC_SYS_SCR_NAND_WRITE_ECC 0xffd21134
+#define S10_NOC_SYS_SCR_OCRAM_ECC 0xffd21138
+#define S10_NOC_SYS_SCR_SDMMC_ECC 0xffd21140
+#define S10_NOC_SYS_SCR_USB0_ECC 0xffd21144
+#define S10_NOC_SYS_SCR_USB1_ECC 0xffd21148
+#define S10_NOC_SYS_SCR_CLK_MGR 0xffd2114c
+#define S10_NOC_SYS_SCR_IO_MGR 0xffd21154
+#define S10_NOC_SYS_SCR_RST_MGR 0xffd21158
+#define S10_NOC_SYS_SCR_SYS_MGR 0xffd2115c
+#define S10_NOC_SYS_SCR_OSC0_TIMER 0xffd21160
+#define S10_NOC_SYS_SCR_OSC1_TIMER 0xffd21164
+#define S10_NOC_SYS_SCR_WATCHDOG0 0xffd21168
+#define S10_NOC_SYS_SCR_WATCHDOG1 0xffd2116c
+#define S10_NOC_SYS_SCR_WATCHDOG2 0xffd21170
+#define S10_NOC_SYS_SCR_WATCHDOG3 0xffd21174
+#define S10_NOC_SYS_SCR_DAP 0xffd21178
+#define S10_NOC_SYS_SCR_L4_NOC_PROBES 0xffd21190
+#define S10_NOC_SYS_SCR_L4_NOC_QOS 0xffd21194
+
+#define S10_CCU_NOC_BRIDGE_CPU0_RAM 0xf7004688
+#define S10_CCU_NOC_BRIDGE_IOM_RAM 0xf7004688
diff --git a/plat/intel/soc/stratix10/include/s10_pinmux.h b/plat/intel/soc/stratix10/include/s10_pinmux.h
new file mode 100644
index 0000000..a1ba29e
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/s10_pinmux.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __S10_PINMUX_H__
+#define __S10_PINMUX_H__
+
+#define S10_PINMUX_PIN0SEL 0xffd13000
+#define S10_PINMUX_IO0CTRL 0xffd13130
+#define S10_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300
+#define S10_PINMUX_IO0_DELAY 0xffd13400
+
+#include "s10_handoff.h"
+
+void config_pinmux(handoff *handoff);
+
+#endif
+
diff --git a/plat/intel/soc/stratix10/include/s10_reset_manager.h b/plat/intel/soc/stratix10/include/s10_reset_manager.h
new file mode 100644
index 0000000..731a8dd
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/s10_reset_manager.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __S10_RESETMANAGER_H__
+#define __S10_RESETMANAGER_H__
+
+#define S10_RSTMGR_PER0MODRST 0xffd11024
+#define S10_RSTMGR_PER1MODRST 0xffd11028
+#define S10_RSTMGR_HDSKEN 0xffd11010
+
+#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
+#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
+#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
+#define S10_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
+#define S10_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
+#define S10_RSTMGR_PER0MODRST_DMAOCP 0x00200000
+#define S10_RSTMGR_PER0MODRST_DMA 0x00010000
+#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
+#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
+#define S10_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
+#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
+#define S10_RSTMGR_PER0MODRST_EMACPTP 0x00400000
+#define S10_RSTMGR_PER0MODRST_NANDOCP 0x00002000
+#define S10_RSTMGR_PER0MODRST_NAND 0x00000020
+#define S10_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
+#define S10_RSTMGR_PER0MODRST_SDMMC 0x00000080
+#define S10_RSTMGR_PER0MODRST_SPIM0 0x00020000
+#define S10_RSTMGR_PER0MODRST_SPIM1 0x00040000
+#define S10_RSTMGR_PER0MODRST_SPIS0 0x00080000
+#define S10_RSTMGR_PER0MODRST_SPIS1 0x00100000
+#define S10_RSTMGR_PER0MODRST_USB0OCP 0x00000800
+#define S10_RSTMGR_PER0MODRST_USB0 0x00000008
+#define S10_RSTMGR_PER0MODRST_USB1OCP 0x00001000
+#define S10_RSTMGR_PER0MODRST_USB1 0x00000010
+
+#define S10_RSTMGR_PER1MODRST_WATCHDOG0 0x1
+#define S10_RSTMGR_PER1MODRST_WATCHDOG1 0x2
+#define S10_RSTMGR_PER1MODRST_WATCHDOG2 0x4
+#define S10_RSTMGR_PER1MODRST_WATCHDOG3 0x8
+#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
+#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
+#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
+#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
+#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
+#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
+#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
+#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
+#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
+#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
+#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
+#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
+#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
+#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
+#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
+#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
+#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
+#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
+#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
+#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
+#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
+#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
+#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
+#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
+#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
+#define S10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
+#define S10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004
+#define S10_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
+#define S10_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
+
+#define S10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
+#define S10_RSTMGR_PER0MODRST_DMAIF0 0x01000000
+#define S10_RSTMGR_PER0MODRST_DMAIF1 0x02000000
+#define S10_RSTMGR_PER0MODRST_DMAIF2 0x04000000
+#define S10_RSTMGR_PER0MODRST_DMAIF3 0x08000000
+#define S10_RSTMGR_PER0MODRST_DMAIF4 0x10000000
+#define S10_RSTMGR_PER0MODRST_DMAIF5 0x20000000
+#define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000
+#define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000
+
+void deassert_peripheral_reset(void);
+void config_hps_hs_before_warm_reset(void);
+
+#endif
+
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
new file mode 100644
index 0000000..802386c
--- /dev/null
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
+#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
+#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
+#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010
+#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c
+#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020
+#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024
+#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028
+#define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c
+#define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030
+#define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034
+#define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040
+#define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044
+#define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048
+#define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050
+#define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054
+#define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058
+#define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c
+#define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060
+#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064
+#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068
+#define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c
+#define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070
+
+#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108
+#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c
+#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110
+#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114
+#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118
+#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c
+#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120
+#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c
+#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130
+#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134
+#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138
+#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140
+#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144
+#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148
+#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c
+#define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154
+#define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158
+#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c
+#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160
+#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164
+#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168
+#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c
+#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170
+#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174
+#define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178
+#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190
+#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194
+
+#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
+#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
+
+#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
+
+void enable_nonsecure_access(void);
+