diff --git a/bl31/ehf.c b/bl31/ehf.c
index 745f165..b328380 100644
--- a/bl31/ehf.c
+++ b/bl31/ehf.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -475,9 +475,16 @@
 	assert((exception_data.pri_bits >= 1U) ||
 			(exception_data.pri_bits < 8U));
 
-	/* Route EL3 interrupts when in Secure and Non-secure. */
+	/* Route EL3 interrupts when in Non-secure. */
 	set_interrupt_rm_flag(flags, NON_SECURE);
+
+	/*
+	 * Route EL3 interrupts when in secure, only when SPMC is not present
+	 * in S-EL2.
+	 */
+#if !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1))
 	set_interrupt_rm_flag(flags, SECURE);
+#endif /* !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)) */
 
 	/* Register handler for EL3 interrupts */
 	ret = register_interrupt_type_handler(INTR_TYPE_EL3,
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 471cd0a..cca76c6 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -467,8 +467,11 @@
 
 -  ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
    targeted at EL3. When set ``0`` (default), no exceptions are expected or
-   handled at EL3, and a panic will result. This is supported only for AArch64
-   builds.
+   handled at EL3, and a panic will result. The exception to this rule is when
+   ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions
+   occuring during normal world execution, are trapped to EL3. Any exception
+   trapped during secure world execution are trapped to the SPMC. This is
+   supported only for AArch64 builds.
 
 -  ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when
    ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 0cef16a..1f497e0 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -21,6 +21,7 @@
    marvell/index
    mt8183
    mt8186
+   mt8188
    mt8192
    mt8195
    nvidia-tegra
diff --git a/docs/plat/marvell/armada/uart-booting.rst b/docs/plat/marvell/armada/uart-booting.rst
new file mode 100644
index 0000000..06601d1
--- /dev/null
+++ b/docs/plat/marvell/armada/uart-booting.rst
@@ -0,0 +1,103 @@
+TF-A UART Booting Instructions for Marvell Platforms
+====================================================
+
+This section describes how to temporary boot the Trusted Firmware-A (TF-A) project over UART
+without flashing it to non-volatile storage for Marvell's platforms.
+
+See :ref:`TF-A Build Instructions for Marvell Platforms` how to build ``mrvl_uart`` and
+``mrvl_flash`` targets used in this section.
+
+Armada37x0 UART image downloading
+---------------------------------
+
+There are two options how to download UART image into any Armada37x0 board.
+
+Marvell Wtpdownloader
+~~~~~~~~~~~~~~~~~~~~~
+
+Marvell Wtpdownloader works only with UART images stored in separate files and supports only upload
+speed with 115200 bauds. Target ``mrvl_uart`` produces GZIPed TAR archive ``uart-images.tgz.bin``
+with either three files ``TIM_ATF.bin``, ``wtmi_h.bin`` and ``boot-image_h.bin`` for non-secure
+boot or with four files ``TIM_ATF_TRUSTED.bin``, ``TIMN_ATF_TRUSTED.bin``, ``wtmi_h.bin`` and
+``boot-image_h.bin`` when secure boot is enabled.
+
+Compilation:
+
+.. code:: shell
+
+    > git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
+    > make -C A3700-utils-marvell/wtptp/src/Wtpdownloader_Linux -f makefile.mk
+
+It produces executable binary ``A3700-utils-marvell/wtptp/src/Wtpdownloader_Linux/WtpDownload_linux``
+
+To download images from ``uart-images.tgz.bin`` archive unpack it and for non-secure boot variant run:
+
+.. code:: shell
+
+    > stty -F /dev/ttyUSB<port#> clocal
+    > WtpDownload_linux -P UART -C <port#> -E -B TIM_ATF.bin -I wtmi_h.bin -I boot-image_h.bin
+
+After that immediately start terminal on ``/dev/ttyUSB<port#>`` to see boot output.
+
+CZ.NIC mox-imager
+~~~~~~~~~~~~~~~~~
+
+CZ.NIC mox-imager supports all Armada37x0 boards (not only Turris MOX as name suggests). It works
+with either with separate files from ``uart-images.tgz.bin`` archive (like Marvell Wtpdownloader)
+produced by ``mrvl_uart`` target or also with ``flash-image.bin`` file produced by ``mrvl_flash``
+target, which is the exactly same file as used for flashing. So when using CZ.NIC mox-imager there
+is no need to build separate files for UART flashing like in case with Marvell Wtpdownloader.
+
+CZ.NIC mox-imager moreover supports higher upload speeds up to the 6000000 bauds (which seems to
+be limit of Armada37x0 SoC) which is much higher and faster than Marvell Wtpdownloader.
+
+Compilation:
+
+.. code:: shell
+
+    > git clone https://gitlab.nic.cz/turris/mox-imager.git
+    > make -C mox-imager
+
+It produces executable binary ``mox-imager/mox-imager``
+
+To download single file image built by ``mrvl_flash`` target at the highest speed, run:
+
+.. code:: shell
+
+    > mox-imager -D /dev/ttyUSB<port#> -E -b 6000000 -t flash-image.bin
+
+To download images from ``uart-images.tgz.bin`` archive built by ``mrvl_uart`` target for
+non-secure boot variant (like Wtpdownloader) but at the highest speed, first unpack
+``uart-images.tgz.bin`` archive and then run:
+
+.. code:: shell
+
+    > mox-imager -D /dev/ttyUSB<port#> -E -b 6000000 -t TIM_ATF.bin wtmi_h.bin boot-image_h.bin
+
+CZ.NIC mox-imager after successful download will start its own mini terminal (option ``-t``) to
+not loose any boot output. It also prints boot output which is sent either by image files or by
+bootrom during transferring of image files. This mini terminal can be quit by CTRL-\\ + C keypress.
+
+
+A7K/8K/CN913x UART image downloading
+------------------------------------
+
+A7K/8K/CN913x uses same image ``flash-image.bin`` for both flashing and booting over UART.
+For downloading image over UART it is possible to use mvebu64boot tool.
+
+Compilation:
+
+.. code:: shell
+
+    > git clone https://github.com/pali/mvebu64boot.git
+    > make -C mvebu64boot
+
+It produces executable binary ``mvebu64boot/mvebu64boot``
+
+To download ``flash-image.bin`` image run:
+
+.. code:: shell
+
+    > mvebu64boot -t -b flash-image.bin /dev/ttyUSB0
+
+After successful download it will start own mini terminal (option ``-t``) like CZ.NIC mox-imager.
diff --git a/docs/plat/marvell/index.rst b/docs/plat/marvell/index.rst
index 0d33432..2d5cdeb 100644
--- a/docs/plat/marvell/index.rst
+++ b/docs/plat/marvell/index.rst
@@ -6,6 +6,7 @@
    :caption: Contents
 
    armada/build
+   armada/uart-booting
    armada/porting
    armada/misc/mvebu-a8k-addr-map
    armada/misc/mvebu-amb
diff --git a/docs/plat/mt8188.rst b/docs/plat/mt8188.rst
new file mode 100644
index 0000000..93abaa5
--- /dev/null
+++ b/docs/plat/mt8188.rst
@@ -0,0 +1,21 @@
+MediaTek 8188
+=============
+
+MediaTek 8188 (MT8188) is a 64-bit ARM SoC introduced by MediaTek in 2022.
+The chip incorporates eight cores - six Cortex-A55 little cores and two Cortex-A78.
+Cortex-A78 can operate at up to 2.6 GHz.
+Cortex-A55 can operate at up to 2.0 GHz.
+
+Boot Sequence
+-------------
+
+::
+
+    Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
+
+    How to Build
+    ------------
+
+    .. code:: shell
+
+           make CROSS_COMPILE=aarch64-linux-gnu- LD=aarch64-linux-gnu-gcc PLAT=mt8188 DEBUG=1 COREBOOT=1
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 9f0331a..6ef2256 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,18 +8,29 @@
 #include <errno.h>
 #include <stddef.h>
 
-#include <platform_def.h>
-
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <drivers/nand.h>
 #include <lib/utils.h>
 
+#include <platform_def.h>
+
 /*
  * Define a single nand_device used by specific NAND frameworks.
  */
 static struct nand_device nand_dev;
-static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE];
+
+#pragma weak plat_get_scratch_buffer
+void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size)
+{
+	static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE];
+
+	assert(buffer_addr != NULL);
+	assert(buf_size != NULL);
+
+	*buffer_addr = (void *)scratch_buff;
+	*buf_size = sizeof(scratch_buff);
+}
 
 int nand_read(unsigned int offset, uintptr_t buffer, size_t length,
 	      size_t *length_read)
@@ -34,6 +45,12 @@
 	unsigned int bytes_read;
 	int is_bad;
 	int ret;
+	uint8_t *scratch_buff;
+	size_t scratch_buff_size;
+
+	plat_get_scratch_buffer((void **)&scratch_buff, &scratch_buff_size);
+
+	assert(scratch_buff != NULL);
 
 	VERBOSE("Block %u - %u, page_start %u, nb %u, length %zu, offset %u\n",
 		block, end_block, page_start, nb_pages, length, offset);
@@ -41,7 +58,7 @@
 	*length_read = 0UL;
 
 	if (((start_offset != 0U) || (length % nand_dev.page_size) != 0U) &&
-	    (sizeof(scratch_buff) < nand_dev.page_size)) {
+	    (scratch_buff_size < nand_dev.page_size)) {
 		return -EINVAL;
 	}
 
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 935bf77..694f1f0 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -107,15 +107,23 @@
 
 static inline int32_t validate_el3_interrupt_rm(uint32_t x)
 {
-#if EL3_EXCEPTION_HANDLING
+#if defined (EL3_EXCEPTION_HANDLING) && !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1))
 	/*
 	 * With EL3 exception handling, EL3 interrupts are always routed to EL3
-	 * from both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is
-	 * the only valid routing model.
+	 * from both Secure and Non-secure, when the SPMC does not live in S-EL2.
+	 * Therefore INTR_EL3_VALID_RM1 is the only valid routing model.
 	 */
 	if (x == INTR_EL3_VALID_RM1)
 		return 0;
 #else
+	/*
+	 * When EL3_EXCEPTION_HANDLING is not defined both routing modes are
+	 * valid. This is the most common case. The exception to this rule is
+	 * when EL3_EXCEPTION_HANDLING is defined but also when the SPMC lives
+	 * at S-EL2. In this case, Group0 Interrupts are trapped to the SPMC
+	 * when running in S-EL0 and S-EL1. The SPMC may handle the interrupt
+	 * itself, delegate it to an SP or forward to EL3 for handling.
+	 */
 	if ((x == INTR_EL3_VALID_RM0) || (x == INTR_EL3_VALID_RM1))
 		return 0;
 #endif
diff --git a/include/drivers/nand.h b/include/drivers/nand.h
index 1b78ad4..5e5607c 100644
--- a/include/drivers/nand.h
+++ b/include/drivers/nand.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,6 +33,8 @@
 			     uintptr_t buffer);
 };
 
+void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size);
+
 /*
  * Read bytes from NAND device
  *
diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h
index 0d00722..423f0db 100644
--- a/include/lib/libc/cdefs.h
+++ b/include/lib/libc/cdefs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,6 +12,7 @@
 #define __packed	__attribute__((__packed__))
 #define __used		__attribute__((__used__))
 #define __unused	__attribute__((__unused__))
+#define __maybe_unused	__attribute__((__unused__))
 #define __aligned(x)	__attribute__((__aligned__(x)))
 #define __section(x)	__attribute__((__section__(x)))
 #if RECLAIM_INIT_CODE
diff --git a/lib/cpus/aarch64/cortex_makalu.S b/lib/cpus/aarch64/cortex_a715.S
similarity index 100%
rename from lib/cpus/aarch64/cortex_makalu.S
rename to lib/cpus/aarch64/cortex_a715.S
diff --git a/lib/cpus/aarch64/cortex_makalu_elp_arm.S b/lib/cpus/aarch64/cortex_x3.S
similarity index 100%
rename from lib/cpus/aarch64/cortex_makalu_elp_arm.S
rename to lib/cpus/aarch64/cortex_x3.S
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 084532c..a14a0d8 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021, Arm Limited. All rights reserved.
+# Copyright (c) 2021-2022, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -71,9 +71,9 @@
 				lib/cpus/aarch64/cortex_a65.S		\
 				lib/cpus/aarch64/cortex_a65ae.S		\
 				lib/cpus/aarch64/cortex_a510.S		\
-				lib/cpus/aarch64/cortex_a710.S	\
-				lib/cpus/aarch64/cortex_makalu.S	\
-				lib/cpus/aarch64/cortex_makalu_elp_arm.S \
+				lib/cpus/aarch64/cortex_a710.S		\
+				lib/cpus/aarch64/cortex_a715.S		\
+				lib/cpus/aarch64/cortex_x3.S 		\
 				lib/cpus/aarch64/cortex_a78c.S
 
 # AArch64/AArch32 cores
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index a7e27e8..2539712 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -135,9 +135,9 @@
 					lib/cpus/aarch64/neoverse_demeter.S	\
 					lib/cpus/aarch64/cortex_a78_ae.S	\
 					lib/cpus/aarch64/cortex_a510.S		\
-					lib/cpus/aarch64/cortex_a710.S	\
-					lib/cpus/aarch64/cortex_makalu.S	\
-					lib/cpus/aarch64/cortex_makalu_elp_arm.S \
+					lib/cpus/aarch64/cortex_a710.S		\
+					lib/cpus/aarch64/cortex_a715.S		\
+					lib/cpus/aarch64/cortex_x3.S 		\
 					lib/cpus/aarch64/cortex_a65.S		\
 					lib/cpus/aarch64/cortex_a65ae.S		\
 					lib/cpus/aarch64/cortex_a78c.S		\
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index e6c1c7c..1a1bc56 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -73,8 +73,8 @@
 # CPU libraries for TARGET_PLATFORM=1
 ifeq (${TARGET_PLATFORM}, 1)
 TC_CPU_SOURCES	+=	lib/cpus/aarch64/cortex_a510.S \
-			lib/cpus/aarch64/cortex_makalu.S \
-			lib/cpus/aarch64/cortex_makalu_elp_arm.S
+			lib/cpus/aarch64/cortex_a715.S \
+			lib/cpus/aarch64/cortex_x3.S
 endif
 
 # CPU libraries for TARGET_PLATFORM=2
diff --git a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
index 78360b0..18f1a37 100644
--- a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
+++ b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
@@ -20,71 +20,72 @@
 static bl_mem_params_node_t bl2_mem_params_descs[] = {
 #ifdef SCP_BL2_BASE
 	/* Fill SCP_BL2 related information if it exists */
-    {
-	    .image_id = SCP_BL2_IMAGE_ID,
+	{
+		.image_id = SCP_BL2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = SCP_BL2_BASE,
-	    .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = SCP_BL2_BASE,
+		.image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 #endif /* SCP_BL2_BASE */
 
 	/* Fill BL32 related information */
-    {
-	    .image_id = BL32_IMAGE_ID,
+	{
+		.image_id = BL32_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = BL32_BASE,
-	    .ep_info.spsr = SPSR_MODE32(MODE32_mon, SPSR_T_ARM,
-		    SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL32_BASE,
+		.ep_info.spsr = SPSR_MODE32(MODE32_mon, SPSR_T_ARM,
+			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = BL33_IMAGE_ID,
-    },
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
 	/* Fill HW_CONFIG related information if it exists */
-    {
-	    .image_id = HW_CONFIG_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE),
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+	{
+		.image_id = HW_CONFIG_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t,
+			NON_SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 	/* Fill BL33 related information */
-    {
-	    .image_id = BL33_IMAGE_ID,
+	{
+		.image_id = BL33_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
 #ifdef PRELOADED_BL33_BASE
-	    .ep_info.pc = PRELOADED_BL33_BASE,
+		.ep_info.pc = PRELOADED_BL33_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 #else
-	    .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
+		.ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
-	    .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
-		    - PLAT_ARM_NS_IMAGE_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+		.image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+			- PLAT_ARM_NS_IMAGE_BASE,
 #endif /* PRELOADED_BL33_BASE */
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    }
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
 };
 
 REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
index 0666e57..3d7b361 100644
--- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
+++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
@@ -20,203 +20,207 @@
 static bl_mem_params_node_t bl2_mem_params_descs[] = {
 #ifdef SCP_BL2_BASE
 	/* Fill SCP_BL2 related information if it exists */
-    {
-	    .image_id = SCP_BL2_IMAGE_ID,
+	{
+		.image_id = SCP_BL2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = SCP_BL2_BASE,
-	    .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = SCP_BL2_BASE,
+		.image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 #endif /* SCP_BL2_BASE */
 
 #ifdef EL3_PAYLOAD_BASE
 	/* Fill EL3 payload related information (BL31 is EL3 payload)*/
-    {
-	    .image_id = BL31_IMAGE_ID,
+	{
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = EL3_PAYLOAD_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = EL3_PAYLOAD_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t,
-		    IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t,
+			IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 #else /* EL3_PAYLOAD_BASE */
 
 	/* Fill BL31 related information */
-    {
-	    .image_id = BL31_IMAGE_ID,
+	{
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = BL31_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 #if DEBUG
-	    .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
+		.ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
 #endif
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = BL31_BASE,
-	    .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
 
 # if defined(BL32_BASE)
-	    .next_handoff_image_id = BL32_IMAGE_ID,
+		.next_handoff_image_id = BL32_IMAGE_ID,
 # elif ENABLE_RME
-	    .next_handoff_image_id = RMM_IMAGE_ID,
+		.next_handoff_image_id = RMM_IMAGE_ID,
 # else
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 # endif
-    },
+	},
 	/* Fill HW_CONFIG related information */
-    {
-	    .image_id = HW_CONFIG_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE),
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+	{
+		.image_id = HW_CONFIG_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t,
+			NON_SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 	/* Fill SOC_FW_CONFIG related information */
-    {
-	    .image_id = SOC_FW_CONFIG_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+	{
+		.image_id = SOC_FW_CONFIG_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 # if ENABLE_RME
 	/* Fill RMM related information */
-    {
-	    .image_id = RMM_IMAGE_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, EP_REALM | EXECUTABLE),
-	    .ep_info.pc = RMM_BASE,
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = RMM_BASE,
-	    .image_info.image_max_size = RMM_LIMIT - RMM_BASE,
-	    .next_handoff_image_id = BL33_IMAGE_ID,
-    },
+	{
+		.image_id = RMM_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, EP_REALM | EXECUTABLE),
+		.ep_info.pc = RMM_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = RMM_BASE,
+		.image_info.image_max_size = RMM_LIMIT - RMM_BASE,
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
 # endif
 
 # ifdef BL32_BASE
 	/* Fill BL32 related information */
-    {
-	    .image_id = BL32_IMAGE_ID,
+	{
+		.image_id = BL32_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
-	    .ep_info.pc = BL32_BASE,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
 # if ENABLE_RME
-	    .next_handoff_image_id = RMM_IMAGE_ID,
+		.next_handoff_image_id = RMM_IMAGE_ID,
 # else
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 # endif
-    },
+	},
 
 	/*
 	 * Fill BL32 external 1 related information.
-	 * A typical use for extra1 image is with OP-TEE where it is the pager image.
+	 * A typical use for extra1 image is with OP-TEE where it is the pager
+	 * image.
 	 */
-    {
-	    .image_id = BL32_EXTRA1_IMAGE_ID,
+	{
+		.image_id = BL32_EXTRA1_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 	/*
 	 * Fill BL32 external 2 related information.
-	 * A typical use for extra2 image is with OP-TEE where it is the paged image.
+	 * A typical use for extra2 image is with OP-TEE where it is the paged
+	 * image.
 	 */
-    {
-	    .image_id = BL32_EXTRA2_IMAGE_ID,
+	{
+		.image_id = BL32_EXTRA2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 #ifdef SPD_opteed
-	    .image_info.image_base = ARM_OPTEE_PAGEABLE_LOAD_BASE,
-	    .image_info.image_max_size = ARM_OPTEE_PAGEABLE_LOAD_SIZE,
+		.image_info.image_base = ARM_OPTEE_PAGEABLE_LOAD_BASE,
+		.image_info.image_max_size = ARM_OPTEE_PAGEABLE_LOAD_SIZE,
 #endif
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 	/* Fill TOS_FW_CONFIG related information */
-    {
-	    .image_id = TOS_FW_CONFIG_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+	{
+		.image_id = TOS_FW_CONFIG_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 # endif /* BL32_BASE */
 
 	/* Fill BL33 related information */
-    {
-	    .image_id = BL33_IMAGE_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+	{
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
 # ifdef PRELOADED_BL33_BASE
-	    .ep_info.pc = PRELOADED_BL33_BASE,
+		.ep_info.pc = PRELOADED_BL33_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 # else
-	    .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
+		.ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
-	    .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
-		    - PLAT_ARM_NS_IMAGE_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+		.image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+			- PLAT_ARM_NS_IMAGE_BASE,
 # endif /* PRELOADED_BL33_BASE */
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 	/* Fill NT_FW_CONFIG related information */
-    {
-	    .image_id = NT_FW_CONFIG_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE),
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    }
+	{
+		.image_id = NT_FW_CONFIG_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t,
+			NON_SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
 #endif /* EL3_PAYLOAD_BASE */
 };
 
diff --git a/plat/brcm/common/brcm_bl2_mem_params_desc.c b/plat/brcm/common/brcm_bl2_mem_params_desc.c
index f711354..aed99d9 100644
--- a/plat/brcm/common/brcm_bl2_mem_params_desc.c
+++ b/plat/brcm/common/brcm_bl2_mem_params_desc.c
@@ -22,84 +22,84 @@
 #ifdef SCP_BL2_BASE
 	/* Fill SCP_BL2 related information if it exists */
 	{
-	    .image_id = SCP_BL2_IMAGE_ID,
+		.image_id = SCP_BL2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = SCP_BL2_BASE,
-	    .image_info.image_max_size = PLAT_MAX_SCP_BL2_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = SCP_BL2_BASE,
+		.image_info.image_max_size = PLAT_MAX_SCP_BL2_SIZE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 #endif /* SCP_BL2_BASE */
 
 	/* Fill BL31 related information */
 	{
-	    .image_id = BL31_IMAGE_ID,
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = BL31_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 #if DEBUG
-	    .ep_info.args.arg3 = BRCM_BL31_PLAT_PARAM_VAL,
+		.ep_info.args.arg3 = BRCM_BL31_PLAT_PARAM_VAL,
 #endif
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = BL31_BASE,
-	    .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
 
 #ifdef BL32_BASE
-	    .next_handoff_image_id = BL32_IMAGE_ID,
+		.next_handoff_image_id = BL32_IMAGE_ID,
 #else
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 #endif
 	},
 
 #ifdef BL32_BASE
 	/* Fill BL32 related information */
 	{
-	    .image_id = BL32_IMAGE_ID,
+		.image_id = BL32_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
-	    .ep_info.pc = BL32_BASE,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 	},
 #endif /* BL32_BASE */
 
 	/* Fill BL33 related information */
 	{
-	    .image_id = BL33_IMAGE_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
 #ifdef PRELOADED_BL33_BASE
-	    .ep_info.pc = PRELOADED_BL33_BASE,
+		.ep_info.pc = PRELOADED_BL33_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 #else
-	    .ep_info.pc = PLAT_BRCM_NS_IMAGE_OFFSET,
+		.ep_info.pc = PLAT_BRCM_NS_IMAGE_OFFSET,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = PLAT_BRCM_NS_IMAGE_OFFSET,
-	    .image_info.image_max_size = BRCM_DRAM1_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = PLAT_BRCM_NS_IMAGE_OFFSET,
+		.image_info.image_max_size = BRCM_DRAM1_SIZE,
 #endif /* PRELOADED_BL33_BASE */
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	}
 };
 
diff --git a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
index 4e013a0..d029703 100644
--- a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
+++ b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
@@ -21,144 +21,146 @@
 static bl_mem_params_node_t bl2_mem_params_descs[] = {
 #ifdef SCP_BL2_BASE
 	/* Fill SCP_BL2 related information if it exists */
-    {
-	    .image_id = SCP_BL2_IMAGE_ID,
+	{
+		.image_id = SCP_BL2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = SCP_BL2_BASE,
-	    .image_info.image_max_size = SCP_BL2_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = SCP_BL2_BASE,
+		.image_info.image_max_size = SCP_BL2_SIZE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 #endif /* SCP_BL2_BASE */
 
 #ifdef EL3_PAYLOAD_BASE
 	/* Fill EL3 payload related information (BL31 is EL3 payload)*/
-    {
-	    .image_id = BL31_IMAGE_ID,
+	{
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = EL3_PAYLOAD_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = EL3_PAYLOAD_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t,
-		    IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t,
+			IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 #else /* EL3_PAYLOAD_BASE */
 
 	/* Fill BL31 related information */
-    {
-	    .image_id = BL31_IMAGE_ID,
+	{
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = BL31_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 #if DEBUG
-	    .ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL,
+		.ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL,
 #endif
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = BL31_BASE,
-	    .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
 
 # ifdef BL32_BASE
-	    .next_handoff_image_id = BL32_IMAGE_ID,
+		.next_handoff_image_id = BL32_IMAGE_ID,
 # else
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 # endif
-    },
+	},
 
 # ifdef BL32_BASE
 	/* Fill BL32 related information */
-    {
-	    .image_id = BL32_IMAGE_ID,
+	{
+		.image_id = BL32_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
-	    .ep_info.pc = BL32_BASE,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = BL33_IMAGE_ID,
-    },
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
 
 	/*
 	 * Fill BL32 external 1 related information.
-	 * A typical use for extra1 image is with OP-TEE where it is the pager image.
+	 * A typical use for extra1 image is with OP-TEE where it is the pager
+	 * image.
 	 */
-    {
-	    .image_id = BL32_EXTRA1_IMAGE_ID,
+	{
+		.image_id = BL32_EXTRA1_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 	/*
 	 * Fill BL32 external 2 related information.
-	 * A typical use for extra2 image is with OP-TEE where it is the paged image.
+	 * A typical use for extra2 image is with OP-TEE where it is the paged
+	 * image.
 	 */
-    {
-	    .image_id = BL32_EXTRA2_IMAGE_ID,
+	{
+		.image_id = BL32_EXTRA2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 #ifdef SPD_opteed
-	    .image_info.image_base = HIKEY_OPTEE_PAGEABLE_LOAD_BASE,
-	    .image_info.image_max_size = HIKEY_OPTEE_PAGEABLE_LOAD_SIZE,
+		.image_info.image_base = HIKEY_OPTEE_PAGEABLE_LOAD_BASE,
+		.image_info.image_max_size = HIKEY_OPTEE_PAGEABLE_LOAD_SIZE,
 #endif
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 # endif /* BL32_BASE */
 
 	/* Fill BL33 related information */
-    {
-	    .image_id = BL33_IMAGE_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+	{
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
 # ifdef PRELOADED_BL33_BASE
-	    .ep_info.pc = PRELOADED_BL33_BASE,
+		.ep_info.pc = PRELOADED_BL33_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 # else
-	    .ep_info.pc = HIKEY_NS_IMAGE_OFFSET,
+		.ep_info.pc = HIKEY_NS_IMAGE_OFFSET,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = HIKEY_NS_IMAGE_OFFSET,
-	    .image_info.image_max_size = 0x200000 /* 2MB */,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = HIKEY_NS_IMAGE_OFFSET,
+		.image_info.image_max_size = 0x200000 /* 2MB */,
 # endif /* PRELOADED_BL33_BASE */
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    }
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
 #endif /* EL3_PAYLOAD_BASE */
 };
 
diff --git a/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c b/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c
index ba236d2..39a54cb 100644
--- a/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c
+++ b/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c
@@ -21,144 +21,146 @@
 static bl_mem_params_node_t bl2_mem_params_descs[] = {
 #ifdef SCP_BL2_BASE
 	/* Fill SCP_BL2 related information if it exists */
-    {
-	    .image_id = SCP_BL2_IMAGE_ID,
+	{
+		.image_id = SCP_BL2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = SCP_BL2_BASE,
-	    .image_info.image_max_size = SCP_BL2_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = SCP_BL2_BASE,
+		.image_info.image_max_size = SCP_BL2_SIZE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 #endif /* SCP_BL2_BASE */
 
 #ifdef EL3_PAYLOAD_BASE
 	/* Fill EL3 payload related information (BL31 is EL3 payload)*/
-    {
-	    .image_id = BL31_IMAGE_ID,
+	{
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = EL3_PAYLOAD_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = EL3_PAYLOAD_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t,
-		    IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t,
+			IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 #else /* EL3_PAYLOAD_BASE */
 
 	/* Fill BL31 related information */
-    {
-	    .image_id = BL31_IMAGE_ID,
+	{
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = BL31_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 #if DEBUG
-	    .ep_info.args.arg1 = HIKEY960_BL31_PLAT_PARAM_VAL,
+		.ep_info.args.arg1 = HIKEY960_BL31_PLAT_PARAM_VAL,
 #endif
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = BL31_BASE,
-	    .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
 
 # ifdef BL32_BASE
-	    .next_handoff_image_id = BL32_IMAGE_ID,
+		.next_handoff_image_id = BL32_IMAGE_ID,
 # else
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 # endif
-    },
+	},
 
 # ifdef BL32_BASE
 	/* Fill BL32 related information */
-    {
-	    .image_id = BL32_IMAGE_ID,
+	{
+		.image_id = BL32_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
-	    .ep_info.pc = BL32_BASE,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = BL33_IMAGE_ID,
-    },
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
 
 	/*
 	 * Fill BL32 external 1 related information.
-	 * A typical use for extra1 image is with OP-TEE where it is the pager image.
+	 * A typical use for extra1 image is with OP-TEE where it is the pager
+	 * image.
 	 */
-    {
-	    .image_id = BL32_EXTRA1_IMAGE_ID,
+	{
+		.image_id = BL32_EXTRA1_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 	/*
 	 * Fill BL32 external 2 related information.
-	 * A typical use for extra2 image is with OP-TEE where it is the paged image.
+	 * A typical use for extra2 image is with OP-TEE where it is the paged
+	 * image.
 	 */
-    {
-	    .image_id = BL32_EXTRA2_IMAGE_ID,
+	{
+		.image_id = BL32_EXTRA2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 #ifdef SPD_opteed
-	    .image_info.image_base = HIKEY960_OPTEE_PAGEABLE_LOAD_BASE,
-	    .image_info.image_max_size = HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE,
+		.image_info.image_base = HIKEY960_OPTEE_PAGEABLE_LOAD_BASE,
+		.image_info.image_max_size = HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE,
 #endif
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 # endif /* BL32_BASE */
 
 	/* Fill BL33 related information */
-    {
-	    .image_id = BL33_IMAGE_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+	{
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
 # ifdef PRELOADED_BL33_BASE
-	    .ep_info.pc = PRELOADED_BL33_BASE,
+		.ep_info.pc = PRELOADED_BL33_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 # else
-	    .ep_info.pc = NS_BL1U_BASE,
+		.ep_info.pc = NS_BL1U_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = NS_BL1U_BASE,
-	    .image_info.image_max_size = 0x200000 /* 2MB */,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = NS_BL1U_BASE,
+		.image_info.image_max_size = 0x200000 /* 2MB */,
 # endif /* PRELOADED_BL33_BASE */
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    }
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
 #endif /* EL3_PAYLOAD_BASE */
 };
 
diff --git a/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c b/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c
index f683d75..9bda02e 100644
--- a/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c
+++ b/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c
@@ -22,143 +22,145 @@
 #ifdef SCP_BL2_BASE
 	/* Fill SCP_BL2 related information if it exists */
 	{
-	    .image_id = SCP_BL2_IMAGE_ID,
+		.image_id = SCP_BL2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = SCP_BL2_BASE,
-	    .image_info.image_max_size = SCP_BL2_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = SCP_BL2_BASE,
+		.image_info.image_max_size = SCP_BL2_SIZE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 #endif /* SCP_BL2_BASE */
 
 #ifdef EL3_PAYLOAD_BASE
 	/* Fill EL3 payload related information (BL31 is EL3 payload)*/
 	{
-	    .image_id = BL31_IMAGE_ID,
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = EL3_PAYLOAD_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = EL3_PAYLOAD_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t,
-		    IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t,
+			IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 
 #else /* EL3_PAYLOAD_BASE */
 
 	/* Fill BL31 related information */
 	{
-	    .image_id = BL31_IMAGE_ID,
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = BL31_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 #if DEBUG
-	    .ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL,
+		.ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL,
 #endif
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = BL31_BASE,
-	    .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
 
 # ifdef BL32_BASE
-	    .next_handoff_image_id = BL32_IMAGE_ID,
+		.next_handoff_image_id = BL32_IMAGE_ID,
 # else
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 # endif
 	},
 
 # ifdef BL32_BASE
 	/* Fill BL32 related information */
 	{
-	    .image_id = BL32_IMAGE_ID,
+		.image_id = BL32_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
-	    .ep_info.pc = BL32_BASE,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 	},
 
 	/*
 	 * Fill BL32 external 1 related information.
-	 * A typical use for extra1 image is with OP-TEE where it is the pager image.
+	 * A typical use for extra1 image is with OP-TEE where it is the pager
+	 * image.
 	 */
 	{
-	    .image_id = BL32_EXTRA1_IMAGE_ID,
+		.image_id = BL32_EXTRA1_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 
 	/*
 	 * Fill BL32 external 2 related information.
-	 * A typical use for extra2 image is with OP-TEE where it is the paged image.
+	 * A typical use for extra2 image is with OP-TEE where it is the paged
+	 * image.
 	 */
 	{
-	    .image_id = BL32_EXTRA2_IMAGE_ID,
+		.image_id = BL32_EXTRA2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 #ifdef SPD_opteed
-	    .image_info.image_base = POPLAR_OPTEE_PAGEABLE_LOAD_BASE,
-	    .image_info.image_max_size = POPLAR_OPTEE_PAGEABLE_LOAD_SIZE,
+		.image_info.image_base = POPLAR_OPTEE_PAGEABLE_LOAD_BASE,
+		.image_info.image_max_size = POPLAR_OPTEE_PAGEABLE_LOAD_SIZE,
 #endif
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 # endif /* BL32_BASE */
 
 	/* Fill BL33 related information */
 	{
-	    .image_id = BL33_IMAGE_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
 # ifdef PRELOADED_BL33_BASE
-	    .ep_info.pc = PRELOADED_BL33_BASE,
+		.ep_info.pc = PRELOADED_BL33_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 # else
-	    .ep_info.pc = PLAT_POPLAR_NS_IMAGE_OFFSET,
+		.ep_info.pc = PLAT_POPLAR_NS_IMAGE_OFFSET,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = PLAT_POPLAR_NS_IMAGE_OFFSET,
-	    .image_info.image_max_size = DDR_BASE + DDR_SIZE -
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = PLAT_POPLAR_NS_IMAGE_OFFSET,
+		.image_info.image_max_size = DDR_BASE + DDR_SIZE -
 					PLAT_POPLAR_NS_IMAGE_OFFSET,
 # endif /* PRELOADED_BL33_BASE */
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	}
 #endif /* EL3_PAYLOAD_BASE */
 };
diff --git a/plat/intel/soc/common/bl2_plat_mem_params_desc.c b/plat/intel/soc/common/bl2_plat_mem_params_desc.c
index 4f75665..187c53a 100644
--- a/plat/intel/soc/common/bl2_plat_mem_params_desc.c
+++ b/plat/intel/soc/common/bl2_plat_mem_params_desc.c
@@ -22,58 +22,58 @@
 #ifdef SCP_BL2_BASE
 	/* Fill SCP_BL2 related information if it exists */
 	{
-	    .image_id = SCP_BL2_IMAGE_ID,
+		.image_id = SCP_BL2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = SCP_BL2_BASE,
-	    .image_info.image_max_size = SCP_BL2_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = SCP_BL2_BASE,
+		.image_info.image_max_size = SCP_BL2_SIZE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 #endif /* SCP_BL2_BASE */
 
 #ifdef EL3_PAYLOAD_BASE
 	/* Fill EL3 payload related information (BL31 is EL3 payload)*/
 	{
-	    .image_id = BL31_IMAGE_ID,
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = EL3_PAYLOAD_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = EL3_PAYLOAD_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t,
-		    IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t,
+			IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 
 #else /* EL3_PAYLOAD_BASE */
 
 	/* Fill BL31 related information */
 	{
-	    .image_id = BL31_IMAGE_ID,
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = BL31_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = BL31_BASE,
-	    .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
 
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 	},
 #endif /* EL3_PAYLOAD_BASE */
 
diff --git a/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c b/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c
index 8d909dc..6c55858 100644
--- a/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c
+++ b/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c
@@ -22,84 +22,84 @@
 static bl_mem_params_node_t bl2_mem_params_descs[] = {
 #ifdef SCP_BL2_BASE
 	/* Fill SCP_BL2 related information if it exists */
-    {
-	    .image_id = SCP_BL2_IMAGE_ID,
+	{
+		.image_id = SCP_BL2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = SCP_BL2_BASE,
-	    .image_info.image_max_size = SCP_BL2_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = SCP_BL2_BASE,
+		.image_info.image_max_size = SCP_BL2_SIZE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 #endif /* SCP_BL2_BASE */
 
 #ifdef EL3_PAYLOAD_BASE
 	/* Fill EL3 payload related information (BL31 is EL3 payload)*/
-    {
-	    .image_id = BL31_IMAGE_ID,
+	{
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = EL3_PAYLOAD_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = EL3_PAYLOAD_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t,
-		    IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t,
+			IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    },
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	},
 
 #else /* EL3_PAYLOAD_BASE */
 
 	/* Fill BL31 related information */
-    {
-	    .image_id = BL31_IMAGE_ID,
+	{
+		.image_id = BL31_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t,
-		    SECURE | EXECUTABLE | EP_FIRST_EXE),
-	    .ep_info.pc = BL31_BASE,
-	    .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-		    DISABLE_ALL_EXCEPTIONS),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t,
+			SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.pc = BL31_BASE,
+		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
 #if DEBUG
-	    .ep_info.args.arg3 = MARVELL_BL31_PLAT_PARAM_VAL,
+		.ep_info.args.arg3 = MARVELL_BL31_PLAT_PARAM_VAL,
 #endif
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-	    .image_info.image_base = BL31_BASE,
-	    .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_base = BL31_BASE,
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
 
 # ifdef BL32_BASE
-	    .next_handoff_image_id = BL32_IMAGE_ID,
+		.next_handoff_image_id = BL32_IMAGE_ID,
 # else
-	    .next_handoff_image_id = BL33_IMAGE_ID,
+		.next_handoff_image_id = BL33_IMAGE_ID,
 # endif
-    },
+	},
 
 # ifdef BL32_BASE
 	/* Fill BL32 related information */
-    {
-	    .image_id = BL32_IMAGE_ID,
+	{
+		.image_id = BL32_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
-	    .ep_info.pc = BL32_BASE,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = BL33_IMAGE_ID,
-    },
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
 
 	/*
 	 * Fill BL32 external 1 related information.
@@ -107,17 +107,17 @@
 	 * where it is the pager image.
 	 */
 	{
-	    .image_id = BL32_EXTRA1_IMAGE_ID,
+		.image_id = BL32_EXTRA1_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-	    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+		VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
-	    .image_info.image_base = BL32_BASE,
-	    .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		.image_info.image_base = BL32_BASE,
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 
 	/*
@@ -126,42 +126,42 @@
 	 * where it is the paged image.
 	 */
 	{
-	    .image_id = BL32_EXTRA2_IMAGE_ID,
+		.image_id = BL32_EXTRA2_IMAGE_ID,
 
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 #ifdef SPD_opteed
-	    .image_info.image_base = MARVELL_OPTEE_PAGEABLE_LOAD_BASE,
-	    .image_info.image_max_size = MARVELL_OPTEE_PAGEABLE_LOAD_SIZE,
+		.image_info.image_base = MARVELL_OPTEE_PAGEABLE_LOAD_BASE,
+		.image_info.image_max_size = MARVELL_OPTEE_PAGEABLE_LOAD_SIZE,
 #endif
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
+		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 # endif /* BL32_BASE */
 
 	/* Fill BL33 related information */
-    {
-	    .image_id = BL33_IMAGE_ID,
-	    SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-		    VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+	{
+		.image_id = BL33_IMAGE_ID,
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
 # ifdef PRELOADED_BL33_BASE
-	    .ep_info.pc = PRELOADED_BL33_BASE,
+		.ep_info.pc = PRELOADED_BL33_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
 # else
-	    .ep_info.pc = MARVELL_DRAM_BASE,
+		.ep_info.pc = MARVELL_DRAM_BASE,
 
-	    SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-		    VERSION_2, image_info_t, 0),
-	    .image_info.image_base = MARVELL_DRAM_BASE,
-	    .image_info.image_max_size = MARVELL_DRAM_SIZE,
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+			VERSION_2, image_info_t, 0),
+		.image_info.image_base = MARVELL_DRAM_BASE,
+		.image_info.image_max_size = MARVELL_DRAM_SIZE,
 # endif /* PRELOADED_BL33_BASE */
 
-	    .next_handoff_image_id = INVALID_IMAGE_ID,
-    }
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
 #endif /* EL3_PAYLOAD_BASE */
 };
 
diff --git a/plat/mediatek/build_helpers/mtk_build_helpers.mk b/plat/mediatek/build_helpers/mtk_build_helpers.mk
index a5a4c3e..fc3876e 100644
--- a/plat/mediatek/build_helpers/mtk_build_helpers.mk
+++ b/plat/mediatek/build_helpers/mtk_build_helpers.mk
@@ -116,9 +116,13 @@
 # Include MTK configuration files
 
 # MTK makefile variables
+ifeq (${COREBOOT},1)
+MTK_COMMON_CFG := $(MTK_PLAT)/common/coreboot_config.mk
+else
+MTK_COMMON_CFG := $(MTK_PLAT)/common/common_config.mk
+endif
 MTK_PLAT      := plat/mediatek
 MTK_PLAT_SOC  := ${MTK_PLAT}/${MTK_SOC}
-MTK_COMMON_CFG := $(MTK_PLAT)/common/common_config.mk
 MTK_PLAT_CFG := $(MTK_PLAT_SOC)/plat_config.mk
 MTK_PROJECT_CFG := $(MTK_PLAT)/project/$(PLAT)/project_config.mk
 MTK_OPTIONS := $(MTK_PLAT)/build_helpers/options.mk
diff --git a/plat/mediatek/common/coreboot_config.mk b/plat/mediatek/common/coreboot_config.mk
new file mode 100644
index 0000000..59d18e8
--- /dev/null
+++ b/plat/mediatek/common/coreboot_config.mk
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# indicate the reset vector address can be programmed
+PROGRAMMABLE_RESET_ADDRESS := 1
+COLD_BOOT_SINGLE_CPU := 1
+# Build flag to include AArch32 registers in cpu context save and restore during
+# world switch. This flag must be set to 0 for AArch64-only platforms.
+CTX_INCLUDE_AARCH32_REGS := 0
+PLAT_XLAT_TABLES_DYNAMIC := 1
+
+VENDOR_EXTEND_PUBEVENT_ENABLE := 1
diff --git a/plat/mediatek/common/custom/oem_svc.c b/plat/mediatek/common/custom/oem_svc.c
deleted file mode 100644
index 27ee6aa..0000000
--- a/plat/mediatek/common/custom/oem_svc.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <stdint.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <plat/common/platform.h>
-#include <tools_share/uuid.h>
-
-#include <oem_svc.h>
-
-/* OEM Service UUID */
-DEFINE_SVC_UUID2(oem_svc_uid,
-	0xd0ad43b9, 0x9b06, 0xe411, 0x91, 0x91,
-	0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66);
-
-/* Setup OEM Services */
-static int32_t oem_svc_setup(void)
-{
-	/*
-	 * Invoke related module setup from here
-	 */
-
-	return 0;
-}
-
-/*******************************************************************************
- * OEM top level handler for servicing SMCs.
- ******************************************************************************/
-uintptr_t oem_smc_handler(uint32_t smc_fid,
-			u_register_t x1,
-			u_register_t x2,
-			u_register_t x3,
-			u_register_t x4,
-			void *cookie,
-			void *handle,
-			u_register_t flags)
-{
-	WARN("Unimplemented OEM Call: 0x%x\n", smc_fid);
-	SMC_RET1(handle, SMC_UNK);
-}
-
-/*
- * Top-level OEM Service SMC handler. This handler will in turn dispatch
- * calls to related SMC handler
- */
-uintptr_t oem_svc_smc_handler(uint32_t smc_fid,
-			 u_register_t x1,
-			 u_register_t x2,
-			 u_register_t x3,
-			 u_register_t x4,
-			 void *cookie,
-			 void *handle,
-			 u_register_t flags)
-{
-	/*
-	 * Dispatch OEM calls to OEM Common handler and return its return value
-	 */
-	if (is_oem_fid(smc_fid)) {
-		return oem_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
-					handle, flags);
-	}
-
-	switch (smc_fid) {
-	case OEM_SVC_CALL_COUNT:
-		/*
-		 * Return the number of OEM Service Calls.
-		 */
-		SMC_RET1(handle, OEM_SVC_NUM_CALLS);
-
-	case OEM_SVC_UID:
-		/* Return UID to the caller */
-		SMC_UUID_RET(handle, oem_svc_uid);
-
-	case OEM_SVC_VERSION:
-		/* Return the version of current implementation */
-		SMC_RET2(handle, OEM_VERSION_MAJOR, OEM_VERSION_MINOR);
-
-	default:
-		WARN("Unimplemented OEM Service Call: 0x%x\n", smc_fid);
-		SMC_RET1(handle, SMC_UNK);
-	}
-}
-
-/* Register OEM Service Calls as runtime service */
-DECLARE_RT_SVC(
-		oem_svc,
-		OEN_OEM_START,
-		OEN_OEM_END,
-		SMC_TYPE_FAST,
-		oem_svc_setup,
-		oem_svc_smc_handler
-);
diff --git a/plat/mediatek/common/custom/oem_svc.h b/plat/mediatek/common/custom/oem_svc.h
deleted file mode 100644
index 76f7c24..0000000
--- a/plat/mediatek/common/custom/oem_svc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef OEM_SVC_H
-#define OEM_SVC_H
-
-/*******************************************************************************
- * Defines for runtime services func ids
- ******************************************************************************/
-/*
- * Number of OEM calls (above) implemented.
- */
-#define OEM_SVC_NUM_CALLS		3
-
-/*******************************************************************************
- * Defines for OEM Service queries
- ******************************************************************************/
-/* 0x83000000 - 0x8300FEFF is OEM service calls */
-#define OEM_SVC_CALL_COUNT		0x8300ff00
-#define OEM_SVC_UID			0x8300ff01
-/* 0x8300ff02 is reserved */
-#define OEM_SVC_VERSION			0x8300ff03
-/* 0x8300ff04 - 0x8300FFFF is reserved for future expansion */
-
-/* OEM Service Calls version numbers */
-#define OEM_VERSION_MAJOR		0x0
-#define OEM_VERSION_MINOR		0x1
-
-/* The macros below are used to identify OEM calls from the SMC function ID */
-/* SMC32 ID range from 0x83000000 to 0x83000FFF */
-/* SMC64 ID range from 0xC3000000 to 0xC3000FFF */
-#define OEM_FID_MASK			0xf000u
-#define OEM_FID_VALUE			0u
-#define is_oem_fid(_fid) \
-	(((_fid) & OEM_FID_MASK) == OEM_FID_VALUE)
-
-#define OEM_SVC_E_SUCCESS		0
-#define OEM_SVC_E_NOT_SUPPORTED		-1
-#define OEM_SVC_E_INVALID_PARAMS	-2
-
-#endif /* OEM_SVC_H */
diff --git a/plat/mediatek/common/mtk_bl31_setup.c b/plat/mediatek/common/mtk_bl31_setup.c
index 46f7a63..79ab29d 100644
--- a/plat/mediatek/common/mtk_bl31_setup.c
+++ b/plat/mediatek/common/mtk_bl31_setup.c
@@ -15,6 +15,14 @@
 #endif
 #include <plat/common/platform.h>
 
+#if COREBOOT
+#include <common/desc_image_load.h>
+
+#include <drivers/ti/uart/uart_16550.h>
+#include <lib/coreboot.h>
+#include <plat_params.h>
+#endif
+
 /* MTK headers */
 #if MTK_SIP_KERNEL_BOOT_ENABLE
 #include <cold_boot.h>
@@ -24,6 +32,32 @@
 
 IMPORT_SYM(uintptr_t, __RW_START__, RW_START);
 IMPORT_SYM(uintptr_t, __DATA_START__, DATA_START);
+
+#if COREBOOT
+static entry_point_info_t bl32_ep_info;
+static entry_point_info_t bl33_ep_info;
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image for
+ * the security state specified. BL33 corresponds to the non-secure image type
+ * while BL32 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+	entry_point_info_t *next_image_info;
+
+	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
+
+	/* None of the images on this platform can have 0x0 as the entrypoint */
+	if (next_image_info->pc) {
+		return next_image_info;
+	} else {
+		return NULL;
+	}
+}
+#else
 #ifndef MTK_BL31_AS_BL2
 static struct mtk_bl31_fw_config bl31_fw_config;
 #else
@@ -55,7 +89,7 @@
 	}
 	return arg;
 }
-
+#endif
 /*****************************************************************************
  * Perform the very early platform specific architectural setup shared between
  * ARM standard platforms. This only does basic initialization. Later
@@ -67,6 +101,18 @@
 				u_register_t hw_config, u_register_t plat_params_from_bl2)
 
 {
+#if COREBOOT
+	static console_t console;
+
+	params_early_setup(soc_fw_config);
+	if (coreboot_serial.type) {
+		console_16550_register(coreboot_serial.baseaddr,
+				       coreboot_serial.input_hertz,
+				       coreboot_serial.baud,
+				       &console);
+	}
+	bl31_params_parse_helper(from_bl2, &bl32_ep_info, &bl33_ep_info);
+#else
 	struct mtk_bl_param_t *p_mtk_bl_param = (struct mtk_bl_param_t *)from_bl2;
 
 	if (p_mtk_bl_param == NULL) {
@@ -78,6 +124,7 @@
 	bl31_fw_config.soc_fw_config = (void *)soc_fw_config;
 	bl31_fw_config.hw_config = (void *)hw_config;
 	bl31_fw_config.reserved = (void *)plat_params_from_bl2;
+#endif
 
 	INFO("MTK BL31 start\n");
 	/* Init delay function */
diff --git a/plat/mediatek/common/mtk_cirq.c b/plat/mediatek/drivers/cirq/mt_cirq.c
similarity index 98%
rename from plat/mediatek/common/mtk_cirq.c
rename to plat/mediatek/drivers/cirq/mt_cirq.c
index 9cf7144..60534a2 100644
--- a/plat/mediatek/common/mtk_cirq.c
+++ b/plat/mediatek/drivers/cirq/mt_cirq.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,8 +9,8 @@
 #include <drivers/arm/gic_common.h>
 #include <lib/mmio.h>
 
+#include <mt_cirq.h>
 #include <mt_gic_v3.h>
-#include <mtk_cirq.h>
 
 static struct cirq_events cirq_all_events = {
 	.spi_start = CIRQ_SPI_START,
diff --git a/plat/mediatek/common/mtk_cirq.h b/plat/mediatek/drivers/cirq/mt_cirq.h
similarity index 97%
rename from plat/mediatek/common/mtk_cirq.h
rename to plat/mediatek/drivers/cirq/mt_cirq.h
index 6e63bb8..cb96295 100644
--- a/plat/mediatek/common/mtk_cirq.h
+++ b/plat/mediatek/drivers/cirq/mt_cirq.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/drivers/cirq/rules.mk b/plat/mediatek/drivers/cirq/rules.mk
new file mode 100644
index 0000000..710eae0
--- /dev/null
+++ b/plat/mediatek/drivers/cirq/rules.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := cirq
+LOCAL_SRCS-y := $(LOCAL_DIR)/mt_cirq.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.c b/plat/mediatek/drivers/dp/mt_dp.c
similarity index 76%
rename from plat/mediatek/mt8195/drivers/dp/mt_dp.c
rename to plat/mediatek/drivers/dp/mt_dp.c
index 5930cd5..8aa246f 100644
--- a/plat/mediatek/mt8195/drivers/dp/mt_dp.c
+++ b/plat/mediatek/drivers/dp/mt_dp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,7 +15,7 @@
 static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset,
 				uint32_t value, uint32_t mask)
 {
-	uint32_t reg = (is_edp != 0U) ? eDP_SEC_BASE : DP_SEC_BASE;
+	uint32_t reg = (is_edp != 0U) ? EDP_SEC_BASE : DP_SEC_BASE;
 
 	mmio_clrsetbits_32(reg + offset, mask, value);
 
@@ -53,7 +53,7 @@
 
 	if (ret == MTK_SIP_E_SUCCESS) {
 		regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK |
-				VIDEO_MUTE_SW_SECURE_FLDMASK);
+			  VIDEO_MUTE_SW_SECURE_FLDMASK);
 		if (para > 0U) {
 			fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK;
 		} else {
@@ -67,3 +67,13 @@
 
 	return ret;
 }
+
+u_register_t mtk_dp_sip_handler(u_register_t x1, u_register_t x2,
+				u_register_t x3, u_register_t x4,
+				void *handle, struct smccc_res *smccc_ret)
+{
+	uint32_t ret_val;
+
+	return dp_secure_handler(x1, x2, &ret_val);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_DP_CONTROL, mtk_dp_sip_handler);
diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.h b/plat/mediatek/drivers/dp/mt_dp.h
similarity index 87%
rename from plat/mediatek/mt8195/drivers/dp/mt_dp.h
rename to plat/mediatek/drivers/dp/mt_dp.h
index 8157598..d5dad29 100644
--- a/plat/mediatek/mt8195/drivers/dp/mt_dp.h
+++ b/plat/mediatek/drivers/dp/mt_dp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/drivers/dp/rules.mk b/plat/mediatek/drivers/dp/rules.mk
new file mode 100644
index 0000000..786d514
--- /dev/null
+++ b/plat/mediatek/drivers/dp/rules.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := dp
+LOCAL_SRCS-y := $(LOCAL_DIR)/mt_dp.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/common/drivers/gic600/mt_gic_v3.c b/plat/mediatek/drivers/gic600/mt_gic_v3.c
similarity index 93%
rename from plat/mediatek/common/drivers/gic600/mt_gic_v3.c
rename to plat/mediatek/drivers/gic600/mt_gic_v3.c
index ae8d697..cca5d0a 100644
--- a/plat/mediatek/common/drivers/gic600/mt_gic_v3.c
+++ b/plat/mediatek/drivers/gic600/mt_gic_v3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,7 +12,7 @@
 #include <bl31/interrupt_mgmt.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
-
+#include <lib/mtk_init/mtk_init.h>
 #include <mt_gic_v3.h>
 #include <mtk_plat_common.h>
 #include <plat/common/platform.h>
@@ -194,3 +194,15 @@
 	mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR +
 		irq / 32 * 4, bit);
 }
+
+int mt_gic_one_init(void)
+{
+	INFO("[%s] GIC initialization\n", __func__);
+
+	/* Initialize the GIC driver, CPU and distributor interfaces */
+	mt_gic_driver_init();
+	mt_gic_init();
+
+	return 0;
+}
+MTK_PLAT_SETUP_0_INIT(mt_gic_one_init);
diff --git a/plat/mediatek/common/drivers/gic600/mt_gic_v3.h b/plat/mediatek/drivers/gic600/mt_gic_v3.h
similarity index 87%
rename from plat/mediatek/common/drivers/gic600/mt_gic_v3.h
rename to plat/mediatek/drivers/gic600/mt_gic_v3.h
index c4ab44f..31513ef 100644
--- a/plat/mediatek/common/drivers/gic600/mt_gic_v3.h
+++ b/plat/mediatek/drivers/gic600/mt_gic_v3.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,5 +23,6 @@
 void gic_sgi_restore_all(void);
 uint32_t mt_irq_get_pending(uint32_t irq);
 void mt_irq_set_pending(uint32_t irq);
+int mt_gic_one_init(void);
 
 #endif /* MT_GIC_V3_H */
diff --git a/plat/mediatek/drivers/gic600/rules.mk b/plat/mediatek/drivers/gic600/rules.mk
new file mode 100644
index 0000000..3070591
--- /dev/null
+++ b/plat/mediatek/drivers/gic600/rules.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := gic600
+LOCAL_SRCS-y := $(LOCAL_DIR)/mt_gic_v3.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/gpio/mt8188/mtgpio.c b/plat/mediatek/drivers/gpio/mt8188/mtgpio.c
new file mode 100644
index 0000000..9e9fc5d
--- /dev/null
+++ b/plat/mediatek/drivers/gpio/mt8188/mtgpio.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+	uintptr_t reg_addr = 0U;
+	struct mt_pin_info gpio_info;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	gpio_info = mt_pin_infos[pin];
+
+	switch (gpio_info.base & 0x0f) {
+	case 0:
+		reg_addr = IOCFG_RM_BASE;
+		break;
+	case 1:
+		reg_addr = IOCFG_LT_BASE;
+		break;
+	case 2:
+		reg_addr = IOCFG_LM_BASE;
+		break;
+	case 3:
+		reg_addr = IOCFG_RT_BASE;
+		break;
+	default:
+		break;
+	}
+
+	return reg_addr;
+}
diff --git a/plat/mediatek/drivers/gpio/mt8188/mtgpio.h b/plat/mediatek/drivers/gpio/mt8188/mtgpio.h
new file mode 100644
index 0000000..32a4608
--- /dev/null
+++ b/plat/mediatek/drivers/gpio/mt8188/mtgpio.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <mtgpio_common.h>
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+	GPIO_UNSUPPORTED = -1,
+	GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6,
+	GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14,
+	GPIO15, GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22,
+	GPIO23, GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30,
+	GPIO31, GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38,
+	GPIO39, GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46,
+	GPIO47, GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54,
+	GPIO55, GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62,
+	GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70,
+	GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78,
+	GPIO79, GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86,
+	GPIO87, GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94,
+	GPIO95, GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102,
+	GPIO103, GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110,
+	GPIO111, GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118,
+	GPIO119, GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126,
+	GPIO127, GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134,
+	GPIO135, GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142,
+	GPIO143, GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150,
+	GPIO151, GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158,
+	GPIO159, GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166,
+	GPIO167, GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174,
+	GPIO175, GPIO176,
+	MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+static const struct mt_pin_info mt_pin_infos[] = {
+	PIN(0, 0, 6, 0x30, 0xb0),
+	PIN(1, 0, 7, 0x30, 0xb0),
+	PIN(2, 0, 8, 0x30, 0xb0),
+	PIN(3, 0, 9, 0x30, 0xb0),
+	PIN(4, 0, 10, 0x30, 0xb0),
+	PIN(5, 0, 11, 0x30, 0xb0),
+	PIN(6, 0, 12, 0x30, 0xb0),
+	PIN(7, 0, 13, 0x30, 0xb0),
+	PIN(8, 0, 14, 0x30, 0xb0),
+	PIN(9, 0, 15, 0x30, 0xb0),
+	PIN(10, 0, 16, 0x30, 0xb0),
+	PIN(11, 0, 17, 0x30, 0xb0),
+	PIN(12, 0, 12, 0x31, 0xa0),
+	PIN(13, 0, 13, 0x31, 0xa0),
+	PIN(14, 0, 14, 0x31, 0xa0),
+	PIN(15, 0, 15, 0x31, 0xa0),
+	PIN(16, 0, 1, 0x22, 0x50),
+	PIN(17, 0, 2, 0x22, 0x50),
+	PIN(18, 0, 3, 0x23, 0x60),
+	PIN(19, 0, 4, 0x23, 0x60),
+	PIN(20, 0, 5, 0x23, 0x60),
+	PIN(21, 0, 6, 0x23, 0x60),
+	PIN(22, 0, 0, 0x23, 0x60),
+	PIN(23, 0, 1, 0x23, 0x60),
+	PIN(24, 0, 2, 0x23, 0x60),
+	PIN(25, 0, 3, 0x30, 0xb0),
+	PIN(26, 0, 2, 0x30, 0xb0),
+	PIN(27, 0, 5, 0x30, 0xb0),
+	PIN(28, 0, 4, 0x30, 0xb0),
+	PIN(29, 0, 0, 0x30, 0xb0),
+	PIN(30, 0, 1, 0x30, 0xb0),
+	PIN(31, 0, 11, 0x30, 0xc0),
+	PIN(32, 0, 10, 0x30, 0xc0),
+	PIN(33, 0, 13, 0x30, 0xc0),
+	PIN(34, 0, 12, 0x30, 0xc0),
+	PIN(35, 0, 15, 0x30, 0xc0),
+	PIN(36, 0, 14, 0x30, 0xc0),
+	PIN(37, 0, 21, 0x30, 0xb0),
+	PIN(38, 0, 18, 0x30, 0xb0),
+	PIN(39, 0, 19, 0x30, 0xb0),
+	PIN(40, 0, 20, 0x30, 0xb0),
+	PIN(41, 0, 22, 0x30, 0xb0),
+	PIN(42, 1, 12, 0x31, 0xc0),
+	PIN(43, 1, 13, 0x31, 0xc0),
+	PIN(44, 1, 14, 0x31, 0xc0),
+	PIN(45, 1, 15, 0x31, 0xc0),
+	PIN(46, 0, 0, 0x22, 0x50),
+	PIN(47, 0, 25, 0x30, 0xb0),
+	PIN(48, 0, 24, 0x30, 0xb0),
+	PIN(49, 0, 23, 0x30, 0xb0),
+	PIN(50, 0, 5, 0x22, 0x50),
+	PIN(51, 0, 4, 0x22, 0x50),
+	PIN(52, 0, 3, 0x22, 0x50),
+	PIN(53, 0, 6, 0x22, 0x50),
+	PIN(54, 0, 7, 0x22, 0x50),
+	PIN(55, 0, 26, 0x30, 0xb0),
+	PIN(56, 0, 29, 0x30, 0xb0),
+	PIN(57, 0, 6, 0x31, 0xb0),
+	PIN(58, 0, 9, 0x31, 0xb0),
+	PIN(59, 0, 27, 0x30, 0xb0),
+	PIN(60, 0, 30, 0x30, 0xb0),
+	PIN(61, 0, 28, 0x30, 0xb0),
+	PIN(62, 0, 31, 0x30, 0xb0),
+	PIN(63, 0, 7, 0x31, 0xb0),
+	PIN(64, 0, 10, 0x31, 0xb0),
+	PIN(65, 0, 7, 0x23, 0x60),
+	PIN(66, 0, 9, 0x23, 0x60),
+	PIN(67, 0, 8, 0x23, 0x60),
+	PIN(68, 0, 10, 0x23, 0x60),
+	PIN(69, 0, 1, 0x30, 0xc0),
+	PIN(70, 0, 0, 0x30, 0xc0),
+	PIN(71, 0, 5, 0x30, 0xc0),
+	PIN(72, 0, 4, 0x30, 0xc0),
+	PIN(73, 0, 2, 0x30, 0xc0),
+	PIN(74, 0, 3, 0x30, 0xc0),
+	PIN(75, 0, 7, 0x30, 0xc0),
+	PIN(76, 0, 6, 0x30, 0xc0),
+	PIN(77, 0, 9, 0x30, 0xc0),
+	PIN(78, 0, 8, 0x30, 0xc0),
+	PIN(79, 0, 12, 0x23, 0x60),
+	PIN(80, 0, 11, 0x23, 0x60),
+	PIN(81, 0, 14, 0x23, 0x60),
+	PIN(82, 0, 13, 0x23, 0x60),
+	PIN(83, 0, 16, 0x31, 0xb0),
+	PIN(84, 0, 15, 0x31, 0xb0),
+	PIN(85, 0, 17, 0x31, 0xb0),
+	PIN(86, 0, 19, 0x31, 0xb0),
+	PIN(87, 0, 18, 0x31, 0xb0),
+	PIN(88, 0, 20, 0x31, 0xb0),
+	PIN(89, 0, 22, 0x31, 0xb0),
+	PIN(90, 0, 21, 0x31, 0xb0),
+	PIN(91, 0, 23, 0x31, 0xb0),
+	PIN(92, 0, 3, 0x31, 0xb0),
+	PIN(93, 0, 2, 0x31, 0xb0),
+	PIN(94, 0, 5, 0x31, 0xb0),
+	PIN(95, 0, 4, 0x31, 0xb0),
+	PIN(96, 0, 31, 0x31, 0xa0),
+	PIN(97, 0, 0, 0x31, 0xb0),
+	PIN(98, 0, 8, 0x31, 0xb0),
+	PIN(99, 0, 30, 0x31, 0xa0),
+	PIN(100, 0, 1, 0x31, 0xb0),
+	PIN(101, 0, 0, 0x31, 0xa0),
+	PIN(102, 0, 5, 0x31, 0xa0),
+	PIN(103, 0, 3, 0x31, 0xa0),
+	PIN(104, 0, 4, 0x31, 0xa0),
+	PIN(105, 0, 1, 0x31, 0xa0),
+	PIN(106, 0, 2, 0x31, 0xa0),
+	PIN(107, 0, 21, 0x31, 0xa0),
+	PIN(108, 0, 16, 0x31, 0xa0),
+	PIN(109, 0, 22, 0x31, 0xa0),
+	PIN(110, 0, 17, 0x31, 0xa0),
+	PIN(111, 0, 18, 0x31, 0xa0),
+	PIN(112, 0, 19, 0x31, 0xa0),
+	PIN(113, 0, 20, 0x31, 0xa0),
+	PIN(114, 0, 28, 0x31, 0xa0),
+	PIN(115, 0, 23, 0x31, 0xa0),
+	PIN(116, 0, 29, 0x31, 0xa0),
+	PIN(117, 0, 24, 0x31, 0xa0),
+	PIN(118, 0, 25, 0x31, 0xa0),
+	PIN(119, 0, 26, 0x31, 0xa0),
+	PIN(120, 0, 27, 0x31, 0xa0),
+	PIN(121, 0, 8, 0x22, 0x50),
+	PIN(122, 0, 11, 0x22, 0x50),
+	PIN(123, 0, 10, 0x22, 0x50),
+	PIN(124, 0, 9, 0x22, 0x50),
+	PIN(125, 0, 6, 0x31, 0xa0),
+	PIN(126, 0, 7, 0x31, 0xa0),
+	PIN(127, 0, 8, 0x31, 0xa0),
+	PIN(128, 0, 9, 0x31, 0xa0),
+	PIN(129, 0, 10, 0x31, 0xa0),
+	PIN(130, 0, 11, 0x31, 0xa0),
+	PIN(131, 1, 1, 0x30, 0xd0),
+	PIN(132, 1, 2, 0x30, 0xd0),
+	PIN(133, 1, 9, 0x30, 0xd0),
+	PIN(134, 1, 10, 0x30, 0xd0),
+	PIN(135, 1, 11, 0x30, 0xd0),
+	PIN(136, 1, 12, 0x30, 0xd0),
+	PIN(137, 1, 13, 0x30, 0xd0),
+	PIN(138, 1, 14, 0x30, 0xd0),
+	PIN(139, 1, 15, 0x30, 0xd0),
+	PIN(140, 1, 16, 0x30, 0xd0),
+	PIN(141, 1, 3, 0x30, 0xd0),
+	PIN(142, 1, 4, 0x30, 0xd0),
+	PIN(143, 1, 5, 0x30, 0xd0),
+	PIN(144, 1, 6, 0x30, 0xd0),
+	PIN(145, 1, 7, 0x30, 0xd0),
+	PIN(146, 1, 8, 0x30, 0xd0),
+	PIN(147, 1, 18, 0x30, 0xd0),
+	PIN(148, 1, 19, 0x30, 0xd0),
+	PIN(149, 1, 17, 0x30, 0xd0),
+	PIN(150, 1, 0, 0x30, 0xd0),
+	PIN(151, 1, 9, 0x31, 0xc0),
+	PIN(152, 1, 8, 0x31, 0xc0),
+	PIN(153, 1, 7, 0x31, 0xc0),
+	PIN(154, 1, 6, 0x31, 0xc0),
+	PIN(155, 1, 11, 0x31, 0xc0),
+	PIN(156, 1, 1, 0x31, 0xc0),
+	PIN(157, 1, 0, 0x31, 0xc0),
+	PIN(158, 1, 5, 0x31, 0xc0),
+	PIN(159, 1, 4, 0x31, 0xc0),
+	PIN(160, 1, 3, 0x31, 0xc0),
+	PIN(161, 1, 2, 0x31, 0xc0),
+	PIN(162, 1, 10, 0x31, 0xc0),
+	PIN(163, 1, 1, 0x23, 0x70),
+	PIN(164, 1, 0, 0x23, 0x70),
+	PIN(165, 1, 2, 0x23, 0x70),
+	PIN(166, 1, 3, 0x23, 0x70),
+	PIN(167, 1, 4, 0x23, 0x70),
+	PIN(168, 1, 5, 0x23, 0x70),
+	PIN(169, 1, 1, 0x22, 0x60),
+	PIN(170, 1, 0, 0x22, 0x60),
+	PIN(171, 1, 2, 0x22, 0x60),
+	PIN(172, 1, 3, 0x22, 0x60),
+	PIN(173, 1, 4, 0x22, 0x60),
+	PIN(174, 1, 5, 0x22, 0x60),
+	PIN(175, 0, 11, 0x31, 0xb0),
+	PIN(176, 0, 12, 0x31, 0xb0),
+};
+
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.c b/plat/mediatek/drivers/gpio/mtgpio_common.c
similarity index 97%
rename from plat/mediatek/common/drivers/gpio/mtgpio_common.c
rename to plat/mediatek/drivers/gpio/mtgpio_common.c
index 89977a5..bad0190 100644
--- a/plat/mediatek/common/drivers/gpio/mtgpio_common.c
+++ b/plat/mediatek/drivers/gpio/mtgpio_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 #include <drivers/delay_timer.h>
 #include <drivers/gpio.h>
 #include <lib/mmio.h>
+#include <lib/mtk_init/mtk_init.h>
 #include <mtgpio.h>
 #include <platform_def.h>
 
@@ -292,7 +293,10 @@
 	 .get_pull = mt_get_gpio_pull,
 };
 
-void mt_gpio_init(void)
+int mt_gpio_init(void)
 {
 	gpio_init(&mtgpio_ops);
+
+	return 0;
 }
+MTK_PLAT_SETUP_0_INIT(mt_gpio_init);
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.h b/plat/mediatek/drivers/gpio/mtgpio_common.h
similarity index 95%
rename from plat/mediatek/common/drivers/gpio/mtgpio_common.h
rename to plat/mediatek/drivers/gpio/mtgpio_common.h
index bf51055..d6b858c 100644
--- a/plat/mediatek/common/drivers/gpio/mtgpio_common.h
+++ b/plat/mediatek/drivers/gpio/mtgpio_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -104,6 +104,6 @@
 	uint16_t offset;
 };
 
-void mt_gpio_init(void);
+int mt_gpio_init(void);
 uintptr_t mt_gpio_find_reg_addr(uint32_t pin);
 #endif /* MT_GPIO_COMMON_H */
diff --git a/plat/mediatek/drivers/gpio/rules.mk b/plat/mediatek/drivers/gpio/rules.mk
new file mode 100644
index 0000000..78061a8
--- /dev/null
+++ b/plat/mediatek/drivers/gpio/rules.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := gpio
+
+LOCAL_SRCS-y := drivers/gpio/gpio.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mtgpio_common.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/mtgpio.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}
+PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c
new file mode 100644
index 0000000..1d6863f
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_iommu_plat.h>
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+
+/* mm iommu */
+#define SMI_L0_ID		(0)
+#define SMI_L1_ID		(1)
+#define SMI_L2_ID		(2)
+#define SMI_L3_ID		(3)
+#define SMI_L4_ID		(4)
+#define SMI_L5_ID		(5)
+#define SMI_L6_ID		(6)
+#define SMI_L7_ID		(7)
+#define SMI_L9_ID		(8)
+#define SMI_L10_ID		(9)
+#define SMI_L11A_ID		(10)
+#define SMI_L11B_ID		(11)
+#define SMI_L11C_ID		(12)
+#define SMI_L12_ID		(13)
+#define SMI_L13_ID		(14)
+#define SMI_L14_ID		(15)
+#define SMI_L15_ID		(16)
+#define SMI_L16A_ID		(17)
+#define SMI_L16B_ID		(18)
+#define SMI_L17A_ID		(19)
+#define SMI_L17B_ID		(20)
+#define SMI_L19_ID		(21)
+#define SMI_L21_ID		(22)
+#define SMI_L23_ID		(23)
+#define SMI_L27_ID		(24)
+#define SMI_L28_ID		(25)
+
+/* infra iommu */
+#define PERI_MST_PROT		(0x710)
+#define PERICFG_AO_IOMMU_1	(0x714)
+#define MMU_DEV_PCIE_0		(0)
+#define IFR_CFG_GROUP_NUM	(1)
+
+static struct mtk_smi_larb_config mt8188_larb_cfg[SMI_LARB_NUM] = {
+	[SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 7, 0),
+	[SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 7, 0),
+	[SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 5, 0),
+	[SMI_L3_ID] = LARB_CFG_ENTRY(SMI_LARB_3_BASE, 7, 0),
+	[SMI_L4_ID] = LARB_CFG_ENTRY(SMI_LARB_4_BASE, 7, 0),
+	[SMI_L5_ID] = LARB_CFG_ENTRY(SMI_LARB_5_BASE, 8, 0),
+	[SMI_L6_ID] = LARB_CFG_ENTRY(SMI_LARB_6_BASE, 4, 0),
+	[SMI_L7_ID] = LARB_CFG_ENTRY(SMI_LARB_7_BASE, 3, 0),
+	[SMI_L9_ID] = LARB_CFG_ENTRY(SMI_LARB_9_BASE, 25, 0),
+	[SMI_L10_ID] = LARB_CFG_ENTRY(SMI_LARB_10_BASE, 20, 0),
+	[SMI_L11A_ID] = LARB_CFG_ENTRY(SMI_LARB_11A_BASE, 30, 0),
+	[SMI_L11B_ID] = LARB_CFG_ENTRY(SMI_LARB_11B_BASE, 30, 0),
+	[SMI_L11C_ID] = LARB_CFG_ENTRY(SMI_LARB_11C_BASE, 30, 0),
+	[SMI_L12_ID] = LARB_CFG_ENTRY(SMI_LARB_12_BASE, 16, 0),
+	[SMI_L13_ID] = LARB_CFG_ENTRY(SMI_LARB_13_BASE, 24, 0),
+	[SMI_L14_ID] = LARB_CFG_ENTRY(SMI_LARB_14_BASE, 23, 0),
+	[SMI_L15_ID] = LARB_CFG_ENTRY(SMI_LARB_15_BASE, 19, 0),
+	[SMI_L16A_ID] = LARB_CFG_ENTRY(SMI_LARB_16A_BASE, 17, 0),
+	[SMI_L16B_ID] = LARB_CFG_ENTRY(SMI_LARB_16B_BASE, 17, 0),
+	[SMI_L17A_ID] = LARB_CFG_ENTRY(SMI_LARB_17A_BASE, 7, 0),
+	[SMI_L17B_ID] = LARB_CFG_ENTRY(SMI_LARB_17B_BASE, 7, 0),
+	/* venc nbm ports (5/6/11/15/16/17) to sram */
+	[SMI_L19_ID] = LARB_CFG_ENTRY_WITH_PATH(SMI_LARB_19_BASE, 27, 0, 0x38860),
+	[SMI_L21_ID] = LARB_CFG_ENTRY(SMI_LARB_21_BASE, 11, 0),
+	[SMI_L23_ID] = LARB_CFG_ENTRY(SMI_LARB_23_BASE, 9, 0),
+	[SMI_L27_ID] = LARB_CFG_ENTRY(SMI_LARB_27_BASE, 4, 0),
+	[SMI_L28_ID] = LARB_CFG_ENTRY(SMI_LARB_28_BASE, 0, 0),
+};
+
+static bool is_protected;
+
+static uint32_t mt8188_ifr_mst_cfg_base[IFR_CFG_GROUP_NUM] = {
+	PERICFG_AO_BASE,
+};
+static uint32_t mt8188_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = {
+	PERICFG_AO_IOMMU_1,
+};
+static struct mtk_ifr_mst_config mt8188_ifr_mst_cfg[MMU_DEV_NUM] = {
+	[MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 18),
+};
+
+struct mtk_smi_larb_config *g_larb_cfg = &mt8188_larb_cfg[0];
+struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8188_ifr_mst_cfg[0];
+uint32_t *g_ifr_mst_cfg_base = &mt8188_ifr_mst_cfg_base[0];
+uint32_t *g_ifr_mst_cfg_offs = &mt8188_ifr_mst_cfg_offs[0];
+
+/* Protect infra iommu enable setting registers as secure access. */
+void mtk_infra_iommu_enable_protect(void)
+{
+	if (!is_protected) {
+		mmio_write_32(PERICFG_AO_BASE + PERI_MST_PROT, 0xffffffff);
+		is_protected = true;
+	}
+}
diff --git a/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h
new file mode 100644
index 0000000..a59e0c7
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IOMMU_PLAT_H
+#define IOMMU_PLAT_H
+
+#include <mtk_iommu_priv.h>
+
+/* mm iommu */
+#define SMI_LARB_NUM	(26)
+extern struct mtk_smi_larb_config *g_larb_cfg;
+
+/* infra iommu */
+#define MMU_DEV_NUM	(1)
+extern struct mtk_ifr_mst_config *g_ifr_mst_cfg;
+extern uint32_t *g_ifr_mst_cfg_base;
+extern uint32_t *g_ifr_mst_cfg_offs;
+
+extern void mtk_infra_iommu_enable_protect(void);
+
+#endif /* IOMMU_PLAT_H */
diff --git a/plat/mediatek/drivers/iommu/mtk_iommu_priv.h b/plat/mediatek/drivers/iommu/mtk_iommu_priv.h
new file mode 100644
index 0000000..3404d31
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mtk_iommu_priv.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IOMMU_PRIV_H
+#define IOMMU_PRIV_H
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mtk_sip_svc.h>
+
+#define LARB_CFG_ENTRY(bs, p_nr, dom)			\
+	{ .base = (bs), .port_nr = (p_nr),		\
+	  .dom_id = (dom), .to_sram = 0, }
+
+#define LARB_CFG_ENTRY_WITH_PATH(bs, p_nr, dom, sram)	\
+	{ .base = (bs), .port_nr = (p_nr),		\
+	  .dom_id = (dom), .to_sram = (sram), }
+
+#define IFR_MST_CFG_ENTRY(idx, bit)	\
+	{ .cfg_addr_idx = (idx), .r_mmu_en_bit = (bit), }
+
+enum IOMMU_ATF_CMD {
+	IOMMU_ATF_CMD_CONFIG_SMI_LARB,		/* For mm master to enable iommu */
+	IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU,	/* For infra master to enable iommu */
+	IOMMU_ATF_CMD_COUNT,
+};
+
+struct mtk_smi_larb_config {
+	uint32_t base;
+	uint32_t port_nr;
+	uint32_t dom_id;
+	uint32_t to_sram;
+	uint32_t sec_en_msk;
+};
+
+struct mtk_ifr_mst_config {
+	uint8_t cfg_addr_idx;
+	uint8_t r_mmu_en_bit;
+};
+
+#endif	/* IOMMU_PRIV_H */
diff --git a/plat/mediatek/drivers/iommu/mtk_iommu_smc.c b/plat/mediatek/drivers/iommu/mtk_iommu_smc.c
new file mode 100644
index 0000000..9762d0b
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mtk_iommu_smc.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <mtk_iommu_plat.h>
+
+/* defination */
+/* smi larb */
+#define SMI_LARB_NON_SEC_CON(port)	(0x380 + ((port) << 2))
+#define PATH_SEL_MASK			(0xf0000) /* to sram (INT) */
+#define SMI_LARB_SEC_CON_INT(port)	(0xf00 + ((port) << 2))
+#define SMI_LARB_SEC_CON(port)		(0xf80 + ((port) << 2))
+#define MMU_MASK			BIT(0)
+#define MMU_EN(en)			((!!(en)) << 0)
+#define SEC_MASK			BIT(1)
+#define SEC_EN(en)			((!!(en)) << 1)
+#define DOMAIN_MASK			(0x1f << 4)
+#define SMI_MMU_EN(port)		(0x1 << (port))
+
+/* infra master */
+#define IFR_CFG_MMU_EN_MSK(r_bit)	(0x3 << (r_bit))
+
+/* smi larb configure */
+/*
+ * If multimedia security config is enabled, the SMI config register must be
+ * configurated in security world.
+ * And the SRAM path is also configurated here to enhance security.
+ */
+static void mtk_smi_larb_port_config_to_sram(
+				const struct mtk_smi_larb_config *larb,
+				uint32_t port_id)
+{
+	mmio_clrbits_32(larb->base + SMI_LARB_SEC_CON_INT(port_id),
+			MMU_MASK | SEC_MASK | DOMAIN_MASK);
+
+	mmio_setbits_32(larb->base + SMI_LARB_NON_SEC_CON(port_id),
+			PATH_SEL_MASK);
+}
+
+static void mtk_smi_port_config(const struct mtk_smi_larb_config *larb,
+				uint32_t port_id, uint8_t mmu_en, uint8_t sec_en)
+{
+	mmio_clrsetbits_32(larb->base + SMI_LARB_SEC_CON(port_id),
+			   MMU_MASK | SEC_MASK | DOMAIN_MASK,
+			   MMU_EN(mmu_en) | SEC_EN(sec_en));
+}
+
+static int mtk_smi_larb_port_config_sec(uint32_t larb_id, uint32_t mmu_en_msk)
+{
+	uint32_t port_id, port_nr;
+	const struct mtk_smi_larb_config *larb;
+	uint32_t to_sram;
+	uint8_t mmu_en;
+
+	if (larb_id >= SMI_LARB_NUM) {
+		return MTK_SIP_E_INVALID_PARAM;
+	}
+
+	larb = &g_larb_cfg[larb_id];
+	port_nr = larb->port_nr;
+	to_sram = larb->to_sram;
+
+	for (port_id = 0; port_id < port_nr; port_id++) {
+		if ((to_sram & BIT(port_id)) > 0U) {
+			mtk_smi_larb_port_config_to_sram(larb, port_id);
+			continue;
+		}
+		mmu_en = !!(mmu_en_msk & SMI_MMU_EN(port_id));
+		mtk_smi_port_config(larb, port_id, mmu_en, 0);
+	}
+
+	return MTK_SIP_E_SUCCESS;
+}
+
+static int mtk_infra_master_config_sec(uint32_t dev_id, uint32_t enable)
+{
+	const struct mtk_ifr_mst_config *ifr_cfg;
+	uint32_t reg_addr;
+
+	mtk_infra_iommu_enable_protect();
+
+	if (dev_id >= MMU_DEV_NUM) {
+		return MTK_SIP_E_NOT_SUPPORTED;
+	}
+
+	ifr_cfg = &g_ifr_mst_cfg[dev_id];
+	reg_addr = g_ifr_mst_cfg_base[(ifr_cfg->cfg_addr_idx)] +
+		   g_ifr_mst_cfg_offs[(ifr_cfg->cfg_addr_idx)];
+
+	if (enable > 0U) {
+		mmio_setbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit));
+	} else {
+		mmio_clrbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit));
+	}
+
+	return MTK_SIP_E_SUCCESS;
+}
+
+static u_register_t mtk_iommu_handler(u_register_t x1, u_register_t x2,
+				      u_register_t x3, u_register_t x4,
+				      void *handle, struct smccc_res *smccc_ret)
+{
+	uint32_t cmd_id = x1, mdl_id = x2, val = x3;
+	int ret = MTK_SIP_E_NOT_SUPPORTED;
+
+	(void)x4;
+	(void)handle;
+
+	switch (cmd_id) {
+	case IOMMU_ATF_CMD_CONFIG_SMI_LARB:
+		ret = mtk_smi_larb_port_config_sec(mdl_id, val);
+		break;
+	case IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU:
+		ret = mtk_infra_master_config_sec(mdl_id, val);
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+DECLARE_SMC_HANDLER(MTK_SIP_IOMMU_CONTROL, mtk_iommu_handler);
diff --git a/plat/mediatek/drivers/iommu/rules.mk b/plat/mediatek/drivers/iommu/rules.mk
new file mode 100644
index 0000000..5490f41
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/rules.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := mtk_iommu
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_iommu_smc.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/mtk_iommu_plat.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}
+PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/common/lpm/mt_lp_rm.c b/plat/mediatek/drivers/lpm/mt_lp_rm.c
similarity index 96%
rename from plat/mediatek/common/lpm/mt_lp_rm.c
rename to plat/mediatek/drivers/lpm/mt_lp_rm.c
index f3148fe..0bafc66 100644
--- a/plat/mediatek/common/lpm/mt_lp_rm.c
+++ b/plat/mediatek/drivers/lpm/mt_lp_rm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/common/lpm/mt_lp_rm.h b/plat/mediatek/drivers/lpm/mt_lp_rm.h
similarity index 94%
rename from plat/mediatek/common/lpm/mt_lp_rm.h
rename to plat/mediatek/drivers/lpm/mt_lp_rm.h
index 39759f1..e93dac3 100644
--- a/plat/mediatek/common/lpm/mt_lp_rm.h
+++ b/plat/mediatek/drivers/lpm/mt_lp_rm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic.c b/plat/mediatek/drivers/pmic/pmic.c
similarity index 73%
rename from plat/mediatek/mt8192/drivers/pmic/pmic.c
rename to plat/mediatek/drivers/pmic/pmic.c
index cca4413..a11ad9a 100644
--- a/plat/mediatek/mt8192/drivers/pmic/pmic.c
+++ b/plat/mediatek/drivers/pmic/pmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic.h b/plat/mediatek/drivers/pmic/pmic.h
similarity index 63%
rename from plat/mediatek/mt8192/drivers/pmic/pmic.h
rename to plat/mediatek/drivers/pmic/pmic.h
index aac22af..6c10f65 100644
--- a/plat/mediatek/mt8192/drivers/pmic/pmic.h
+++ b/plat/mediatek/drivers/pmic/pmic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,7 @@
 #ifndef PMIC_H
 #define PMIC_H
 
-#define PMIC_PWRHOLD 0xa08
+#define PMIC_PWRHOLD (0xa08)
 
 /* external API */
 void pmic_power_off(void);
diff --git a/plat/mediatek/drivers/pmic/rules.mk b/plat/mediatek/drivers/pmic/rules.mk
new file mode 100644
index 0000000..e408b03
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/rules.mk
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := pmic
+
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}/
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/pmic_wrap/mt8188/pmic_wrap_init.h b/plat/mediatek/drivers/pmic_wrap/mt8188/pmic_wrap_init.h
new file mode 100644
index 0000000..9027daf
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/mt8188/pmic_wrap_init.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <stdint.h>
+
+#include "platform_def.h"
+#include <pmic_wrap_init_common.h>
+
+static struct mt8188_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+/* PMIC_WRAP registers */
+struct mt8188_pmic_wrap_regs {
+	uint32_t init_done;
+	uint32_t reserved[543];
+	uint32_t wacs2_cmd;
+	uint32_t wacs2_wdata;
+	uint32_t reserved1[3];
+	uint32_t wacs2_rdata;
+	uint32_t reserved2[3];
+	uint32_t wacs2_vldclr;
+	uint32_t wacs2_sta;
+};
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init.c
similarity index 98%
rename from plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c
rename to plat/mediatek/drivers/pmic_wrap/pmic_wrap_init.c
index e3cfd46..0ee1c64 100644
--- a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2019-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
new file mode 100644
index 0000000..4ba1f5c
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_COMMON_H
+#define PMIC_WRAP_INIT_COMMON_H
+
+#include <stdint.h>
+
+#include "platform_def.h"
+
+/* external API */
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+
+#define GET_WACS_FSM(x)	((x >> 1) & 0x7)
+
+/* macro for SWINF_FSM */
+#define SWINF_FSM_IDLE		(0x00)
+#define SWINF_FSM_REQ		(0x02)
+#define SWINF_FSM_WFDLE		(0x04)
+#define SWINF_FSM_WFVLDCLR	(0x06)
+#define SWINF_INIT_DONE		(0x01)
+
+/* timeout setting */
+#define PWRAP_READ_US		(1000)
+#define PWRAP_WAIT_IDLE_US	(1000)
+
+/* error information flag */
+enum pwrap_errno {
+	E_PWR_INVALID_ARG		= 1,
+	E_PWR_INVALID_RW		= 2,
+	E_PWR_INVALID_ADDR		= 3,
+	E_PWR_INVALID_WDAT		= 4,
+	E_PWR_INVALID_OP_MANUAL		= 5,
+	E_PWR_NOT_IDLE_STATE		= 6,
+	E_PWR_NOT_INIT_DONE		= 7,
+	E_PWR_NOT_INIT_DONE_READ	= 8,
+	E_PWR_WAIT_IDLE_TIMEOUT		= 9,
+	E_PWR_WAIT_IDLE_TIMEOUT_READ	= 10,
+	E_PWR_INIT_SIDLY_FAIL		= 11,
+	E_PWR_RESET_TIMEOUT		= 12,
+	E_PWR_TIMEOUT			= 13,
+	E_PWR_INIT_RESET_SPI		= 20,
+	E_PWR_INIT_SIDLY		= 21,
+	E_PWR_INIT_REG_CLOCK		= 22,
+	E_PWR_INIT_ENABLE_PMIC		= 23,
+	E_PWR_INIT_DIO			= 24,
+	E_PWR_INIT_CIPHER		= 25,
+	E_PWR_INIT_WRITE_TEST		= 26,
+	E_PWR_INIT_ENABLE_CRC		= 27,
+	E_PWR_INIT_ENABLE_DEWRAP	= 28,
+	E_PWR_INIT_ENABLE_EVENT		= 29,
+	E_PWR_READ_TEST_FAIL		= 30,
+	E_PWR_WRITE_TEST_FAIL		= 31,
+	E_PWR_SWITCH_DIO		= 32,
+};
+
+#endif /* PMIC_WRAP_INIT_COMMON_H */
diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v2.c
similarity index 97%
rename from plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
rename to plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v2.c
index d9a79c4..80f55de 100644
--- a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/drivers/pmic_wrap/rules.mk b/plat/mediatek/drivers/pmic_wrap/rules.mk
new file mode 100644
index 0000000..9ba44a6
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/rules.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := pmic_wrap
+
+ifeq (${USE_PMIC_WRAP_INIT_V2}, 1)
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v2.c
+else
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init.c
+endif
+
+PLAT_INCLUDES += -I${LOCAL_DIR}/
+PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/rtc/mt8188/rtc.h b/plat/mediatek/drivers/rtc/mt8188/rtc.h
new file mode 100644
index 0000000..734e89f
--- /dev/null
+++ b/plat/mediatek/drivers/rtc/mt8188/rtc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+#include <rtc_mt6359p.h>
+
+#endif  /* RTC_H */
diff --git a/plat/mediatek/common/drivers/rtc/rtc_common.c b/plat/mediatek/drivers/rtc/rtc_common.c
similarity index 94%
rename from plat/mediatek/common/drivers/rtc/rtc_common.c
rename to plat/mediatek/drivers/rtc/rtc_common.c
index cad12a0..4efddff 100644
--- a/plat/mediatek/common/drivers/rtc/rtc_common.c
+++ b/plat/mediatek/drivers/rtc/rtc_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2019-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.c b/plat/mediatek/drivers/rtc/rtc_mt6359p.c
similarity index 97%
rename from plat/mediatek/common/drivers/rtc/rtc_mt6359p.c
rename to plat/mediatek/drivers/rtc/rtc_mt6359p.c
index 124bc8f..3bf4337 100644
--- a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.c
+++ b/plat/mediatek/drivers/rtc/rtc_mt6359p.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h b/plat/mediatek/drivers/rtc/rtc_mt6359p.h
similarity index 98%
rename from plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
rename to plat/mediatek/drivers/rtc/rtc_mt6359p.h
index 04726e3..199f152 100644
--- a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
+++ b/plat/mediatek/drivers/rtc/rtc_mt6359p.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/drivers/rtc/rules.mk b/plat/mediatek/drivers/rtc/rules.mk
new file mode 100644
index 0000000..2398f8a
--- /dev/null
+++ b/plat/mediatek/drivers/rtc/rules.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := rtc
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/rtc_common.c
+
+ifeq (${USE_RTC_MT6359P}, 1)
+LOCAL_SRCS-y += ${LOCAL_DIR}/rtc_mt6359p.c
+PLAT_INCLUDES += -I${LOCAL_DIR}
+endif
+
+PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/common/drivers/timer/mt_timer.c b/plat/mediatek/drivers/timer/mt_timer.c
similarity index 72%
rename from plat/mediatek/common/drivers/timer/mt_timer.c
rename to plat/mediatek/drivers/timer/mt_timer.c
index 0860885..11e4572 100644
--- a/plat/mediatek/common/drivers/timer/mt_timer.c
+++ b/plat/mediatek/drivers/timer/mt_timer.c
@@ -1,15 +1,16 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <arch_helpers.h>
+#include <common/debug.h>
 #include <lib/mmio.h>
+#include <lib/mtk_init/mtk_init.h>
 #include <mt_timer.h>
 #include <platform_def.h>
 
-
 uint64_t normal_time_base;
 uint64_t atf_time_base;
 
@@ -30,9 +31,14 @@
 	return cval;
 }
 
-void mt_systimer_init(void)
+int mt_systimer_init(void)
 {
+	INFO("[%s] systimer initialization\n", __func__);
+
 	/* Enable access in NS mode */
 	mmio_write_32(CNTWACR_REG, CNT_WRITE_ACCESS_CTL_MASK);
 	mmio_write_32(CNTRACR_REG, CNT_READ_ACCESS_CTL_MASK);
+
+	return 0;
 }
+MTK_PLAT_SETUP_0_INIT(mt_systimer_init);
diff --git a/plat/mediatek/common/drivers/timer/mt_timer.h b/plat/mediatek/drivers/timer/mt_timer.h
similarity index 91%
rename from plat/mediatek/common/drivers/timer/mt_timer.h
rename to plat/mediatek/drivers/timer/mt_timer.h
index b353177..1c08f90 100644
--- a/plat/mediatek/common/drivers/timer/mt_timer.h
+++ b/plat/mediatek/drivers/timer/mt_timer.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -30,6 +30,6 @@
 
 void sched_clock_init(uint64_t normal_base, uint64_t atf_base);
 uint64_t sched_clock(void);
-void mt_systimer_init(void);
+int mt_systimer_init(void);
 
 #endif /* MT_TIMER_H */
diff --git a/plat/mediatek/drivers/timer/rules.mk b/plat/mediatek/drivers/timer/rules.mk
new file mode 100644
index 0000000..005cf45
--- /dev/null
+++ b/plat/mediatek/drivers/timer/rules.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := timer
+LOCAL_SRCS-y := $(LOCAL_DIR)/mt_timer.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/common/drivers/uart/8250_console.S b/plat/mediatek/drivers/uart/8250_console.S
similarity index 98%
rename from plat/mediatek/common/drivers/uart/8250_console.S
rename to plat/mediatek/drivers/uart/8250_console.S
index 7a946f9..66f998d 100644
--- a/plat/mediatek/common/drivers/uart/8250_console.S
+++ b/plat/mediatek/drivers/uart/8250_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/common/drivers/uart/uart.c b/plat/mediatek/drivers/uart/uart.c
similarity index 97%
rename from plat/mediatek/common/drivers/uart/uart.c
rename to plat/mediatek/drivers/uart/uart.c
index b940eb3..fdaa793 100644
--- a/plat/mediatek/common/drivers/uart/uart.c
+++ b/plat/mediatek/drivers/uart/uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/common/drivers/uart/uart.h b/plat/mediatek/drivers/uart/uart.h
similarity index 97%
rename from plat/mediatek/common/drivers/uart/uart.h
rename to plat/mediatek/drivers/uart/uart.h
index ac8b94d..2ca74fa 100644
--- a/plat/mediatek/common/drivers/uart/uart.h
+++ b/plat/mediatek/drivers/uart/uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/common/drivers/uart/uart8250.h b/plat/mediatek/drivers/uart/uart8250.h
similarity index 93%
rename from plat/mediatek/common/drivers/uart/uart8250.h
rename to plat/mediatek/drivers/uart/uart8250.h
index da7c7a1..f0541d6 100644
--- a/plat/mediatek/common/drivers/uart/uart8250.h
+++ b/plat/mediatek/drivers/uart/uart8250.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/mediatek/include/mt8188/platform_def.h b/plat/mediatek/include/mt8188/platform_def.h
new file mode 100644
index 0000000..962d952
--- /dev/null
+++ b/plat/mediatek/include/mt8188/platform_def.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#define PLAT_PRIMARY_CPU	(0x0)
+
+#define MT_GIC_BASE		(0x0C000000)
+#define MCUCFG_BASE		(0x0C530000)
+#define IO_PHYS			(0x10000000)
+
+/* Aggregate of all devices for MMU mapping */
+#define MTK_DEV_RNG0_BASE	(MT_GIC_BASE)
+#define MTK_DEV_RNG0_SIZE	(0x600000)
+#define MTK_DEV_RNG1_BASE	(IO_PHYS)
+#define MTK_DEV_RNG1_SIZE	(0x10000000)
+
+/*******************************************************************************
+ * GPIO related constants
+ ******************************************************************************/
+#define GPIO_BASE		(IO_PHYS + 0x00005000)
+#define IOCFG_RM_BASE		(IO_PHYS + 0x01C00000)
+#define IOCFG_LT_BASE		(IO_PHYS + 0x01E10000)
+#define IOCFG_LM_BASE		(IO_PHYS + 0x01E20000)
+#define IOCFG_RT_BASE		(IO_PHYS + 0x01EA0000)
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define UART0_BASE	(IO_PHYS + 0x01002000)
+#define UART_BAUDRATE	(115200)
+
+/*******************************************************************************
+ * PMIC related constants
+ ******************************************************************************/
+#define PMIC_WRAP_BASE		(IO_PHYS + 0x00024000)
+
+/*******************************************************************************
+ * Infra IOMMU related constants
+ ******************************************************************************/
+#define PERICFG_AO_BASE		(IO_PHYS + 0x01003000)
+#define PERICFG_AO_REG_SIZE	(0x1000)
+
+/*******************************************************************************
+ * GIC-600 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE		(MT_GIC_BASE)
+#define MT_GIC_RDIST_BASE	(MT_GIC_BASE + 0x40000)
+
+/*******************************************************************************
+ * CIRQ related constants
+ ******************************************************************************/
+#define SYS_CIRQ_BASE		(IO_PHYS + 0x204000)
+#define MD_WDT_IRQ_BIT_ID	(141)
+#define CIRQ_IRQ_NUM		(730)
+#define CIRQ_REG_NUM		(23)
+#define CIRQ_SPI_START		(96)
+
+/*******************************************************************************
+ * MM IOMMU & SMI related constants
+ ******************************************************************************/
+#define SMI_LARB_0_BASE		(IO_PHYS + 0x0c022000)
+#define SMI_LARB_1_BASE		(IO_PHYS + 0x0c023000)
+#define SMI_LARB_2_BASE		(IO_PHYS + 0x0c102000)
+#define SMI_LARB_3_BASE		(IO_PHYS + 0x0c103000)
+#define SMI_LARB_4_BASE		(IO_PHYS + 0x04013000)
+#define SMI_LARB_5_BASE		(IO_PHYS + 0x04f02000)
+#define SMI_LARB_6_BASE		(IO_PHYS + 0x04f03000)
+#define SMI_LARB_7_BASE		(IO_PHYS + 0x04e04000)
+#define SMI_LARB_9_BASE		(IO_PHYS + 0x05001000)
+#define SMI_LARB_10_BASE	(IO_PHYS + 0x05120000)
+#define SMI_LARB_11A_BASE	(IO_PHYS + 0x05230000)
+#define SMI_LARB_11B_BASE	(IO_PHYS + 0x05530000)
+#define SMI_LARB_11C_BASE	(IO_PHYS + 0x05630000)
+#define SMI_LARB_12_BASE	(IO_PHYS + 0x05340000)
+#define SMI_LARB_13_BASE	(IO_PHYS + 0x06001000)
+#define SMI_LARB_14_BASE	(IO_PHYS + 0x06002000)
+#define SMI_LARB_15_BASE	(IO_PHYS + 0x05140000)
+#define SMI_LARB_16A_BASE	(IO_PHYS + 0x06008000)
+#define SMI_LARB_16B_BASE	(IO_PHYS + 0x0600a000)
+#define SMI_LARB_17A_BASE	(IO_PHYS + 0x06009000)
+#define SMI_LARB_17B_BASE	(IO_PHYS + 0x0600b000)
+#define SMI_LARB_19_BASE	(IO_PHYS + 0x0a010000)
+#define SMI_LARB_21_BASE	(IO_PHYS + 0x0802e000)
+#define SMI_LARB_23_BASE	(IO_PHYS + 0x0800d000)
+#define SMI_LARB_27_BASE	(IO_PHYS + 0x07201000)
+#define SMI_LARB_28_BASE	(IO_PHYS + 0x00000000)
+#define SMI_LARB_REG_RNG_SIZE	(0x1000)
+
+/*******************************************************************************
+ * DP related constants
+ ******************************************************************************/
+#define EDP_SEC_BASE		(IO_PHYS + 0x0C504000)
+#define DP_SEC_BASE		(IO_PHYS + 0x0C604000)
+#define EDP_SEC_SIZE		(0x1000)
+#define DP_SEC_SIZE		(0x1000)
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define SYS_COUNTER_FREQ_IN_HZ	(13000000)
+#define SYS_COUNTER_FREQ_IN_MHZ	(13)
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+#define PLATFORM_STACK_SIZE		(0x800)
+
+#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+
+#define PLAT_MAX_PWR_LVL		U(3)
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(9)
+
+#define PLATFORM_SYSTEM_COUNT		U(1)
+#define PLATFORM_MCUSYS_COUNT		U(1)
+#define PLATFORM_CLUSTER_COUNT		U(1)
+#define PLATFORM_CLUSTER0_CORE_COUNT	U(8)
+#define PLATFORM_CLUSTER1_CORE_COUNT	U(0)
+
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(8)
+
+#define SOC_CHIP_ID			U(0x8188)
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define TZRAM_BASE			(0x54600000)
+#define TZRAM_SIZE			(0x00030000)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
+ */
+#define BL31_BASE			(TZRAM_BASE + 0x1000)
+#define BL31_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#define MAX_XLAT_TABLES			(16)
+#define MAX_MMAP_REGIONS		(16)
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT		(6)
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/include/mtk_sip_def.h b/plat/mediatek/include/mtk_sip_def.h
index b591499..d760101 100644
--- a/plat/mediatek/include/mtk_sip_def.h
+++ b/plat/mediatek/include/mtk_sip_def.h
@@ -11,7 +11,9 @@
 #define MTK_SIP_SMC_FROM_NS_EL1_TABLE(_func) \
 	_func(MTK_SIP_KERNEL_TIME_SYNC, 0x202) \
 	_func(MTK_SIP_VCORE_CONTROL, 0x506) \
+	_func(MTK_SIP_IOMMU_CONTROL, 0x514) \
 	_func(MTK_SIP_APUSYS_CONTROL, 0x51E) \
+	_func(MTK_SIP_DP_CONTROL, 0x523) \
 	_func(MTK_SIP_KERNEL_GIC_OP, 0x526)
 
 #define MTK_SIP_SMC_FROM_BL33_TABLE(_func) \
diff --git a/plat/mediatek/lib/pm/mtk_pm.c b/plat/mediatek/lib/pm/mtk_pm.c
new file mode 100644
index 0000000..632a1e7
--- /dev/null
+++ b/plat/mediatek/lib/pm/mtk_pm.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+
+static const plat_psci_ops_t plat_psci_ops = {
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+			const plat_psci_ops_t **psci_ops)
+{
+	*psci_ops = &plat_psci_ops;
+
+	return 0;
+}
diff --git a/plat/mediatek/lib/pm/rules.mk b/plat/mediatek/lib/pm/rules.mk
new file mode 100644
index 0000000..77d0408
--- /dev/null
+++ b/plat/mediatek/lib/pm/rules.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := pm
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_pm.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index fa3605a..6bf1aa7 100644
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk
@@ -37,10 +37,10 @@
 				lib/cpus/aarch64/cortex_a53.S			\
 				lib/cpus/aarch64/cortex_a57.S			\
 				lib/cpus/aarch64/cortex_a72.S			\
-				${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c	\
-				${MTK_PLAT}/common/drivers/rtc/rtc_common.c	\
 				${MTK_PLAT}/common/mtk_plat_common.c		\
 				${MTK_PLAT}/common/mtk_sip_svc.c		\
+				${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init.c	\
+				${MTK_PLAT}/drivers/rtc/rtc_common.c		\
 				${MTK_PLAT_SOC}/aarch64/plat_helpers.S		\
 				${MTK_PLAT_SOC}/aarch64/platform_common.c	\
 				${MTK_PLAT_SOC}/bl31_plat_setup.c		\
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 653a0a6..a737d24 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -8,7 +8,7 @@
 MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
-                 -I${MTK_PLAT}/common/drivers/uart/               \
+                 -I${MTK_PLAT}/drivers/uart/                      \
                  -I${MTK_PLAT}/include/                           \
                  -I${MTK_PLAT_SOC}/drivers/                       \
                  -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
@@ -44,10 +44,10 @@
                    lib/cpus/aarch64/cortex_a73.S                         \
                    plat/common/plat_gicv3.c                              \
                    ${MTK_PLAT}/common/mtk_plat_common.c                  \
-                   ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \
-                   ${MTK_PLAT}/common/drivers/rtc/rtc_common.c           \
-                   ${MTK_PLAT}/common/drivers/uart/uart.c                \
                    ${MTK_PLAT}/common/params_setup.c                     \
+                   ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init.c        \
+                   ${MTK_PLAT}/drivers/rtc/rtc_common.c                  \
+                   ${MTK_PLAT}/drivers/uart/uart.c                       \
                    ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                    ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
                    ${MTK_PLAT_SOC}/drivers/devapc/devapc.c               \
diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c
index 42b2808..b5a0284 100644
--- a/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c
+++ b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c
@@ -4,9 +4,9 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <mt_cirq.h>
 #include <mt_lp_irqremain.h>
 #include <mt_lp_rm.h>
-#include <mtk_cirq.h>
 #include <plat_mtk_lpm.h>
 
 #define KEYPAD_IRQ_ID		U(138)
diff --git a/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h
index e837456..e8cbf7e 100644
--- a/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h
+++ b/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,10 +10,7 @@
 #include <stdint.h>
 
 #include "platform_def.h"
-
-/* external API */
-int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
-int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+#include <pmic_wrap_init_common.h>
 
 static struct mt8186_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
 
@@ -61,34 +58,4 @@
 	WACS_SYNC_BUSY           = 0x00
 };
 
-/* error information flag */
-enum {
-	E_PWR_INVALID_ARG             = 1,
-	E_PWR_INVALID_RW              = 2,
-	E_PWR_INVALID_ADDR            = 3,
-	E_PWR_INVALID_WDAT            = 4,
-	E_PWR_INVALID_OP_MANUAL       = 5,
-	E_PWR_NOT_IDLE_STATE          = 6,
-	E_PWR_NOT_INIT_DONE           = 7,
-	E_PWR_NOT_INIT_DONE_READ      = 8,
-	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
-	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
-	E_PWR_INIT_SIDLY_FAIL         = 11,
-	E_PWR_RESET_TIMEOUT           = 12,
-	E_PWR_TIMEOUT                 = 13,
-	E_PWR_INIT_RESET_SPI          = 20,
-	E_PWR_INIT_SIDLY              = 21,
-	E_PWR_INIT_REG_CLOCK          = 22,
-	E_PWR_INIT_ENABLE_PMIC        = 23,
-	E_PWR_INIT_DIO                = 24,
-	E_PWR_INIT_CIPHER             = 25,
-	E_PWR_INIT_WRITE_TEST         = 26,
-	E_PWR_INIT_ENABLE_CRC         = 27,
-	E_PWR_INIT_ENABLE_DEWRAP      = 28,
-	E_PWR_INIT_ENABLE_EVENT       = 29,
-	E_PWR_READ_TEST_FAIL          = 30,
-	E_PWR_WRITE_TEST_FAIL         = 31,
-	E_PWR_SWITCH_DIO              = 32
-};
-
 #endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c
index 66fbe91..dd2aee8 100644
--- a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -26,7 +26,7 @@
 #include <mt_spm_suspend.h>
 
 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
-#include <mtk_cirq.h>
+#include <mt_cirq.h>
 #endif
 
 #include <plat_mtk_lpm.h>
diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk
index 1492038..8717d7d 100644
--- a/plat/mediatek/mt8186/platform.mk
+++ b/plat/mediatek/mt8186/platform.mk
@@ -8,17 +8,19 @@
 MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
-                 -I${MTK_PLAT}/common/drivers/gic600/             \
-                 -I${MTK_PLAT}/common/drivers/gpio/             \
-                 -I${MTK_PLAT}/common/drivers/uart/               \
-                 -I${MTK_PLAT}/common/drivers/timer/              \
-		 -I${MTK_PLAT}/common/lpm/                        \
+                 -I${MTK_PLAT}/drivers/cirq/                      \
+                 -I${MTK_PLAT}/drivers/gic600/                    \
+                 -I${MTK_PLAT}/drivers/gpio/                      \
+                 -I${MTK_PLAT}/drivers/lpm/                       \
+                 -I${MTK_PLAT}/drivers/pmic_wrap/                 \
+                 -I${MTK_PLAT}/drivers/timer/                     \
+                 -I${MTK_PLAT}/drivers/uart/                      \
                  -I${MTK_PLAT}/include/                           \
                  -I${MTK_PLAT_SOC}/drivers/spm/                   \
                  -I${MTK_PLAT_SOC}/drivers/dcm/                   \
-                 -I${MTK_PLAT_SOC}/drivers/dfd/                    \
+                 -I${MTK_PLAT_SOC}/drivers/dfd/                   \
                  -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
-                 -I${MTK_PLAT_SOC}/drivers/gpio/               \
+                 -I${MTK_PLAT_SOC}/drivers/gpio/                  \
                  -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
                  -I${MTK_PLAT_SOC}/drivers/pmic/                  \
                  -I${MTK_PLAT_SOC}/drivers/rtc/                   \
@@ -44,17 +46,17 @@
                 lib/cpus/aarch64/cortex_a55.S                         \
                 lib/cpus/aarch64/cortex_a76.S                         \
                 plat/common/plat_gicv3.c                              \
-                ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c         \
-                ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c       \
-                ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \
-                ${MTK_PLAT}/common/drivers/rtc/rtc_common.c           \
                 ${MTK_PLAT}/common/mtk_plat_common.c                  \
                 ${MTK_PLAT}/common/mtk_sip_svc.c                      \
                 ${MTK_PLAT}/common/params_setup.c                     \
-                ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
-                ${MTK_PLAT}/common/drivers/uart/uart.c                \
-                ${MTK_PLAT}/common/mtk_cirq.c           	      \
-		${MTK_PLAT}/common/lpm/mt_lp_rm.c                     \
+                ${MTK_PLAT}/drivers/cirq/mt_cirq.c                    \
+                ${MTK_PLAT}/drivers/gic600/mt_gic_v3.c                \
+                ${MTK_PLAT}/drivers/gpio/mtgpio_common.c              \
+                ${MTK_PLAT}/drivers/lpm/mt_lp_rm.c                    \
+                ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init.c        \
+                ${MTK_PLAT}/drivers/rtc/rtc_common.c                  \
+                ${MTK_PLAT}/drivers/timer/mt_timer.c                  \
+                ${MTK_PLAT}/drivers/uart/uart.c                       \
                 ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
                 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                 ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
diff --git a/plat/mediatek/mt8188/aarch64/plat_helpers.S b/plat/mediatek/mt8188/aarch64/plat_helpers.S
new file mode 100644
index 0000000..7073ab1
--- /dev/null
+++ b/plat/mediatek/mt8188/aarch64/plat_helpers.S
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl plat_is_my_cpu_primary
+	.globl plat_my_core_pos
+	.globl plat_mediatek_calc_core_pos
+
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+	cmp	x0, #PLAT_PRIMARY_CPU
+	cset	x0, eq
+	ret
+endfunc plat_is_my_cpu_primary
+
+	/* -----------------------------------------------------
+	 *  unsigned int plat_my_core_pos(void)
+	 *  This function uses the plat_mediatek_calc_core_pos()
+	 *  definition to get the index of the calling CPU.
+	 * -----------------------------------------------------
+	 */
+func plat_my_core_pos
+	mrs	x0, mpidr_el1
+	b	plat_mediatek_calc_core_pos
+endfunc plat_my_core_pos
+
+	/* -----------------------------------------------------
+	 * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+	 *
+	 * With this function: CorePos = CoreID (AFF1)
+	 * we do it with x0 = (x0 >> 8) & 0xff
+	 * -----------------------------------------------------
+	 */
+func plat_mediatek_calc_core_pos
+	mov	x1, #MPIDR_AFFLVL_MASK
+	and	x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
+	ret
+endfunc plat_mediatek_calc_core_pos
diff --git a/plat/mediatek/mt8188/include/plat_helpers.h b/plat/mediatek/mt8188/include/plat_helpers.h
new file mode 100644
index 0000000..eb78623
--- /dev/null
+++ b/plat/mediatek/mt8188/include/plat_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_HELPERS_H
+#define PLAT_HELPERS_H
+
+unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+
+#endif /* PLAT_HELPERS_H */
diff --git a/plat/mediatek/mt8188/include/plat_macros.S b/plat/mediatek/mt8188/include/plat_macros.S
new file mode 100644
index 0000000..a6e05a9
--- /dev/null
+++ b/plat/mediatek/mt8188/include/plat_macros.S
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <platform_def.h>
+
+.section .rodata.gic_reg_name, "aS"
+gicc_regs:
+	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
+gicd_pend_reg:
+	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
+		" Offset:\t\t\tvalue\n"
+newline:
+	.asciz "\n"
+spacer:
+	.asciz ":\t\t0x"
+
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
+	/* ---------------------------------------------
+	 * The below macro prints out relevant GIC
+	 * registers whenever an unhandled exception
+	 * is taken in BL31.
+	 * Clobbers: x0 - x10, x26, x27, sp
+	 * ---------------------------------------------
+	 */
+	.macro plat_crash_print_regs
+	/* TODO: leave implementation to GIC owner */
+	.endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/mediatek/mt8188/include/plat_private.h b/plat/mediatek/mt8188/include/plat_private.h
new file mode 100644
index 0000000..4d4ac85
--- /dev/null
+++ b/plat/mediatek/mt8188/include/plat_private.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PRIVATE_H
+#define PLAT_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+			    uintptr_t total_size,
+			    uintptr_t ro_start,
+			    uintptr_t ro_limit);
+
+#endif /* PLAT_PRIVATE_H */
diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk
new file mode 100644
index 0000000..0c1e7cd
--- /dev/null
+++ b/plat/mediatek/mt8188/plat_config.mk
@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Separate text code and read only data
+SEPARATE_CODE_AND_RODATA := 1
+# ARMv8.2 and above need enable HW assist coherence
+HW_ASSISTED_COHERENCY := 1
+# No need coherency memory because of HW assistency
+USE_COHERENT_MEM := 0
+# GIC600
+GICV3_SUPPORT_GIC600 := 1
+#
+# MTK options
+#
+PLAT_EXTRA_RODATA_INCLUDES := 1
+USE_PMIC_WRAP_INIT_V2 := 1
+USE_RTC_MT6359P := 1
+
+# Configs for A78 and A55
+CTX_INCLUDE_AARCH32_REGS := 0
+ERRATA_A55_1530923 := 1
+ERRATA_A55_1221012 := 1
+ERRATA_A78_1688305 := 1
+ERRATA_A78_1941498 := 1
+ERRATA_A78_1951500 := 1
+ERRATA_A78_1821534 := 1
+ERRATA_A78_2132060 := 1
+ERRATA_A78_2242635 := 1
+
+MACH_MT8188 := 1
+$(eval $(call add_define,MACH_MT8188))
diff --git a/plat/mediatek/mt8188/plat_mmap.c b/plat/mediatek/mt8188/plat_mmap.c
new file mode 100644
index 0000000..0d4cbe8
--- /dev/null
+++ b/plat/mediatek/mt8188/plat_mmap.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+
+static const mmap_region_t plat_mmap[] = {
+	MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	{ 0 }
+};
+DECLARE_MTK_MMAP_REGIONS(plat_mmap);
diff --git a/plat/mediatek/mt8188/plat_topology.c b/plat/mediatek/mt8188/plat_topology.c
new file mode 100644
index 0000000..9fa2855
--- /dev/null
+++ b/plat/mediatek/mt8188/plat_topology.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+
+#include <plat_helpers.h>
+#include <platform_def.h>
+
+const unsigned char mtk_power_domain_tree_desc[] = {
+	/* Number of root nodes */
+	PLATFORM_SYSTEM_COUNT,
+	/* Number of children for the root node */
+	PLATFORM_MCUSYS_COUNT,
+	/* Number of children for the mcusys node */
+	PLATFORM_CLUSTER_COUNT,
+	/* Number of children for the first cluster node */
+	PLATFORM_CLUSTER0_CORE_COUNT,
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return mtk_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	unsigned int cluster_id, cpu_id;
+
+	if ((read_mpidr() & MPIDR_MT_MASK) != 0) {
+		/* ARMv8.2 arch */
+		if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) {
+			return -1;
+		}
+		return plat_mediatek_calc_core_pos(mpidr);
+	}
+
+	mpidr &= MPIDR_AFFINITY_MASK;
+
+	if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) {
+		return -1;
+	}
+
+	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+	if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
+		return -1;
+	}
+
+	/*
+	 * Validate cpu_id by checking whether it represents a CPU in
+	 * one of the two clusters present on the platform.
+	 */
+	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
+		return -1;
+	}
+
+	return (cpu_id + (cluster_id * 8));
+}
diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk
new file mode 100644
index 0000000..84bcfac
--- /dev/null
+++ b/plat/mediatek/mt8188/platform.mk
@@ -0,0 +1,56 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+MTK_PLAT := plat/mediatek
+MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
+MTK_SOC := ${PLAT}
+
+include plat/mediatek/build_helpers/mtk_build_helpers.mk
+include drivers/arm/gic/v3/gicv3.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_INCLUDES := -I${MTK_PLAT}/common \
+		 -I${MTK_PLAT}/include \
+		 -I${MTK_PLAT}/include/${MTK_SOC} \
+		 -I${MTK_PLAT} \
+		 -I${MTK_PLAT_SOC}/include \
+		 -Idrivers/arm/gic \
+
+MODULES-y += $(MTK_PLAT)/common
+MODULES-y += $(MTK_PLAT)/lib/mtk_init
+MODULES-y += $(MTK_PLAT)/lib/pm
+MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/dp
+MODULES-y += $(MTK_PLAT)/drivers/gic600
+MODULES-y += $(MTK_PLAT)/drivers/gpio
+MODULES-y += $(MTK_PLAT)/drivers/iommu
+MODULES-y += $(MTK_PLAT)/drivers/pmic
+MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
+MODULES-y += $(MTK_PLAT)/drivers/rtc
+MODULES-y += $(MTK_PLAT)/drivers/timer
+
+PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
+			  drivers/ti/uart/aarch64/16550_console.S \
+			  lib/bl_aux_params/bl_aux_params.c
+
+BL31_SOURCES += drivers/delay_timer/delay_timer.c \
+		drivers/delay_timer/generic_delay_timer.c \
+		lib/cpus/aarch64/cortex_a55.S \
+		lib/cpus/aarch64/cortex_a78.S \
+		${GICV3_SOURCES} \
+		${XLAT_TABLES_LIB_SRCS} \
+		plat/common/plat_gicv3.c \
+		plat/common/plat_psci_common.c \
+		plat/common/aarch64/crash_console_helpers.S \
+		${MTK_PLAT}/common/mtk_plat_common.c \
+		${MTK_PLAT}/common/params_setup.c \
+		${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
+		$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c \
+		$(MTK_PLAT)/$(MTK_SOC)/plat_topology.c
+
+include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk
+
+include lib/coreboot/coreboot.mk
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
index e74d3e7..872f4d0 100644
--- a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <mt_lp_rm.h>
+#include <mt_cirq.h>
 #include <mt_lp_irqremain.h>
-#include <mtk_cirq.h>
+#include <mt_lp_rm.h>
 #include <plat_mtk_lpm.h>
 
 #define EDMA0_IRQ_ID		U(448)
diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h
index ae892ed..b9ab586 100644
--- a/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h
+++ b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,10 +10,7 @@
 #include <stdint.h>
 
 #include "platform_def.h"
-
-/* external API */
-int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
-int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+#include <pmic_wrap_init_common.h>
 
 static struct mt8192_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
 
@@ -30,47 +27,4 @@
 	uint32_t wacs2_sta;
 };
 
-#define GET_WACS_FSM(x)	((x >> 1) & 0x7)
-
-/* macro for SWINF_FSM */
-#define SWINF_FSM_IDLE		(0x00)
-#define SWINF_FSM_REQ		(0x02)
-#define SWINF_FSM_WFDLE		(0x04)
-#define SWINF_FSM_WFVLDCLR	(0x06)
-#define SWINF_INIT_DONE		(0x01)
-
-/* timeout setting */
-#define PWRAP_READ_US	1000
-#define PWRAP_WAIT_IDLE_US	1000
-
-/* error information flag */
-enum pwrap_errno {
-	E_PWR_INVALID_ARG             = 1,
-	E_PWR_INVALID_RW              = 2,
-	E_PWR_INVALID_ADDR            = 3,
-	E_PWR_INVALID_WDAT            = 4,
-	E_PWR_INVALID_OP_MANUAL       = 5,
-	E_PWR_NOT_IDLE_STATE          = 6,
-	E_PWR_NOT_INIT_DONE           = 7,
-	E_PWR_NOT_INIT_DONE_READ      = 8,
-	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
-	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
-	E_PWR_INIT_SIDLY_FAIL         = 11,
-	E_PWR_RESET_TIMEOUT           = 12,
-	E_PWR_TIMEOUT                 = 13,
-	E_PWR_INIT_RESET_SPI          = 20,
-	E_PWR_INIT_SIDLY              = 21,
-	E_PWR_INIT_REG_CLOCK          = 22,
-	E_PWR_INIT_ENABLE_PMIC        = 23,
-	E_PWR_INIT_DIO                = 24,
-	E_PWR_INIT_CIPHER             = 25,
-	E_PWR_INIT_WRITE_TEST         = 26,
-	E_PWR_INIT_ENABLE_CRC         = 27,
-	E_PWR_INIT_ENABLE_DEWRAP      = 28,
-	E_PWR_INIT_ENABLE_EVENT       = 29,
-	E_PWR_READ_TEST_FAIL          = 30,
-	E_PWR_WRITE_TEST_FAIL         = 31,
-	E_PWR_SWITCH_DIO              = 32
-};
-
 #endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
index f66b8ec..18c43b1 100644
--- a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,8 +23,8 @@
 #include <plat_mtk_lpm.h>
 
 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mt_cirq.h>
 #include <mt_gic_v3.h>
-#include <mtk_cirq.h>
 #endif
 
 #define CONSTRAINT_BUS26M_ALLOW			\
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index 4f61368..efc14ec 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -8,12 +8,15 @@
 MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
-                 -I${MTK_PLAT}/common/drivers/gic600/             \
-                 -I${MTK_PLAT}/common/drivers/gpio/               \
-                 -I${MTK_PLAT}/common/drivers/rtc/                \
-                 -I${MTK_PLAT}/common/drivers/timer/              \
-                 -I${MTK_PLAT}/common/drivers/uart/               \
-                 -I${MTK_PLAT}/common/lpm/                        \
+                 -I${MTK_PLAT}/drivers/cirq/                      \
+                 -I${MTK_PLAT}/drivers/gic600/                    \
+                 -I${MTK_PLAT}/drivers/gpio/                      \
+                 -I${MTK_PLAT}/drivers/lpm/                       \
+                 -I${MTK_PLAT}/drivers/pmic/                      \
+                 -I${MTK_PLAT}/drivers/pmic_wrap/                 \
+                 -I${MTK_PLAT}/drivers/rtc/                       \
+                 -I${MTK_PLAT}/drivers/timer/                     \
+                 -I${MTK_PLAT}/drivers/uart/                      \
                  -I${MTK_PLAT}/include/                           \
                  -I${MTK_PLAT_SOC}/include/                       \
                  -I${MTK_PLAT_SOC}/drivers/                       \
@@ -46,22 +49,22 @@
                    lib/cpus/aarch64/cortex_a55.S                         \
                    lib/cpus/aarch64/cortex_a76.S                         \
                    plat/common/plat_gicv3.c                              \
-                   ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c         \
-                   ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c       \
-                   ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
-                   ${MTK_PLAT}/common/drivers/rtc/rtc_common.c           \
-                   ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c          \
-                   ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
-                   ${MTK_PLAT}/common/drivers/uart/uart.c                \
-                   ${MTK_PLAT}/common/lpm/mt_lp_rm.c                     \
-                   ${MTK_PLAT}/common/mtk_cirq.c                         \
                    ${MTK_PLAT}/common/mtk_plat_common.c                  \
                    ${MTK_PLAT}/common/mtk_sip_svc.c                      \
                    ${MTK_PLAT}/common/params_setup.c                     \
+                   ${MTK_PLAT}/drivers/cirq/mt_cirq.c                    \
+                   ${MTK_PLAT}/drivers/gic600/mt_gic_v3.c                \
+                   ${MTK_PLAT}/drivers/gpio/mtgpio_common.c              \
+                   ${MTK_PLAT}/drivers/lpm/mt_lp_rm.c                    \
+                   ${MTK_PLAT}/drivers/pmic/pmic.c                       \
+                   ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init_v2.c     \
+                   ${MTK_PLAT}/drivers/rtc/rtc_common.c                  \
+                   ${MTK_PLAT}/drivers/rtc/rtc_mt6359p.c                 \
+                   ${MTK_PLAT}/drivers/timer/mt_timer.c                  \
+                   ${MTK_PLAT}/drivers/uart/uart.c                       \
                    ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
                    ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                    ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
-                   ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
                    ${MTK_PLAT_SOC}/plat_pm.c                             \
                    ${MTK_PLAT_SOC}/plat_topology.c                       \
                    ${MTK_PLAT_SOC}/plat_sip_calls.c                      \
diff --git a/plat/mediatek/mt8195/aarch64/platform_common.c b/plat/mediatek/mt8195/aarch64/platform_common.c
index 2b95171..1f5c5fa 100644
--- a/plat/mediatek/mt8195/aarch64/platform_common.c
+++ b/plat/mediatek/mt8195/aarch64/platform_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,7 +19,7 @@
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE,
+	MAP_REGION_FLAT(EDP_SEC_BASE, EDP_SEC_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c
index 4147184..f415cb8 100644
--- a/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c
@@ -1,15 +1,14 @@
 /*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <mt_lp_rm.h>
+#include <mt_cirq.h>
 #include <mt_lp_irqremain.h>
-#include <mtk_cirq.h>
+#include <mt_lp_rm.h>
 #include <plat_mtk_lpm.h>
 
-
 #define KEYPAD_IRQ_ID		U(138)
 
 #define KEYPAD_WAKESRC		0x4
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.c b/plat/mediatek/mt8195/drivers/pmic/pmic.c
deleted file mode 100644
index cca4413..0000000
--- a/plat/mediatek/mt8195/drivers/pmic/pmic.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <pmic.h>
-#include <pmic_wrap_init.h>
-
-void pmic_power_off(void)
-{
-	pwrap_write(PMIC_PWRHOLD, 0x0);
-}
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.h b/plat/mediatek/mt8195/drivers/pmic/pmic.h
deleted file mode 100644
index aac22af..0000000
--- a/plat/mediatek/mt8195/drivers/pmic/pmic.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PMIC_H
-#define PMIC_H
-
-#define PMIC_PWRHOLD 0xa08
-
-/* external API */
-void pmic_power_off(void);
-
-#endif /* PMIC_H */
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
index 39e78f5..9e6e74c 100644
--- a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,10 +10,7 @@
 #include <stdint.h>
 
 #include "platform_def.h"
-
-/* external API */
-int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
-int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+#include <pmic_wrap_init_common.h>
 
 static struct mt8195_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
 
@@ -30,47 +27,4 @@
 	uint32_t wacs2_sta;
 };
 
-#define GET_WACS_FSM(x)	((x >> 1) & 0x7)
-
-/* macro for SWINF_FSM */
-#define SWINF_FSM_IDLE		(0x00)
-#define SWINF_FSM_REQ		(0x02)
-#define SWINF_FSM_WFDLE		(0x04)
-#define SWINF_FSM_WFVLDCLR	(0x06)
-#define SWINF_INIT_DONE		(0x01)
-
-/* timeout setting */
-#define PWRAP_READ_US	1000
-#define PWRAP_WAIT_IDLE_US	1000
-
-/* error information flag */
-enum pwrap_errno {
-	E_PWR_INVALID_ARG             = 1,
-	E_PWR_INVALID_RW              = 2,
-	E_PWR_INVALID_ADDR            = 3,
-	E_PWR_INVALID_WDAT            = 4,
-	E_PWR_INVALID_OP_MANUAL       = 5,
-	E_PWR_NOT_IDLE_STATE          = 6,
-	E_PWR_NOT_INIT_DONE           = 7,
-	E_PWR_NOT_INIT_DONE_READ      = 8,
-	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
-	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
-	E_PWR_INIT_SIDLY_FAIL         = 11,
-	E_PWR_RESET_TIMEOUT           = 12,
-	E_PWR_TIMEOUT                 = 13,
-	E_PWR_INIT_RESET_SPI          = 20,
-	E_PWR_INIT_SIDLY              = 21,
-	E_PWR_INIT_REG_CLOCK          = 22,
-	E_PWR_INIT_ENABLE_PMIC        = 23,
-	E_PWR_INIT_DIO                = 24,
-	E_PWR_INIT_CIPHER             = 25,
-	E_PWR_INIT_WRITE_TEST         = 26,
-	E_PWR_INIT_ENABLE_CRC         = 27,
-	E_PWR_INIT_ENABLE_DEWRAP      = 28,
-	E_PWR_INIT_ENABLE_EVENT       = 29,
-	E_PWR_READ_TEST_FAIL          = 30,
-	E_PWR_WRITE_TEST_FAIL         = 31,
-	E_PWR_SWITCH_DIO              = 32
-};
-
 #endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c
index d2ad282..87278d7 100644
--- a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,8 +23,8 @@
 #include <plat_mtk_lpm.h>
 
 #ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mt_cirq.h>
 #include <mt_gic_v3.h>
-#include <mtk_cirq.h>
 #endif
 
 #define CONSTRAINT_BUS26M_ALLOW			\
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index d4f2f83..2a2f559 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -48,9 +48,9 @@
 /*******************************************************************************
  * DP/eDP related constants
  ******************************************************************************/
-#define eDP_SEC_BASE		(IO_PHYS + 0x0C504000)
+#define EDP_SEC_BASE		(IO_PHYS + 0x0C504000)
 #define DP_SEC_BASE		(IO_PHYS + 0x0C604000)
-#define eDP_SEC_SIZE		0x1000
+#define EDP_SEC_SIZE		0x1000
 #define DP_SEC_SIZE		0x1000
 
 /*******************************************************************************
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 9d5b5c9..414d655 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk
@@ -8,23 +8,26 @@
 MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
-                 -I${MTK_PLAT}/common/drivers/gic600/             \
-                 -I${MTK_PLAT}/common/drivers/gpio/               \
-                 -I${MTK_PLAT}/common/drivers/rtc/                \
-                 -I${MTK_PLAT}/common/drivers/timer/              \
-                 -I${MTK_PLAT}/common/drivers/uart/               \
-                 -I${MTK_PLAT}/common/lpm/                        \
+                 -I${MTK_PLAT}/drivers/cirq/                      \
+                 -I${MTK_PLAT}/drivers/dp/                        \
+                 -I${MTK_PLAT}/drivers/gic600/                    \
+                 -I${MTK_PLAT}/drivers/gpio/                      \
+                 -I${MTK_PLAT}/drivers/lpm/                       \
+                 -I${MTK_PLAT}/drivers/pmic/                      \
+                 -I${MTK_PLAT}/drivers/pmic_wrap/                 \
+                 -I${MTK_PLAT}/drivers/rtc/                       \
+                 -I${MTK_PLAT}/drivers/timer/                     \
+                 -I${MTK_PLAT}/drivers/uart/                      \
                  -I${MTK_PLAT}/include/                           \
                  -I${MTK_PLAT_SOC}/drivers/apusys/                \
                  -I${MTK_PLAT_SOC}/drivers/dcm                    \
                  -I${MTK_PLAT_SOC}/drivers/dfd                    \
-                 -I${MTK_PLAT_SOC}/drivers/dp/                    \
                  -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
                  -I${MTK_PLAT_SOC}/drivers/gpio/                  \
                  -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
                  -I${MTK_PLAT_SOC}/drivers/pmic/                  \
                  -I${MTK_PLAT_SOC}/drivers/spmc/                  \
-                 -I${MTK_PLAT_SOC}/drivers/ptp3/                   \
+                 -I${MTK_PLAT_SOC}/drivers/ptp3/                  \
                  -I${MTK_PLAT_SOC}/include/
 
 GICV3_SUPPORT_GIC600        :=      1
@@ -46,36 +49,36 @@
                 lib/cpus/aarch64/cortex_a55.S                         \
                 lib/cpus/aarch64/cortex_a78.S                         \
                 plat/common/plat_gicv3.c                              \
-                ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c         \
-                ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c       \
-                ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
-                ${MTK_PLAT}/common/drivers/rtc/rtc_common.c           \
-                ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c          \
-                ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
-		${MTK_PLAT}/common/drivers/uart/uart.c                \
-		${MTK_PLAT}/common/lpm/mt_lp_rm.c                     \
-                ${MTK_PLAT}/common/mtk_cirq.c                         \
                 ${MTK_PLAT}/common/mtk_plat_common.c                  \
                 ${MTK_PLAT}/common/mtk_sip_svc.c                      \
                 ${MTK_PLAT}/common/params_setup.c                     \
+                ${MTK_PLAT}/drivers/cirq/mt_cirq.c                    \
+                ${MTK_PLAT}/drivers/dp/mt_dp.c                        \
+                ${MTK_PLAT}/drivers/gic600/mt_gic_v3.c                \
+                ${MTK_PLAT}/drivers/gpio/mtgpio_common.c              \
+                ${MTK_PLAT}/drivers/lpm/mt_lp_rm.c                    \
+                ${MTK_PLAT}/drivers/pmic/pmic.c                       \
+                ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init_v2.c     \
+                ${MTK_PLAT}/drivers/rtc/rtc_common.c                  \
+                ${MTK_PLAT}/drivers/rtc/rtc_mt6359p.c                 \
+                ${MTK_PLAT}/drivers/timer/mt_timer.c                  \
+                ${MTK_PLAT}/drivers/uart/uart.c                       \
                 ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
                 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                 ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
                 ${MTK_PLAT_SOC}/drivers/apusys/apupll.c               \
                 ${MTK_PLAT_SOC}/drivers/apusys/apupwr_clkctl.c        \
-		${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c           \
+                ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c           \
                 ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c                 \
                 ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c           \
                 ${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c                \
-                ${MTK_PLAT_SOC}/drivers/dp/mt_dp.c                    \
                 ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c             \
                 ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c              \
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c          \
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c                \
-		${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c        \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c        \
                 ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
-                ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
                 ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c          \
                 ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
                 ${MTK_PLAT_SOC}/plat_pm.c                             \
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index b425fa5..7203de8 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -357,6 +357,9 @@
 endif
 
 ifeq (${STM32MP_SPI_NOR},1)
+ifneq (${STM32MP_FORCE_MTD_START_OFFSET},)
+$(eval $(call add_define_val,STM32MP_NOR_FIP_OFFSET,${STM32MP_FORCE_MTD_START_OFFSET}))
+endif
 BL2_SOURCES		+=	drivers/mtd/nor/spi_nor.c
 endif
 
@@ -366,6 +369,9 @@
 endif
 
 ifneq ($(filter 1,${STM32MP_RAW_NAND} ${STM32MP_SPI_NAND}),)
+ifneq (${STM32MP_FORCE_MTD_START_OFFSET},)
+$(eval $(call add_define_val,STM32MP_NAND_FIP_OFFSET,${STM32MP_FORCE_MTD_START_OFFSET}))
+endif
 BL2_SOURCES		+=	drivers/mtd/nand/core.c
 endif
 
diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c
index b05de1c..3a8a27a 100644
--- a/plat/st/stm32mp1/stm32mp1_boot_device.c
+++ b/plat/st/stm32mp1/stm32mp1_boot_device.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <assert.h>
 #include <errno.h>
 
 #include <common/debug.h>
@@ -15,9 +16,21 @@
 #include <plat/common/platform.h>
 
 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND
+#if STM32MP13
+void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size)
+{
+	assert(buffer_addr != NULL);
+	assert(buf_size != NULL);
+
+	*buffer_addr = (void *)STM32MP_MTD_BUFFER;
+	*buf_size = PLATFORM_MTD_MAX_PAGE_SIZE;
+}
+#endif
+
 static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc)
 {
 	uint32_t nand_param;
+	uint32_t nand2_param __maybe_unused;
 
 	/* Check if NAND parameters are stored in OTP */
 	if (stm32_get_otp_value(NAND_OTP, &nand_param) != 0) {
@@ -26,12 +39,39 @@
 	}
 
 	if (nand_param == 0U) {
+#if STM32MP13
+		if (is_slc) {
+			return 0;
+		}
+#endif
+#if STM32MP15
 		return 0;
+#endif
 	}
 
 	if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) {
+#if STM32MP13
+		if (is_slc) {
+			goto ecc;
+		}
+#endif
+#if STM32MP15
 		goto ecc;
+#endif
+	}
+
+#if STM32MP13
+	if (stm32_get_otp_value(NAND2_OTP, &nand2_param) != 0) {
+		ERROR("BSEC: NAND_OTP Error\n");
+		return -EACCES;
+	}
+
+	/* Check OTP configuration for this device */
+	if ((((nand2_param & NAND2_CONFIG_DISTRIB) == NAND2_PNAND_NAND1_SNAND_NAND2) && !is_slc) ||
+	    (((nand2_param & NAND2_CONFIG_DISTRIB) == NAND2_PNAND_NAND2_SNAND_NAND1) && is_slc)) {
+		nand_param = nand2_param << (NAND_PAGE_SIZE_SHIFT - NAND2_PAGE_SIZE_SHIFT);
 	}
+#endif
 
 	/* NAND parameter shall be read from OTP */
 	if ((nand_param & NAND_WIDTH_MASK) != 0U) {
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 542895a..116bd5d 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -194,6 +194,12 @@
 /* Define maximum page size for NAND devices */
 #define PLATFORM_MTD_MAX_PAGE_SIZE	U(0x1000)
 
+/* Define location for the MTD scratch buffer */
+#if STM32MP13
+#define STM32MP_MTD_BUFFER		(SRAM1_BASE + \
+					 SRAM1_SIZE - \
+					 PLATFORM_MTD_MAX_PAGE_SIZE)
+#endif
 /*******************************************************************************
  * STM32MP1 device/io map related constants (used for MMU)
  ******************************************************************************/
@@ -436,7 +442,13 @@
 #define PACKAGE_OTP			"package_otp"
 #endif
 #define HW2_OTP				"hw2_otp"
+#if STM32MP13
+#define NAND_OTP			"cfg9_otp"
+#define NAND2_OTP			"cfg10_otp"
+#endif
+#if STM32MP15
 #define NAND_OTP			"nand_otp"
+#endif
 #define MONOTONIC_OTP			"monotonic_otp"
 #define UID_OTP				"uid_otp"
 #define BOARD_ID_OTP			"board_id"
@@ -496,7 +508,7 @@
 #define NAND_BLOCK_SIZE_128_PAGES	U(1)
 #define NAND_BLOCK_SIZE_256_PAGES	U(2)
 
-/* NAND number of block (in unit of 256 blocs) */
+/* NAND number of block (in unit of 256 blocks) */
 #define NAND_BLOCK_NB_MASK		GENMASK_32(26, 19)
 #define NAND_BLOCK_NB_SHIFT		19
 #define NAND_BLOCK_NB_UNIT		U(256)
@@ -517,6 +529,14 @@
 /* NAND number of planes */
 #define NAND_PLANE_BIT_NB_MASK		BIT(14)
 
+/* NAND2 OTP */
+#define NAND2_PAGE_SIZE_SHIFT		16
+
+/* NAND2 config distribution */
+#define NAND2_CONFIG_DISTRIB		BIT(0)
+#define NAND2_PNAND_NAND2_SNAND_NAND1	U(0)
+#define NAND2_PNAND_NAND1_SNAND_NAND2	U(1)
+
 /* MONOTONIC OTP */
 #define MAX_MONOTONIC_VALUE		32
 
diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h
index 82e53db..5652597 100644
--- a/plat/st/stm32mp1/stm32mp1_fip_def.h
+++ b/plat/st/stm32mp1/stm32mp1_fip_def.h
@@ -106,7 +106,11 @@
  * STM32MP1 RAW partition offset for devices without GPT
  ******************************************************************************/
 #define STM32MP_EMMC_BOOT_FIP_OFFSET	U(0x00040000)
+#ifndef STM32MP_NOR_FIP_OFFSET
 #define STM32MP_NOR_FIP_OFFSET		U(0x00080000)
+#endif
+#ifndef STM32MP_NAND_FIP_OFFSET
 #define STM32MP_NAND_FIP_OFFSET		U(0x00200000)
+#endif
 
 #endif /* STM32MP1_FIP_DEF_H */