diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 8b513ef..83e5083 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,9 +18,9 @@
 #define PLATFORM_STACK_SIZE	0x440
 
 #define PLATFORM_CORE_COUNT		U(2)
-#define PLAT_MAX_PWR_LVL		1
-#define PLAT_MAX_RET_STATE		1
-#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_PWR_LVL		U(1)
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(2)
 
 /*******************************************************************************
  * BL31 specific defines.
@@ -31,8 +31,8 @@
  * little space for growth.
  */
 #ifndef VERSAL_ATF_MEM_BASE
-# define BL31_BASE			0xfffe0000
-# define BL31_LIMIT			0xffffffff
+# define BL31_BASE			U(0xfffe0000)
+# define BL31_LIMIT			U(0xffffffff)
 #else
 # define BL31_BASE			(VERSAL_ATF_MEM_BASE)
 # define BL31_LIMIT			(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE - 1)
@@ -45,8 +45,8 @@
  * BL32 specific defines.
  ******************************************************************************/
 #ifndef VERSAL_BL32_MEM_BASE
-# define BL32_BASE			0x60000000
-# define BL32_LIMIT			0x7fffffff
+# define BL32_BASE			U(0x60000000)
+# define BL32_LIMIT			U(0x7fffffff)
 #else
 # define BL32_BASE			(VERSAL_BL32_MEM_BASE)
 # define BL32_LIMIT			(VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE - 1)
@@ -56,7 +56,7 @@
  * BL33 specific defines.
  ******************************************************************************/
 #ifndef PRELOADED_BL33_BASE
-# define PLAT_ARM_NS_IMAGE_BASE		0x8000000
+# define PLAT_ARM_NS_IMAGE_BASE		U(0x8000000)
 #else
 # define PLAT_ARM_NS_IMAGE_BASE		PRELOADED_BL33_BASE
 #endif
@@ -81,8 +81,8 @@
 #define CACHE_WRITEBACK_SHIFT	6
 #define CACHE_WRITEBACK_GRANULE	(1 << CACHE_WRITEBACK_SHIFT)
 
-#define PLAT_VERSAL_GICD_BASE	0xF9000000
-#define PLAT_VERSAL_GICR_BASE	0xF9080000
+#define PLAT_VERSAL_GICD_BASE	U(0xF9000000)
+#define PLAT_VERSAL_GICR_BASE	U(0xF9080000)
 
 /*
  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
@@ -91,7 +91,7 @@
  */
 #define PLAT_VERSAL_G1S_IRQS	VERSAL_IRQ_SEC_PHY_TIMER
 #define PLAT_VERSAL_G0_IRQS	VERSAL_IRQ_SEC_PHY_TIMER
-#define PLAT_VERSAL_IPI_IRQ	62
+#define PLAT_VERSAL_IPI_IRQ	U(62)
 
 #define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
 	INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index e8f9a82..3319ac2 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -127,18 +127,18 @@
 #define PMC_GLOBAL_GLOB_GEN_STORAGE4	(PMC_GLOBAL_BASE + 0x40U)
 
 /* IPI registers and bitfields */
-#define IPI0_REG_BASE		0xFF330000
+#define IPI0_REG_BASE		U(0xFF330000)
 #define IPI0_TRIG_BIT		(1 << 2)
 #define PMC_IPI_TRIG_BIT	(1 << 1)
-#define IPI1_REG_BASE		0xFF340000
+#define IPI1_REG_BASE		U(0xFF340000)
 #define IPI1_TRIG_BIT		(1 << 3)
-#define IPI2_REG_BASE		0xFF350000
+#define IPI2_REG_BASE		U(0xFF350000)
 #define IPI2_TRIG_BIT		(1 << 4)
-#define IPI3_REG_BASE		0xFF360000
+#define IPI3_REG_BASE		U(0xFF360000)
 #define IPI3_TRIG_BIT		(1 << 5)
-#define IPI4_REG_BASE		0xFF370000
+#define IPI4_REG_BASE		U(0xFF370000)
 #define IPI4_TRIG_BIT		(1 << 5)
-#define IPI5_REG_BASE		0xFF380000
+#define IPI5_REG_BASE		U(0xFF380000)
 #define IPI5_TRIG_BIT		(1 << 6)
 
 #endif /* VERSAL_DEF_H */
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 07d2534..e7bf8f8 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -21,7 +21,7 @@
 
 static int versal_pwr_domain_on(u_register_t mpidr)
 {
-	unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
+	int cpu_id = plat_core_pos_by_mpidr(mpidr);
 	const struct pm_proc *proc;
 
 	VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
@@ -30,10 +30,10 @@
 		return PSCI_E_INTERN_FAIL;
 	}
 
-	proc = pm_get_proc(cpu_id);
+	proc = pm_get_proc((unsigned int)cpu_id);
 
 	/* Send request to PMC to wake up selected ACPU core */
-	pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFF) | 0x1,
+	pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
 		      versal_sec_entry >> 32, 0, SECURE_FLAG);
 
 	/* Clear power down request */
@@ -54,7 +54,7 @@
 	unsigned int cpu_id = plat_my_core_pos();
 	const struct pm_proc *proc = pm_get_proc(cpu_id);
 
-	for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
+	for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
 		VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
 			__func__, i, target_state->pwr_domain_state[i]);
 	}
@@ -91,7 +91,7 @@
 	unsigned int cpu_id = plat_my_core_pos();
 	const struct pm_proc *proc = pm_get_proc(cpu_id);
 
-	for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
+	for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
 		VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
 			__func__, i, target_state->pwr_domain_state[i]);
 	}
@@ -159,7 +159,7 @@
 	unsigned int cpu_id = plat_my_core_pos();
 	const struct pm_proc *proc = pm_get_proc(cpu_id);
 
-	for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
+	for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
 		VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
 			__func__, i, target_state->pwr_domain_state[i]);
 	}
diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c
index bc7d8b7..2649e18 100644
--- a/plat/xilinx/versal/sip_svc_setup.c
+++ b/plat/xilinx/versal/sip_svc_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,9 +14,9 @@
 #include "pm_svc_main.h"
 
 /* SMC function IDs for SiP Service queries */
-#define VERSAL_SIP_SVC_CALL_COUNT	0x8200ff00
-#define VERSAL_SIP_SVC_UID		0x8200ff01
-#define VERSAL_SIP_SVC_VERSION		0x8200ff03
+#define VERSAL_SIP_SVC_CALL_COUNT	U(0x8200ff00)
+#define VERSAL_SIP_SVC_UID		U(0x8200ff01)
+#define VERSAL_SIP_SVC_VERSION		U(0x8200ff03)
 
 /* SiP Service Calls version numbers */
 #define SIP_SVC_VERSION_MAJOR	0
diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index 27541ff..f99af82 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,49 +24,49 @@
 	[IPI_ID_APU] = {
 		.ipi_bit_mask = IPI0_TRIG_BIT,
 		.ipi_reg_base = IPI0_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* PMC IPI */
 	[IPI_ID_PMC] = {
 		.ipi_bit_mask = PMC_IPI_TRIG_BIT,
 		.ipi_reg_base = IPI0_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* RPU0 IPI */
 	[IPI_ID_RPU0] = {
 		.ipi_bit_mask = IPI1_TRIG_BIT,
 		.ipi_reg_base = IPI1_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* RPU1 IPI */
 	[IPI_ID_RPU1] = {
 		.ipi_bit_mask = IPI2_TRIG_BIT,
 		.ipi_reg_base = IPI2_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* IPI3 IPI */
 	[IPI_ID_3] = {
 		.ipi_bit_mask = IPI3_TRIG_BIT,
 		.ipi_reg_base = IPI3_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* IPI4 IPI */
 	[IPI_ID_4] = {
 		.ipi_bit_mask = IPI4_TRIG_BIT,
 		.ipi_reg_base = IPI4_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* IPI5 IPI */
 	[IPI_ID_5] = {
 		.ipi_bit_mask = IPI5_TRIG_BIT,
 		.ipi_reg_base = IPI5_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 };