diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index 27541ff..f99af82 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,49 +24,49 @@
 	[IPI_ID_APU] = {
 		.ipi_bit_mask = IPI0_TRIG_BIT,
 		.ipi_reg_base = IPI0_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* PMC IPI */
 	[IPI_ID_PMC] = {
 		.ipi_bit_mask = PMC_IPI_TRIG_BIT,
 		.ipi_reg_base = IPI0_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* RPU0 IPI */
 	[IPI_ID_RPU0] = {
 		.ipi_bit_mask = IPI1_TRIG_BIT,
 		.ipi_reg_base = IPI1_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* RPU1 IPI */
 	[IPI_ID_RPU1] = {
 		.ipi_bit_mask = IPI2_TRIG_BIT,
 		.ipi_reg_base = IPI2_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* IPI3 IPI */
 	[IPI_ID_3] = {
 		.ipi_bit_mask = IPI3_TRIG_BIT,
 		.ipi_reg_base = IPI3_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* IPI4 IPI */
 	[IPI_ID_4] = {
 		.ipi_bit_mask = IPI4_TRIG_BIT,
 		.ipi_reg_base = IPI4_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 
 	/* IPI5 IPI */
 	[IPI_ID_5] = {
 		.ipi_bit_mask = IPI5_TRIG_BIT,
 		.ipi_reg_base = IPI5_REG_BASE,
-		.secure_only = 0,
+		.secure_only = 0U,
 	},
 };