tree 64d0768297c21d2600bb043234edf345ace2dd60
parent 16e5ca2d2638452ebd7482f21191c3580429a868
author Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> 1681222531 +0100
committer Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> 1690446912 +0100

refactor(cpus): convert the Cortex-A510 to use the errata framework

This involves replacing:
 * the reset_func with the standard cpu_reset_func_{start,end} to apply
   errata automatically
 * the <cpu>_errata_report with the errata_report_shim to report errata
   automatically
...and for each erratum:
 * the prologue with the workaround_<type>_start to do the checks and
   framework registration automatically
 * the epilogue with the workaround_<type>_end
 * the checker function with the check_erratum_<type> to make it more
   descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Note: cortex_a510.S is applicable and being used only by arm_fpga platform.

However, to test the ported changes, below steps were carried out on the
fvp and the obtained results has been verified.

Testing was conducted by:
 * Building for release with all errata flags enabled and running script
   in change 19136 to compare output of objdump for each errata.

 * Testing via script was not complete, as it directed to verify the
   check and the workaround functions of few erratas manually.

 * Manual comparison of disassembly of converted functions with non-
   converted functions

   aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/../release/bl31/bl31.elf
     vs
   aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

 * Manual comparison of disassembly of both both files(bl31.elf)
   ensured, the ported changes were identical and hence verified.

 * Build for release with all errata flags enabled and run default
   tftf tests.

   CROSS_COMPILE=aarch64-none-elf- \
   make PLAT=fvp \
   ARCH=aarch64 \
   DEBUG=0 \
   HW_ASSISTED_COHERENCY=1 \
   USE_COHERENT_MEM=0 \
   CTX_INCLUDE_AARCH32_REGS=0 \
   ERRATA_A510_1922240=1 \
   ERRATA_A510_2288014=1 \
   ERRATA_A510_2042739=1 \
   ERRATA_A510_2041909=1 \
   ERRATA_A510_2250311=1 \
   ERRATA_A510_2218950=1 \
   ERRATA_A510_2172148=1 \
   ERRATA_A510_2347730=1 \
   ERRATA_A510_2371937=1 \
   ERRATA_A510_2666669=1 \
   ERRATA_A510_2684597=1 \
   ERRATA_DSU_2313941=1 \
   BL33=/home/jaychi01/tf_a/tf-a-tests/build/fvp/release/tftf.bin \
   fip all -j12

 * Build for debug with all errata enabled and step through ArmDS
   at reset to ensure that if Errata are applicable then the
   workaround functions are entered precisely.

Change-Id: Icf7aa25c0b3b30f5e2ad6db83953f7f4f0b201d9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>