fix(dt-bindings): update STM32MP2 clock and reset bindings
Fix some clocks and reset binding values.
Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
diff --git a/include/dt-bindings/clock/stm32mp25-clks.h b/include/dt-bindings/clock/stm32mp25-clks.h
index c4ff9cf..e7ab5b0 100644
--- a/include/dt-bindings/clock/stm32mp25-clks.h
+++ b/include/dt-bindings/clock/stm32mp25-clks.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
- * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
+ * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
*/
#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_
@@ -109,7 +109,7 @@
/* LOW SPEED MCU CLOCK */
#define CK_ICN_LS_MCU 88
-#define CK_BUS_STM500 89
+#define CK_BUS_STM 89
#define CK_BUS_FMC 90
#define CK_BUS_GPU 91
#define CK_BUS_ETH1 92
@@ -233,7 +233,6 @@
#define CK_BUS_DDRCFG 210
#define CK_BUS_GICV2M 211
#define CK_BUS_USBTC 212
-#define CK_BUS_BUSPERFM 213
#define CK_BUS_USB3PCIEPHY 214
#define CK_BUS_STGEN 215
#define CK_BUS_VDEC 216
@@ -272,7 +271,7 @@
#define CK_BUS_RISAF4 249
#define CK_BUS_USB2OHCI 250
#define CK_BUS_USB2EHCI 251
-#define CK_BUS_USB3DRD 252
+#define CK_BUS_USB3DR 252
#define CK_KER_LPTIM1 253
#define CK_KER_LPTIM2 254
#define CK_KER_USART2 255
@@ -364,8 +363,10 @@
#define CK_BUS_ETHSWACMCFG 341
#define CK_BUS_ETHSWACMMSG 342
#define HSE_DIV2_CK 343
+#define CK_KER_ETR 344
+#define CK_KER_STM 345
-#define STM32MP25_LAST_CLK 344
+#define STM32MP25_LAST_CLK 346
#define CK_SCMI_ICN_HS_MCU 0
#define CK_SCMI_ICN_SDMMC 1
@@ -453,8 +454,7 @@
#define CK_SCMI_TIMG2 83
#define CK_SCMI_BKPSRAM 84
#define CK_SCMI_BSEC 85
-#define CK_SCMI_BUSPERFM 86
-#define CK_SCMI_ETR 87
+#define CK_SCMI_BUS_ETR 87
#define CK_SCMI_FMC 88
#define CK_SCMI_GPIOA 89
#define CK_SCMI_GPIOB 90
@@ -489,6 +489,8 @@
#define CK_SCMI_SYSDBG 119
#define CK_SCMI_SYSATB 120
#define CK_SCMI_TSDBG 121
-#define CK_SCMI_STM500 122
+#define CK_SCMI_BUS_STM 122
+#define CK_SCMI_KER_STM 123
+#define CK_SCMI_KER_ETR 124
#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp25-clksrc.h b/include/dt-bindings/clock/stm32mp25-clksrc.h
index e6f7154..319fd82 100644
--- a/include/dt-bindings/clock/stm32mp25-clksrc.h
+++ b/include/dt-bindings/clock/stm32mp25-clksrc.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
- * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
@@ -108,9 +108,8 @@
#define MUX_DSIPHY 18
#define MUX_LVDSPHY 19
#define MUX_DTS 20
-#define MUX_CPU1 21
-#define MUX_D3PER 22
-#define MUX_NB 23
+#define MUX_D3PER 21
+#define MUX_NB 22
#define MUXSEL_HSI 0
#define MUXSEL_HSE 1
@@ -144,7 +143,7 @@
#define MUX_USB3PCIEPHY_FLEX34 0x0
#define MUX_USB3PCIEPHY_HSE 0x1
-#define MUX_DSIBLANE_FLEX28 0x0
+#define MUX_DSIBLANE_DSIPHY 0x0
#define MUX_DSIBLANE_FLEX27 0x1
#define MUX_DSIPHY_FLEX28 0x0
@@ -219,8 +218,8 @@
/* define for st,drive */
#define LSEDRV_LOWEST 0
-#define LSEDRV_MEDIUM_LOW 1
-#define LSEDRV_MEDIUM_HIGH 2
+#define LSEDRV_MEDIUM_LOW 2
+#define LSEDRV_MEDIUM_HIGH 1
#define LSEDRV_HIGHEST 3
#endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */
diff --git a/include/dt-bindings/reset/stm32mp25-resets.h b/include/dt-bindings/reset/stm32mp25-resets.h
index c34fe2a..99b8058 100644
--- a/include/dt-bindings/reset/stm32mp25-resets.h
+++ b/include/dt-bindings/reset/stm32mp25-resets.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
/*
- * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
* Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
@@ -14,16 +14,16 @@
#define C2_R 8288
#define C2_HOLDBOOT_R 8608
#define C1_HOLDBOOT_R 8609
-#define VSW_R 8703
-#define C1MS_R 8808
-#define IWDG2_KER_R 9074
-#define IWDG4_KER_R 9202
-#define C3_R 9312
-#define DDRCP_R 9856
-#define DDRCAPB_R 9888
-#define DDRPHYCAPB_R 9920
-#define DDRCFG_R 9984
-#define DDR_R 10016
+#define VSW_R 8735
+#define C1MS_R 8840
+#define IWDG2_KER_R 9106
+#define IWDG4_KER_R 9234
+#define C3_R 9344
+#define DDRCP_R 9888
+#define DDRCAPB_R 9920
+#define DDRPHYCAPB_R 9952
+#define DDRCFG_R 10016
+#define DDR_R 10048
#define OSPI1_R 10400
#define OSPI1DLL_R 10416
#define OSPI2_R 10432
@@ -115,7 +115,7 @@
#define USB2_R 16352
#define USB2PHY1_R 16384
#define USB2PHY2_R 16416
-#define USB3DRD_R 16448
+#define USB3DR_R 16448
#define USB3PCIEPHY_R 16480
#define PCIE_R 16512
#define USBTC_R 16544
@@ -143,7 +143,6 @@
#define CRYP2_R 17440
#define WWDG1_R 17632
#define WWDG2_R 17664
-#define BUSPERFM_R 17696
#define VREF_R 17728
#define DTS_R 17760
#define CRC_R 17824
@@ -159,6 +158,9 @@
#define RST_SCMI_C1_HOLDBOOT_R 2
#define RST_SCMI_C2_HOLDBOOT_R 3
#define RST_SCMI_FMC 4
-#define RST_SCMI_PCIE 5
+#define RST_SCMI_OSPI1 5
+#define RST_SCMI_OSPI1DLL 6
+#define RST_SCMI_OSPI2 7
+#define RST_SCMI_OSPI2DLL 8
#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */