commit 56ff58f9718f50c881c76ebac05cf8aff18b4970
author Yidi Lin <yidilin@chromium.org> Fri Jul 08 16:16:09 2022 +0800
committer Yidi Lin <yidilin@chromium.org> Tue Jul 19 15:56:19 2022 +0800
tree f7da4587d552f6f6bec9fd3c6602b6a8010d4c6b
parent a57cbff78d7a8f4daede952ead6e9c14f151df5d

fix(mt8186): move SSPM base register definition to platform_def.h

- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.

Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ibb0291ce7b7426068392e90bd70f29d1a90d5297

plat/mediatek/mt8186/include/platform_def.h

diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h
index b8b877a..f3d15f3 100644
--- a/plat/mediatek/mt8186/include/platform_def.h
+++ b/plat/mediatek/mt8186/include/platform_def.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,6 +26,8 @@
 #define INFRACFG_AO_BASE        (IO_PHYS + 0x00001000)
 #define SPM_BASE		(IO_PHYS + 0x00006000)
 #define APMIXEDSYS              (IO_PHYS + 0x0000C000)
+#define SSPM_MCDI_SHARE_SRAM    (IO_PHYS + 0x00420000)
+#define SSPM_CFGREG_BASE        (IO_PHYS + 0x00440000)  /* SSPM view: 0x30040000 */
 #define SSPM_MBOX_BASE          (IO_PHYS + 0x00480000)
 #define PERICFG_AO_BASE         (IO_PHYS + 0x01003000)
 #define VPPSYS0_BASE            (IO_PHYS + 0x04000000)