tree cdcd89d54630342a71882352db4ed88835f6dcf1
parent e09e93137f5d840649ea64d2a4bd801f58be556c
author Masahiro Yamada <yamada.masahiro@socionext.com> 1580726800 +0900
committer Masahiro Yamada <yamada.masahiro@socionext.com> 1582707311 +0900

uniphier: prepare uniphier_soc_info() for next SoC

The revision register address will be changed in the next SoC.

The LSI revision is needed in order to know where the revision
register is located, but you need to read out the revision
register for that. This is impossible.

We need to know the revision register address by other means.
Use BL_CODE_BASE, where the base address of the TF image that is
currently running. If it is bigger than 0x80000000 (i.e. the DRAM
base is 0x80000000), we assume it is a legacy SoC.

Change-Id: I9d7f4325fe2085a8a1ab5310025e5948da611256
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>