fix(intel): bit-wise configuration flag handling
Change configuration type handling to bit-wise flag. This is to align
with Linux's FPGA Manager definitions and promotes better compatibility.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I5aaf91d3fec538fe3f4fe8395d9adb47ec969434
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index aab7bbf..2917d0a 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -27,6 +27,12 @@
#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
+/* FPGA Bitstream Flag */
+#define FLAG_PARTIAL_CONFIG BIT(0)
+#define FLAG_AUTHENTICATION BIT(1)
+#define CONFIG_TEST_FLAG(_flag, _type) (((flag) & FLAG_##_type) \
+ == FLAG_##_type)
+
/* Secure Register Access */
#define INTEL_SIP_SMC_REG_READ 0xC2000007
#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
@@ -60,21 +66,21 @@
/* ECC DBE */
#define WARM_RESET_WFI_FLAG BIT(31)
-#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
+#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
SYSMGR_ECC_DDR0_MASK |\
SYSMGR_ECC_DDR1_MASK)
/* Non-mailbox SMC Call */
-#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
+#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
/* SMC function IDs for SiP Service queries */
-#define SIP_SVC_CALL_COUNT 0x8200ff00
-#define SIP_SVC_UID 0x8200ff01
-#define SIP_SVC_VERSION 0x8200ff03
+#define SIP_SVC_CALL_COUNT 0x8200ff00
+#define SIP_SVC_UID 0x8200ff01
+#define SIP_SVC_VERSION 0x8200ff03
/* SiP Service Calls version numbers */
-#define SIP_SVC_VERSION_MAJOR 1
-#define SIP_SVC_VERSION_MINOR 0
+#define SIP_SVC_VERSION_MAJOR 1
+#define SIP_SVC_VERSION_MINOR 0
/* Structure Definitions */
@@ -87,11 +93,6 @@
int block_number;
};
-typedef enum {
- FULL_CONFIG = 0,
- PARTIAL_CONFIG,
-} config_type;
-
/* Function Definitions */
bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 77b91b2..56a88ab 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -23,7 +23,7 @@
static int read_block, max_blocks;
static uint32_t send_id, rcv_id;
static uint32_t bytes_per_block, blocks_submitted;
-static bool is_full_reconfig;
+static bool bridge_disable;
/* RSU static variables */
static uint32_t rsu_dcmf_ver[4] = {0};
@@ -102,10 +102,9 @@
return INTEL_SIP_SMC_STATUS_ERROR;
}
- if (query_type != 1) {
- /* full reconfiguration */
- if (is_full_reconfig)
- socfpga_bridges_enable(); /* Enable bridge */
+ if (bridge_disable) {
+ socfpga_bridges_enable(); /* Enable bridge */
+ bridge_disable = false;
}
return INTEL_SIP_SMC_STATUS_OK;
@@ -191,7 +190,7 @@
return status;
}
-static int intel_fpga_config_start(uint32_t type)
+static int intel_fpga_config_start(uint32_t flag)
{
uint32_t argument = 0x1;
uint32_t response[3];
@@ -199,10 +198,15 @@
unsigned int size = 0;
unsigned int resp_len = ARRAY_SIZE(response);
- if ((config_type)type == FULL_CONFIG) {
- is_full_reconfig = true;
+ if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
+ bridge_disable = true;
}
+ if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
+ size = 1;
+ bridge_disable = false;
+ }
+
mailbox_clear_response();
mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
@@ -212,6 +216,7 @@
CMD_CASUAL, response, &resp_len);
if (status < 0) {
+ bridge_disable = false;
return INTEL_SIP_SMC_STATUS_ERROR;
}
@@ -232,9 +237,8 @@
read_block = 0;
current_buffer = 0;
- /* full reconfiguration */
- if (is_full_reconfig) {
- /* Disable bridge */
+ /* Disable bridge on full reconfiguration */
+ if (bridge_disable) {
socfpga_bridges_disable();
}