tree d0e0ab1418d5df9b075b361d53f2e5ab405f9f87
parent dc8e82e362313b0d77791700c16b9074d0dca647
author Lin Huang <hl@rock-chips.com> 1481785727 +0800
committer Xing Zheng <zhengxing@rock-chips.com> 1487938064 +0800

rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0

The phy pll needs to get 2X frequency to the DDR, so set the
pll_postdiv to 0.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>