diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index c410a8e..953a92e 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -519,6 +519,20 @@
    Firmware as error. It can take the value 1 (flag the use of deprecated
    APIs as error) or 0. The default is 0.
 
+-  ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
+   configure an Arm® Ethos™-N NPU. To use this service the target platform's
+   ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
+   the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
+   only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
+
+-  ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the
+   Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and
+   ``TRUSTED_BOARD_BOOT`` to be enabled.
+
+-  ``ETHOSN_NPU_FW``: location of the NPU firmware binary
+   (```ethosn.bin```). This firmware image will be included in the FIP and
+   loaded at runtime.
+
 -  ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
    targeted at EL3. When set ``0`` (default), no exceptions are expected or
    handled at EL3, and a panic will result. The exception to this rule is when
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index 3179267..e81052b 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -95,20 +95,6 @@
    platforms. If this option is specified, then the path to the CryptoCell
    SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
 
--  ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
-   configure an Arm® Ethos™-N NPU. To use this service the target platform's
-   ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
-   the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
-   only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
-
--  ``ARM_ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the
-   Arm® Ethos™-N NPU. Requires ``ARM_ETHOSN_NPU_DRIVER`` and
-   ``TRUSTED_BOARD_BOOT`` to be enabled.
-
--  ``ARM_ETHOSN_NPU_FW``: location of the NPU firmware binary
-   (```ethosn.bin```). This firmware image will be included in the FIP and
-   loaded at runtime.
-
 -  ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of
    the various partitions present in the GPT image. This support is available
    only for the BL2 component, and it is disabled by default.
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index f074021..5a017ce 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -591,32 +591,32 @@
 If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support
 enabled, the following constants and configuration must also be defined:
 
-- **ARM_ETHOSN_NPU_PROT_FW_NSAID**
+- **ETHOSN_NPU_PROT_FW_NSAID**
 
   Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to
   access the protected memory that contains the NPU's firmware.
 
-- **ARM_ETHOSN_NPU_PROT_DATA_RW_NSAID**
+- **ETHOSN_NPU_PROT_DATA_RW_NSAID**
 
   Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
   read/write access to the protected memory that contains inference data.
 
-- **ARM_ETHOSN_NPU_PROT_DATA_RO_NSAID**
+- **ETHOSN_NPU_PROT_DATA_RO_NSAID**
 
   Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
   read-only access to the protected memory that contains inference data.
 
-- **ARM_ETHOSN_NPU_NS_RW_DATA_NSAID**
+- **ETHOSN_NPU_NS_RW_DATA_NSAID**
 
   Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
   read/write access to the non-protected memory.
 
-- **ARM_ETHOSN_NPU_NS_RO_DATA_NSAID**
+- **ETHOSN_NPU_NS_RO_DATA_NSAID**
 
   Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for
   read-only access to the non-protected memory.
 
-- **ARM_ETHOSN_NPU_FW_IMAGE_BASE** and **ARM_ETHOSN_NPU_FW_IMAGE_LIMIT**
+- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT**
 
   Defines the physical address range that the NPU's firmware will be loaded
   into and executed from.
@@ -634,10 +634,10 @@
 - Add MMU mappings such that:
 
  - BL2 can write the NPU firmware into the region defined by
-   ``ARM_ETHOSN_NPU_FW_IMAGE_BASE`` and ``ARM_ETHOSN_NPU_FW_IMAGE_LIMIT``
+   ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT``
  - BL31 (SiP service) can read the NPU firmware from the same region
 
-- Add the firmware image ID ``ARM_ETHOSN_NPU_FW_IMAGE_ID`` to the list of images
+- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images
   loaded by BL2.
 
 Please see the reference implementation code for the Juno platform as an example.
diff --git a/drivers/arm/ethosn/ethosn_npu.mk b/drivers/arm/ethosn/ethosn_npu.mk
new file mode 100644
index 0000000..4a31b59
--- /dev/null
+++ b/drivers/arm/ethosn/ethosn_npu.mk
@@ -0,0 +1,49 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Arm(R) Ethos(TM)-N NPU SiP service
+ETHOSN_NPU_DRIVER			:=	0
+
+$(eval $(call assert_boolean,ETHOSN_NPU_DRIVER))
+$(eval $(call add_define,ETHOSN_NPU_DRIVER))
+
+#Ethos-N NPU TZMP1
+ETHOSN_NPU_TZMP1			:=	0
+$(eval $(call assert_boolean,ETHOSN_NPU_TZMP1))
+$(eval $(call add_define,ETHOSN_NPU_TZMP1))
+ifeq (${ETHOSN_NPU_TZMP1},1)
+  ifeq (${ETHOSN_NPU_DRIVER},0)
+    $(error "ETHOSN_NPU_TZMP1 is only available if ETHOSN_NPU_DRIVER=1)
+  endif
+  ifeq (${PLAT},juno)
+    $(eval $(call add_define,JUNO_ETHOSN_TZMP1))
+  else
+    $(error "ETHOSN_NPU_TZMP1 only supported on Juno platform, not ", ${PLAT})
+  endif
+
+  ifeq (${TRUSTED_BOARD_BOOT},0)
+    # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
+    # tampered with, which is required to protect the confidentiality of protected
+    # inference data.
+    $(error "ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
+  endif
+
+  # We need the FW certificate and key certificate
+  $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
+  $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
+  # We need the firmware to be built into the FIP
+  $(eval $(call TOOL_ADD_IMG,ETHOSN_NPU_FW,--npu-fw))
+
+  # Needed for our OIDs to be available in tbbr_cot_bl2.c
+  $(eval $(call add_define, PLAT_DEF_OID))
+
+  # Needed so that UUIDs from the FIP are available in BL2
+  $(eval $(call add_define,PLAT_DEF_FIP_UUID))
+
+  PLAT_INCLUDES	+=	-I${PLAT_DIR}certificate/include
+  PLAT_INCLUDES	+=	-Iinclude/drivers/arm/
+  PLAT_INCLUDES	+=	-I${PLAT_DIR}fip
+endif
diff --git a/drivers/arm/ethosn/ethosn_smc.c b/drivers/arm/ethosn/ethosn_smc.c
index 85a12c5..42158e4 100644
--- a/drivers/arm/ethosn/ethosn_smc.c
+++ b/drivers/arm/ethosn/ethosn_smc.c
@@ -17,9 +17,9 @@
 
 #include <platform_def.h>
 
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 #include "ethosn_big_fw.h"
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 /*
  * Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available
@@ -51,11 +51,11 @@
 #define SEC_AUXCTLR_STASHING_VAL	U(0xA5000000)
 
 #define SEC_DEL_REG			U(0x0004)
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 #define SEC_DEL_VAL			U(0x808)
 #else
 #define SEC_DEL_VAL			U(0x80C)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 #define SEC_DEL_EXCC_MASK		U(0x20)
 
 #define SEC_SECCTLR_REG			U(0x0010)
@@ -69,7 +69,7 @@
 #define SEC_SYSCTRL0_CPU_WAIT		U(1)
 #define SEC_SYSCTRL0_SLEEPING		U(1U << 4)
 #define SEC_SYSCTRL0_INITVTOR_MASK	U(0x1FFFFF80)
-#define SEC_SYSCTRL0_SOFT_RESET		U(3U << 29)
+#define SEC_SYSCTRL0_SOFT_RESET		U(1U << 29)
 #define SEC_SYSCTRL0_HARD_RESET		U(1U << 31)
 
 #define SEC_SYSCTRL1_REG		U(0x001C)
@@ -104,8 +104,8 @@
 #define TO_EXTEND_ADDR(addr) \
 	((addr >> SEC_ADDR_EXT_SHIFT) & SEC_ADDR_EXT_MASK)
 
-#if ARM_ETHOSN_NPU_TZMP1
-CASSERT(ARM_ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
+#if ETHOSN_NPU_TZMP1
+CASSERT(ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
 static const struct ethosn_big_fw *big_fw;
 
 #define FW_INITVTOR_ADDR(big_fw) \
@@ -115,7 +115,7 @@
 #define SYSCTRL0_INITVTOR_ADDR(value) \
 	(value & SEC_SYSCTRL0_INITVTOR_MASK)
 
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 static bool ethosn_get_device_and_core(uintptr_t core_addr,
 				       const struct ethosn_device_t **dev_match,
@@ -142,7 +142,7 @@
 	return false;
 }
 
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 static uint32_t ethosn_core_read_arch_version(uintptr_t core_addr)
 {
 	uint32_t npu_id = mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr,
@@ -155,23 +155,23 @@
 					  bool is_protected)
 {
 	size_t i;
-	uint32_t streams[9] = {[0 ... 8] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID};
+	uint32_t streams[9] = {[0 ... 8] = ETHOSN_NPU_NS_RO_DATA_NSAID};
 
-	streams[FIRMWARE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
-	streams[PLE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
+	streams[FIRMWARE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID;
+	streams[PLE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID;
 
-	streams[WORKING_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
+	streams[WORKING_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID;
 
 	if (is_protected) {
-		streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID;
+		streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RO_DATA_NSAID;
 		streams[INTERMEDIATE_STREAM_INDEX] =
-			ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
-		streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
+			ETHOSN_NPU_PROT_RW_DATA_NSAID;
+		streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RW_DATA_NSAID;
 	} else {
-		streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID;
+		streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RO_DATA_NSAID;
 		streams[INTERMEDIATE_STREAM_INDEX] =
-			ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
-		streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
+			ETHOSN_NPU_NS_RW_DATA_NSAID;
+		streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID;
 	}
 
 	for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
@@ -188,7 +188,7 @@
 			FW_INITVTOR_ADDR(big_fw));
 }
 
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 static void ethosn_configure_events(uintptr_t core_addr)
 {
@@ -343,7 +343,7 @@
 
 static int ethosn_core_boot_fw(uintptr_t core_addr)
 {
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 	const uintptr_t sysctrl0_reg = ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
 	const uint32_t sysctrl0_val = mmio_read_32(sysctrl0_reg);
 	const bool waiting = (sysctrl0_val & SEC_SYSCTRL0_CPU_WAIT);
@@ -363,7 +363,7 @@
 	return ETHOSN_SUCCESS;
 #else
 	return ETHOSN_NOT_SUPPORTED;
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 }
 
 static int ethosn_core_full_reset(const struct ethosn_device_t *device,
@@ -392,17 +392,17 @@
 	if (!device->has_reserved_memory) {
 		ethosn_configure_smmu_streams(device, core, asset_alloc_idx);
 
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 		ethosn_configure_stream_nsaid(core, is_protected);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 	}
 
 	ethosn_configure_stream_addr_extends(device, core->addr);
 	ethosn_configure_stream_attr_ctlr(core->addr);
 
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 	ethosn_configure_vector_table(core->addr);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 	ethosn_delegate_to_ns(core->addr);
 
@@ -481,7 +481,7 @@
 static uintptr_t ethosn_smc_fw_prop_handler(u_register_t fw_property,
 					    void *handle)
 {
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 	switch (fw_property) {
 	case ETHOSN_FW_PROP_VERSION:
 		SMC_RET4(handle, ETHOSN_SUCCESS,
@@ -507,7 +507,7 @@
 	}
 #else
 	SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 }
 
 uintptr_t ethosn_smc_handler(uint32_t smc_fid,
@@ -554,17 +554,17 @@
 
 int ethosn_smc_setup(void)
 {
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 	struct ethosn_device_t *dev;
 	uint32_t arch_ver;
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 	if (ETHOSN_NUM_DEVICES == 0U) {
 		ERROR("ETHOSN: No NPU found\n");
 		return ETHOSN_FAILURE;
 	}
 
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 
 	/* Only one NPU core is supported in the TZMP1 setup */
 	if ((ETHOSN_NUM_DEVICES != 1U) ||
@@ -580,7 +580,7 @@
 	}
 
 	arch_ver = ethosn_core_read_arch_version(dev->cores[0U].addr);
-	big_fw = (struct ethosn_big_fw *)ARM_ETHOSN_NPU_FW_IMAGE_BASE;
+	big_fw = (struct ethosn_big_fw *)ETHOSN_NPU_FW_IMAGE_BASE;
 
 	if (!ethosn_big_fw_verify_header(big_fw, arch_ver)) {
 		return ETHOSN_FAILURE;
@@ -591,7 +591,7 @@
 	       big_fw->fw_ver_patch);
 #else
 	NOTICE("ETHOSN: Setup succeeded\n");
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 	return 0;
 }
diff --git a/drivers/arm/fvp/fvp_pwrc.c b/drivers/arm/fvp/fvp_pwrc.c
index 75a2b66..fb77f77 100644
--- a/drivers/arm/fvp/fvp_pwrc.c
+++ b/drivers/arm/fvp/fvp_pwrc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,22 +10,39 @@
 #include <plat/arm/common/plat_arm.h>
 #include <platform_def.h>
 
+#define FVP_PWRC_ID_MASK U(0x00FFFFFF)
+
 /*
  * TODO: Someday there will be a generic power controller api. At the moment
  * each platform has its own pwrc so just exporting functions is fine.
  */
 ARM_INSTANTIATE_LOCK;
 
+/*
+ * Core ID field is 24 bits wide and extracted from MPIDR.
+ * Bits[23:16] represent Affinity Level 2
+ * Bits[15:8] represent Affinity Level 1
+ * Bits[7:0] represent Affinity Level 0
+ */
+static unsigned int fvp_pwrc_core_id(u_register_t mpidr)
+{
+	return (unsigned int)(mpidr & FVP_PWRC_ID_MASK);
+}
+
 unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr)
 {
-	return PSYSR_WK(fvp_pwrc_read_psysr(mpidr));
+	unsigned int id = fvp_pwrc_core_id(mpidr);
+
+	return PSYSR_WK(fvp_pwrc_read_psysr(id));
 }
 
 unsigned int fvp_pwrc_read_psysr(u_register_t mpidr)
 {
 	unsigned int rc;
+	unsigned int id = fvp_pwrc_core_id(mpidr);
+
 	arm_lock_get();
-	mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
+	mmio_write_32(PWRC_BASE + PSYSR_OFF, id);
 	rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
 	arm_lock_release();
 	return rc;
@@ -33,38 +50,47 @@
 
 void fvp_pwrc_write_pponr(u_register_t mpidr)
 {
+	unsigned int id = fvp_pwrc_core_id(mpidr);
+
 	arm_lock_get();
-	mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
+	mmio_write_32(PWRC_BASE + PPONR_OFF, id);
 	arm_lock_release();
 }
 
 void fvp_pwrc_write_ppoffr(u_register_t mpidr)
 {
+	unsigned int id = fvp_pwrc_core_id(mpidr);
+
 	arm_lock_get();
-	mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
+	mmio_write_32(PWRC_BASE + PPOFFR_OFF, id);
 	arm_lock_release();
 }
 
 void fvp_pwrc_set_wen(u_register_t mpidr)
 {
+	unsigned int id = fvp_pwrc_core_id(mpidr);
+
 	arm_lock_get();
 	mmio_write_32(PWRC_BASE + PWKUPR_OFF,
-		      (unsigned int) (PWKUPR_WEN | mpidr));
+		      (unsigned int) (PWKUPR_WEN | id));
 	arm_lock_release();
 }
 
 void fvp_pwrc_clr_wen(u_register_t mpidr)
 {
+	unsigned int id = fvp_pwrc_core_id(mpidr);
+
 	arm_lock_get();
-	mmio_write_32(PWRC_BASE + PWKUPR_OFF,
-		      (unsigned int) mpidr);
+	mmio_write_32(PWRC_BASE + PWKUPR_OFF, id);
 	arm_lock_release();
 }
 
 void fvp_pwrc_write_pcoffr(u_register_t mpidr)
 {
+	unsigned int id = fvp_pwrc_core_id(mpidr);
+
 	arm_lock_get();
-	mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
+	mmio_write_32(PWRC_BASE + PCOFFR_OFF, id);
 	arm_lock_release();
 }
 
diff --git a/fdts/juno.dts b/fdts/juno.dts
index 56fe167..8e373e7 100644
--- a/fdts/juno.dts
+++ b/fdts/juno.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,6 @@
 
 };
 
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
 	#include "juno-ethosn.dtsi"
 #endif
diff --git a/include/export/lib/bl_aux_params/bl_aux_params_exp.h b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
index 7391dec..5ae1d64 100644
--- a/include/export/lib/bl_aux_params/bl_aux_params_exp.h
+++ b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h
index 2ee5769..8c58cbb 100644
--- a/include/export/lib/utils_def_exp.h
+++ b/include/export/lib/utils_def_exp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index 2cf2b44..5d165c9 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/bl_aux_params/bl_aux_params.h b/include/lib/bl_aux_params/bl_aux_params.h
index 072a29d..c2da96c 100644
--- a/include/lib/bl_aux_params/bl_aux_params.h
+++ b/include/lib/bl_aux_params/bl_aux_params.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cassert.h b/include/lib/cassert.h
index bbfdfdb..512a2ad 100644
--- a/include/lib/cassert.h
+++ b/include/lib/cassert.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h
index 42d4149..c8e1b2d 100644
--- a/include/lib/coreboot.h
+++ b/include/lib/coreboot.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/aem_generic.h b/include/lib/cpus/aarch32/aem_generic.h
index 1d40cec..f631f26 100644
--- a/include/lib/cpus/aarch32/aem_generic.h
+++ b/include/lib/cpus/aarch32/aem_generic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a12.h b/include/lib/cpus/aarch32/cortex_a12.h
index abacdba..789b4cf 100644
--- a/include/lib/cpus/aarch32/cortex_a12.h
+++ b/include/lib/cpus/aarch32/cortex_a12.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h
index 9526a9c..aca4d34 100644
--- a/include/lib/cpus/aarch32/cortex_a15.h
+++ b/include/lib/cpus/aarch32/cortex_a15.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h
index 89a8eb6..b9e754a 100644
--- a/include/lib/cpus/aarch32/cortex_a17.h
+++ b/include/lib/cpus/aarch32/cortex_a17.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h
index 6ddd533..841898a 100644
--- a/include/lib/cpus/aarch32/cortex_a32.h
+++ b/include/lib/cpus/aarch32/cortex_a32.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a5.h b/include/lib/cpus/aarch32/cortex_a5.h
index 76703b7..c0763f9 100644
--- a/include/lib/cpus/aarch32/cortex_a5.h
+++ b/include/lib/cpus/aarch32/cortex_a5.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h
index 8dd0192..b9bb310 100644
--- a/include/lib/cpus/aarch32/cortex_a53.h
+++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h
index ffabd61..bb977ff 100644
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a7.h b/include/lib/cpus/aarch32/cortex_a7.h
index 730fdb5..16fbfaa 100644
--- a/include/lib/cpus/aarch32/cortex_a7.h
+++ b/include/lib/cpus/aarch32/cortex_a7.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 954f736..0a3a23a 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h
index a8c978a..337bad9 100644
--- a/include/lib/cpus/aarch32/cortex_a9.h
+++ b/include/lib/cpus/aarch32/cortex_a9.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h
index 6bb30a2..acb6adb 100644
--- a/include/lib/cpus/aarch64/aem_generic.h
+++ b/include/lib/cpus/aarch64/aem_generic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h
index 5421478..cef2960 100644
--- a/include/lib/cpus/aarch64/cortex_a35.h
+++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 54e646c..18796ee 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h
index 60ed957..0a1593a 100644
--- a/include/lib/cpus/aarch64/cortex_a55.h
+++ b/include/lib/cpus/aarch64/cortex_a55.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index dc40e31..19ac513 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index bef9337..a00f6d6 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index 271a333..ede76d1 100644
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index e5ca1ba..ca79991 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index a9b4546..39717a3 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 66f565d..2984f82 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h
index b68ec1e..4ada845 100644
--- a/include/lib/cpus/aarch64/cortex_a78_ae.h
+++ b/include/lib/cpus/aarch64/cortex_a78_ae.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
  * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index d945d7c..6faef5d 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -472,15 +472,25 @@
  * _chosen:
  *	Compile time flag on whether the erratum is included
  *
- * clobbers: x0-x9 (PCS compliant)
+ * _get_rev:
+ *	Optional parameter that determines whether to insert a call to the CPU revision fetching
+ *	procedure. Stores the result of this in the temporary register x10.
+ *
+ * clobbers: x0-x10 (PCS compliant)
  */
-.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req
-	.if \_chosen
+.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req, _get_rev=GET_CPU_REV
+	.if (\_chosen & \_get_rev)
 		mov	x9, x30
 		bl	cpu_get_rev_var
+		mov	x10, x0
+	.elseif (\_chosen)
+		mov	x9, x30
+		mov	x0, x10
+	.endif
+
+	.if \_chosen
 		bl	erratum_\_cpu\()_\_id\()_wa
 		mov	x30, x9
-
 	.endif
 .endm
 
diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h
index 463f890..cb004bf 100644
--- a/include/lib/cpus/aarch64/cpuamu.h
+++ b/include/lib/cpus/aarch64/cpuamu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index 24b6a87..84ab6bb 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h
index 96b4661..6e784f6 100644
--- a/include/lib/cpus/aarch64/neoverse_e1.h
+++ b/include/lib/cpus/aarch64/neoverse_e1.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index b6b8d8d..0ba5ad1 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
index 798ecd1..202ef5c 100644
--- a/include/lib/cpus/aarch64/neoverse_poseidon.h
+++ b/include/lib/cpus/aarch64/neoverse_poseidon.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 1bb6243..d618994 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h
index 14da170..58923d2 100644
--- a/include/lib/cpus/aarch64/qemu_max.h
+++ b/include/lib/cpus/aarch64/qemu_max.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index b280435..2080898 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -66,6 +66,9 @@
 #define NO_ASSERT		0
 #define NO_APPLY_AT_RESET	0
 #define APPLY_AT_RESET		1
+#define GET_CPU_REV		1
+#define NO_GET_CPU_REV		0
+
 /* useful for errata that end up always being worked around */
 #define ERRATUM_ALWAYS_CHOSEN	1
 
diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h
index 940fc65..2ad56e1 100644
--- a/include/lib/cpus/wa_cve_2017_5715.h
+++ b/include/lib/cpus/wa_cve_2017_5715.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h
index e37db37..5a7c9bf 100644
--- a/include/lib/cpus/wa_cve_2018_3639.h
+++ b/include/lib/cpus/wa_cve_2018_3639.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h
index 35b3fd8..50c0f76 100644
--- a/include/lib/cpus/wa_cve_2022_23960.h
+++ b/include/lib/cpus/wa_cve_2022_23960.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h
index df77c0f..3b698e3 100644
--- a/include/lib/el3_runtime/aarch32/context.h
+++ b/include/lib/el3_runtime/aarch32/context.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/el3_runtime/pubsub_events.h b/include/lib/el3_runtime/pubsub_events.h
index 5012082..d0c0502 100644
--- a/include/lib/el3_runtime/pubsub_events.h
+++ b/include/lib/el3_runtime/pubsub_events.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index 80ad68c..09d8dee 100644
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h
index 2e780de..dbc2226 100644
--- a/include/lib/extensions/pauth.h
+++ b/include/lib/extensions/pauth.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h
index 793ab9f..6997da0 100644
--- a/include/lib/extensions/ras.h
+++ b/include/lib/extensions/ras.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h
index 55760b0..e0aee50 100644
--- a/include/lib/extensions/ras_arch.h
+++ b/include/lib/extensions/ras_arch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h
index 3762021..5b54c04 100644
--- a/include/lib/fconf/fconf.h
+++ b/include/lib/fconf/fconf.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/fconf/fconf_tbbr_getter.h b/include/lib/fconf/fconf_tbbr_getter.h
index db98b68..541a396 100644
--- a/include/lib/fconf/fconf_tbbr_getter.h
+++ b/include/lib/fconf/fconf_tbbr_getter.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/aarch32/endian_.h b/include/lib/libc/aarch32/endian_.h
index 0cf2c75..edca496 100644
--- a/include/lib/libc/aarch32/endian_.h
+++ b/include/lib/libc/aarch32/endian_.h
@@ -32,7 +32,7 @@
  * $FreeBSD$
  */
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/aarch32/inttypes_.h b/include/lib/libc/aarch32/inttypes_.h
index ef3fb8f..0888bf0 100644
--- a/include/lib/libc/aarch32/inttypes_.h
+++ b/include/lib/libc/aarch32/inttypes_.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/aarch32/limits_.h b/include/lib/libc/aarch32/limits_.h
index a67ec53..5b0516a 100644
--- a/include/lib/libc/aarch32/limits_.h
+++ b/include/lib/libc/aarch32/limits_.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/aarch32/stddef_.h b/include/lib/libc/aarch32/stddef_.h
index 36dc20b..14ed094 100644
--- a/include/lib/libc/aarch32/stddef_.h
+++ b/include/lib/libc/aarch32/stddef_.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h
index dafe142..6e2deed 100644
--- a/include/lib/libc/aarch32/stdint_.h
+++ b/include/lib/libc/aarch32/stdint_.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/aarch32/stdio_.h b/include/lib/libc/aarch32/stdio_.h
index 5e49425..7042664 100644
--- a/include/lib/libc/aarch32/stdio_.h
+++ b/include/lib/libc/aarch32/stdio_.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/aarch64/endian_.h b/include/lib/libc/aarch64/endian_.h
index 7c79fd4..58273d7 100644
--- a/include/lib/libc/aarch64/endian_.h
+++ b/include/lib/libc/aarch64/endian_.h
@@ -32,7 +32,7 @@
  * $FreeBSD$
  */
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/aarch64/inttypes_.h b/include/lib/libc/aarch64/inttypes_.h
index f25882f..6109084 100644
--- a/include/lib/libc/aarch64/inttypes_.h
+++ b/include/lib/libc/aarch64/inttypes_.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/aarch64/limits_.h b/include/lib/libc/aarch64/limits_.h
index 1bb0681..834439e 100644
--- a/include/lib/libc/aarch64/limits_.h
+++ b/include/lib/libc/aarch64/limits_.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/aarch64/setjmp_.h b/include/lib/libc/aarch64/setjmp_.h
index f880a17..a7d0b5c 100644
--- a/include/lib/libc/aarch64/setjmp_.h
+++ b/include/lib/libc/aarch64/setjmp_.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/aarch64/stddef_.h b/include/lib/libc/aarch64/stddef_.h
index 6ecc606..963048e 100644
--- a/include/lib/libc/aarch64/stddef_.h
+++ b/include/lib/libc/aarch64/stddef_.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h
index 56e9f1b..34a75ec 100644
--- a/include/lib/libc/aarch64/stdint_.h
+++ b/include/lib/libc/aarch64/stdint_.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/aarch64/stdio_.h b/include/lib/libc/aarch64/stdio_.h
index afaeadc..331bcaa 100644
--- a/include/lib/libc/aarch64/stdio_.h
+++ b/include/lib/libc/aarch64/stdio_.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/arm_acle.h b/include/lib/libc/arm_acle.h
index eb08552..d1bc0f9 100644
--- a/include/lib/libc/arm_acle.h
+++ b/include/lib/libc/arm_acle.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 ARM Limited
+ * Copyright (c) 2021 Arm Limited
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h
index 462bb43..acfd147 100644
--- a/include/lib/libc/assert.h
+++ b/include/lib/libc/assert.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h
index 2423f38..b11d072 100644
--- a/include/lib/libc/cdefs.h
+++ b/include/lib/libc/cdefs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/endian.h b/include/lib/libc/endian.h
index 4100f57..9c9fd58 100644
--- a/include/lib/libc/endian.h
+++ b/include/lib/libc/endian.h
@@ -28,7 +28,7 @@
  * $FreeBSD$
  */
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/errno.h b/include/lib/libc/errno.h
index 029912f..b536fe9 100644
--- a/include/lib/libc/errno.h
+++ b/include/lib/libc/errno.h
@@ -37,7 +37,7 @@
  * $FreeBSD$
  */
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/inttypes.h b/include/lib/libc/inttypes.h
index 6ad1c9e..344b71c 100644
--- a/include/lib/libc/inttypes.h
+++ b/include/lib/libc/inttypes.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2020, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/limits.h b/include/lib/libc/limits.h
index 41bb658..c5c8764 100644
--- a/include/lib/libc/limits.h
+++ b/include/lib/libc/limits.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/setjmp.h b/include/lib/libc/setjmp.h
index be8e2c0..871c868 100644
--- a/include/lib/libc/setjmp.h
+++ b/include/lib/libc/setjmp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/stdarg.h b/include/lib/libc/stdarg.h
index e260b9b..2d1f785 100644
--- a/include/lib/libc/stdarg.h
+++ b/include/lib/libc/stdarg.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h
index b58334c..c2c9b22 100644
--- a/include/lib/libc/stdbool.h
+++ b/include/lib/libc/stdbool.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/libc/stddef.h b/include/lib/libc/stddef.h
index 58a519e..aaad673 100644
--- a/include/lib/libc/stddef.h
+++ b/include/lib/libc/stddef.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h
index e96a25c..88502e7 100644
--- a/include/lib/libc/stdint.h
+++ b/include/lib/libc/stdint.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h
index ba13683..5ceaf68 100644
--- a/include/lib/libc/stdio.h
+++ b/include/lib/libc/stdio.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h
index 4641e56..4e5a824 100644
--- a/include/lib/libc/stdlib.h
+++ b/include/lib/libc/stdlib.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h
index 7ddeed9..8129404 100644
--- a/include/lib/libc/string.h
+++ b/include/lib/libc/string.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018-2020, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2020, Arm Limited and Contributors.
  * Portions copyright (c) 2023, Intel Corporation. All rights reserved.
  * All rights reserved.
  */
diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h
index c1c95e5..e1eb2a5 100644
--- a/include/lib/libc/time.h
+++ b/include/lib/libc/time.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018-2019, ARM Limited and Contributors.
+ * Portions copyright (c) 2018-2019, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/include/lib/mmio.h b/include/lib/mmio.h
index 3242a7c..591d7b6 100644
--- a/include/lib/mmio.h
+++ b/include/lib/mmio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/object_pool.h b/include/lib/object_pool.h
index 66e8c47..49584eb 100644
--- a/include/lib/object_pool.h
+++ b/include/lib/object_pool.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/optee_utils.h b/include/lib/optee_utils.h
index 8224d50..e1e9d80 100644
--- a/include/lib/optee_utils.h
+++ b/include/lib/optee_utils.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/pmf/aarch64/pmf_asm_macros.S b/include/lib/pmf/aarch64/pmf_asm_macros.S
index 5f3e6b7..792ede9 100644
--- a/include/lib/pmf/aarch64/pmf_asm_macros.S
+++ b/include/lib/pmf/aarch64/pmf_asm_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h
index fa990d2..9d901e2 100644
--- a/include/lib/pmf/pmf.h
+++ b/include/lib/pmf/pmf.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h
index 01cc179..f5f040b 100644
--- a/include/lib/pmf/pmf_helpers.h
+++ b/include/lib/pmf/pmf_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index 01dc3cb..c40f955 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/runtime_instr.h b/include/lib/runtime_instr.h
index 303f27e..65fafa7 100644
--- a/include/lib/runtime_instr.h
+++ b/include/lib/runtime_instr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h
index 24b030c..5c72e8b 100644
--- a/include/lib/semihosting.h
+++ b/include/lib/semihosting.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index fb2b3a2..8fd6093 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h
index 0bf3ee0..9fd3fc6 100644
--- a/include/lib/spinlock.h
+++ b/include/lib/spinlock.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/utils.h b/include/lib/utils.h
index 17ee936..ce76de2 100644
--- a/include/lib/utils.h
+++ b/include/lib/utils.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 63eda63..ba52bc6 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/xlat_mpu/xlat_mpu.h b/include/lib/xlat_mpu/xlat_mpu.h
index 252b92c..3a470ad 100644
--- a/include/lib/xlat_mpu/xlat_mpu.h
+++ b/include/lib/xlat_mpu/xlat_mpu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
index 30eb5e9..42a48f4 100644
--- a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
+++ b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
index 3014c8f..6c0d73b 100644
--- a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
+++ b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h
index 269afd2..fabc494 100644
--- a/include/lib/xlat_tables/xlat_mmu_helpers.h
+++ b/include/lib/xlat_tables/xlat_mmu_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h
index a156969..24f833c 100644
--- a/include/lib/xlat_tables/xlat_tables.h
+++ b/include/lib/xlat_tables/xlat_tables.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h
index 0ce0cac..46e058c 100644
--- a/include/lib/xlat_tables/xlat_tables_arch.h
+++ b/include/lib/xlat_tables/xlat_tables_arch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/xlat_tables/xlat_tables_compat.h b/include/lib/xlat_tables/xlat_tables_compat.h
index 5f28195..3877c91 100644
--- a/include/lib/xlat_tables/xlat_tables_compat.h
+++ b/include/lib/xlat_tables/xlat_tables_compat.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h
index 4d16ced..64fe5ef 100644
--- a/include/lib/xlat_tables/xlat_tables_v2.h
+++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
index 62f853d..992c94e 100644
--- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h
+++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/lib/zlib/tf_gunzip.h b/include/lib/zlib/tf_gunzip.h
index 741ba50..9435860 100644
--- a/include/lib/zlib/tf_gunzip.h
+++ b/include/lib/zlib/tf_gunzip.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h
index cafbc3e..d45c269 100644
--- a/include/plat/arm/common/fconf_ethosn_getter.h
+++ b/include/plat/arm/common/fconf_ethosn_getter.h
@@ -57,8 +57,6 @@
 	struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX];
 };
 
-int fconf_populate_arm_ethosn(uintptr_t config);
-
 extern struct ethosn_config_t ethosn_config;
 
 #endif /* FCONF_ETHOSN_GETTER_H */
diff --git a/lib/aarch32/arm32_aeabi_divmod.c b/lib/aarch32/arm32_aeabi_divmod.c
index ea8e2bb..89a9033 100644
--- a/lib/aarch32/arm32_aeabi_divmod.c
+++ b/lib/aarch32/arm32_aeabi_divmod.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/aarch32/arm32_aeabi_divmod_a32.S b/lib/aarch32/arm32_aeabi_divmod_a32.S
index 6915dcd..9155100 100644
--- a/lib/aarch32/arm32_aeabi_divmod_a32.S
+++ b/lib/aarch32/arm32_aeabi_divmod_a32.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/aarch32/armclang_printf.S b/lib/aarch32/armclang_printf.S
index 2b87bf7..e736a11 100644
--- a/lib/aarch32/armclang_printf.S
+++ b/lib/aarch32/armclang_printf.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S
index 59e15bd..c010cbc 100644
--- a/lib/aarch32/misc_helpers.S
+++ b/lib/aarch32/misc_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/aarch64/armclang_printf.S b/lib/aarch64/armclang_printf.S
index 52a6976..f9326fd 100644
--- a/lib/aarch64/armclang_printf.S
+++ b/lib/aarch64/armclang_printf.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/bl_aux_params/bl_aux_params.c b/lib/bl_aux_params/bl_aux_params.c
index 7f357b7..6e30ecf 100644
--- a/lib/bl_aux_params/bl_aux_params.c
+++ b/lib/bl_aux_params/bl_aux_params.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/compiler-rt/compiler-rt.mk b/lib/compiler-rt/compiler-rt.mk
index b41c4d0..2b16504 100644
--- a/lib/compiler-rt/compiler-rt.mk
+++ b/lib/compiler-rt/compiler-rt.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are met:
diff --git a/lib/coreboot/coreboot.mk b/lib/coreboot/coreboot.mk
index 4201823..e07d28c 100644
--- a/lib/coreboot/coreboot.mk
+++ b/lib/coreboot/coreboot.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c
index 43e9835..c954e97 100644
--- a/lib/coreboot/coreboot_table.c
+++ b/lib/coreboot/coreboot_table.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch32/aem_generic.S b/lib/cpus/aarch32/aem_generic.S
index 7bd586a..9f45e38 100644
--- a/lib/cpus/aarch32/aem_generic.S
+++ b/lib/cpus/aarch32/aem_generic.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S
index dfa159f..d08b4ff 100644
--- a/lib/cpus/aarch32/cortex_a32.S
+++ b/lib/cpus/aarch32/cortex_a32.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 05bc5d9..83e3e49 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S
index 6291e43..d47279a 100644
--- a/lib/cpus/aarch64/aem_generic.S
+++ b/lib/cpus/aarch64/aem_generic.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index cebd6f0..eab5ada 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,22 +26,7 @@
 	wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710
 #endif /* WORKAROUND_CVE_2022_23960 */
 
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 1987031.
- * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still
- * open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a710_1987031_wa
-	/* Check revision. */
-	mov	x17, x30
-	bl	check_errata_1987031
-	cbz	x0, 1f
-
-	/* Apply instruction patching sequence */
+workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
 	ldr x0,=0x6
 	msr S3_6_c15_c8_0,x0
 	ldr x0,=0xF3A08002
@@ -58,33 +43,53 @@
 	msr S3_6_c15_c8_3,x0
 	ldr x0,=0x40000001003f3
 	msr S3_6_c15_c8_1,x0
-	isb
-1:
-	ret	x17
-endfunc errata_a710_1987031_wa
+workaround_reset_end cortex_a710, ERRATUM(1987031)
 
-func check_errata_1987031
-	/* Applies to r0p0, r1p0 and r2p0 */
-	mov	x1, #0x20
-	b	cpu_rev_var_ls
-endfunc check_errata_1987031
+check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0)
 
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2081180.
- * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a710_2081180_wa
-	/* Check revision. */
-	mov	x17, x30
-	bl	check_errata_2081180
-	cbz	x0, 1f
+workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
+	/* Stash ERRSELR_EL1 in x2 */
+	mrs	x2, ERRSELR_EL1
+
+	/* Select error record 0 and clear ED bit */
+	msr	ERRSELR_EL1, xzr
+	mrs	x1, ERXCTLR_EL1
+	bfi	x1, xzr, #ERXCTLR_ED_SHIFT, #1
+	msr	ERXCTLR_EL1, x1
 
-	/* Apply instruction patching sequence */
+	/* Select error record 1 and clear ED bit */
+	mov	x0, #1
+	msr	ERRSELR_EL1, x0
+	mrs	x1, ERXCTLR_EL1
+	bfi	x1, xzr, #ERXCTLR_ED_SHIFT, #1
+	msr	ERXCTLR_EL1, x1
+
+	/* Restore ERRSELR_EL1 from x2 */
+	msr	ERRSELR_EL1, x2
+workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB
+
+check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096
+	sysreg_bit_set	CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end cortex_a710, ERRATUM(2017096)
+
+check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002
+	sysreg_bit_set	CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46
+workaround_reset_end cortex_a710, ERRATUM(2055002)
+
+check_erratum_ls cortex_a710, ERRATUM(2055002), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056
+	sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \
+		CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH
+workaround_reset_end cortex_a710, ERRATUM(2058056)
+
+check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180
 	ldr	x0,=0x3
 	msr	S3_6_c15_c8_0,x0
 	ldr	x0,=0xF3A08002
@@ -101,238 +106,30 @@
 	msr	S3_6_c15_c8_3,x0
 	ldr	x0,=0x10002001003F3
 	msr	S3_6_c15_c8_1,x0
-	isb
-1:
-	ret	x17
-endfunc errata_a710_2081180_wa
-
-func check_errata_2081180
-	/* Applies to r0p0, r1p0 and r2p0 */
-	mov	x1, #0x20
-	b	cpu_rev_var_ls
-endfunc check_errata_2081180
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2055002.
- * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2055002_wa
-	/* Compare x0 against revision r2p0 */
-	mov	x17, x30
-	bl	check_errata_2055002
-	cbz	x0, 1f
-	mrs	x1, CORTEX_A710_CPUACTLR_EL1
-	orr	x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
-	msr	CORTEX_A710_CPUACTLR_EL1, x1
-1:
-	ret	x17
-endfunc errata_a710_2055002_wa
-
-func check_errata_2055002
-	/* Applies to r1p0, r2p0 */
-	mov	x1, #0x20
-	b	cpu_rev_var_ls
-endfunc check_errata_2055002
-
-/* -------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2017096.
- * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------------
- */
-func errata_a710_2017096_wa
-	/* Compare x0 against revision r0p0 to r2p0 */
-	mov     x17, x30
-	bl      check_errata_2017096
-	cbz     x0, 1f
-	mrs     x1, CORTEX_A710_CPUECTLR_EL1
-	orr     x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
-	msr     CORTEX_A710_CPUECTLR_EL1, x1
-
-1:
-	ret     x17
-endfunc errata_a710_2017096_wa
-
-func check_errata_2017096
-	/* Applies to r0p0, r1p0, r2p0 */
-	mov     x1, #0x20
-	b       cpu_rev_var_ls
-endfunc check_errata_2017096
-
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2083908.
- * This applies to revision r2p0 of Cortex-A710 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2083908_wa
-	/* Compare x0 against revision r2p0 */
-	mov	x17, x30
-	bl	check_errata_2083908
-	cbz	x0, 1f
-	mrs	x1, CORTEX_A710_CPUACTLR5_EL1
-	orr	x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
-	msr	CORTEX_A710_CPUACTLR5_EL1, x1
-1:
-	ret	x17
-endfunc errata_a710_2083908_wa
-
-func check_errata_2083908
-	/* Applies to r2p0 */
-	mov	x1, #CPU_REV(2, 0)
-	mov	x2, #CPU_REV(2, 0)
-	b	cpu_rev_var_range
-endfunc check_errata_2083908
-
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2058056.
- * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still
- * open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2058056_wa
-	/* Compare x0 against revision r2p0 */
-	mov	x17, x30
-	bl	check_errata_2058056
-	cbz	x0, 1f
-	mrs	x1, CORTEX_A710_CPUECTLR2_EL1
-	mov	x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV
-	bfi	x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
-	msr	CORTEX_A710_CPUECTLR2_EL1, x1
-1:
-	ret	x17
-endfunc errata_a710_2058056_wa
+workaround_reset_end cortex_a710, ERRATUM(2081180)
 
-func check_errata_2058056
-	/* Applies to r0p0, r1p0 and r2p0 */
-	mov	x1, #0x20
-	b	cpu_rev_var_ls
-endfunc check_errata_2058056
+check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0)
 
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2267065.
- * This applies to revisions r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a710_2267065_wa
-	/* Compare x0 against revision r2p0 */
-	mov	x17, x30
-	bl	check_errata_2267065
-	cbz	x0, 1f
-
-	/* Apply instruction patching sequence */
-	mrs	x1, CORTEX_A710_CPUACTLR_EL1
-	orr	x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
-	msr	CORTEX_A710_CPUACTLR_EL1, x1
-1:
-	ret	x17
-endfunc errata_a710_2267065_wa
+workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908
+	sysreg_bit_set	CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
+workaround_reset_end cortex_a710, ERRATUM(2083908)
 
-func check_errata_2267065
-	/* Applies to r0p0, r1p0 and r2p0 */
-	mov	x1, #0x20
-	b	cpu_rev_var_ls
-endfunc check_errata_2267065
+check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
 
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2136059.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2136059_wa
-	/* Compare x0 against revision r2p0 */
-	mov     x17, x30
-	bl      check_errata_2136059
-	cbz     x0, 1f
+workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059
+	sysreg_bit_set	CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
+workaround_reset_end cortex_a710, ERRATUM(2136059)
 
-	/* Apply the workaround */
-	mrs     x1, CORTEX_A710_CPUACTLR5_EL1
-	orr     x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
-	msr     CORTEX_A710_CPUACTLR5_EL1, x1
+check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0)
 
-1:
-	ret     x17
-endfunc errata_a710_2136059_wa
+workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715
+	sysreg_bit_set	CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_a710, ERRATUM(2147715)
 
-func check_errata_2136059
-	/* Applies to r0p0, r1p0 and r2p0 */
-	mov     x1, #0x20
-	b       cpu_rev_var_ls
-endfunc check_errata_2136059
+check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
 
-/* ----------------------------------------------------------------
- * Errata workaround for Cortex-A710 Erratum 2147715.
- * This applies to revision r2p0, and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ----------------------------------------------------------------
- */
-func errata_a710_2147715_wa
-	mov 	x17, x30
-	bl 	check_errata_2147715
-	cbz	x0, 1f
-
-	/* Apply workaround; set CPUACTLR_EL1[22]
-	 * to 1, which will cause the CFP instruction
-	 * to invalidate all branch predictor resources
-	 * regardless of context.
-	 */
-	mrs 	x1, CORTEX_A710_CPUACTLR_EL1
-	orr	x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
-	msr 	CORTEX_A710_CPUACTLR_EL1, x1
-1:
-	ret	x17
-endfunc errata_a710_2147715_wa
-
-func check_errata_2147715
-	mov 	x1, #0x20
-	mov 	x2, #0x20
-	b 	cpu_rev_var_range
-endfunc check_errata_2147715
-
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2216384.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2216384_wa
-	/* Compare x0 against revision r2p0 */
-	mov	x17, x30
-	bl	check_errata_2216384
-	cbz	x0, 1f
-
-	/* Apply workaround: set CPUACTLR5_EL1[17]
-	 * to 1 and the following instruction
-	 * patching sequence.
-	 */
-	mrs	x1, CORTEX_A710_CPUACTLR5_EL1
-	orr	x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
-	msr	CORTEX_A710_CPUACTLR5_EL1, x1
+workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384
+	sysreg_bit_set	CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
 
 	ldr	x0,=0x5
 	msr	CORTEX_A710_CPUPSELR_EL3, x0
@@ -342,338 +139,88 @@
 	msr	CORTEX_A710_CPUPMR_EL3, x0
 	ldr	x0,=0x80000000003FF
 	msr	CORTEX_A710_CPUPCR_EL3, x0
-	isb
-1:
-	ret 	x17
-endfunc errata_a710_2216384_wa
+workaround_reset_end cortex_a710, ERRATUM(2216384)
 
-func check_errata_2216384
-	/* Applies to r0p0, r1p0 and r2p0 */
-	mov	x1, #0x20
-	b	cpu_rev_var_ls
-endfunc check_errata_2216384
+check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0)
 
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2282622.
- * This applies to revision r0p0, r1p0, r2p0 and r2p1.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2282622_wa
-	/* Compare x0 against revision r2p1 */
-	mov     x17, x30
-	bl      check_errata_2282622
-	cbz     x0, 1f
+workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065
+	sysreg_bit_set	CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_a710, ERRATUM(2267065)
 
-	/* Apply the workaround */
-	mrs     x1, CORTEX_A710_CPUACTLR2_EL1
-	orr     x1, x1, #BIT(0)
-	msr     CORTEX_A710_CPUACTLR2_EL1, x1
+check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0)
 
-1:
-	ret     x17
-endfunc errata_a710_2282622_wa
+workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622
+	sysreg_bit_set	CORTEX_A710_CPUACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_a710, ERRATUM(2282622)
 
-func check_errata_2282622
-	/* Applies to r0p0, r1p0, r2p0 and r2p1 */
-	mov     x1, #0x21
-	b       cpu_rev_var_ls
-endfunc check_errata_2282622
+check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1)
 
-/* ------------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2291219 on power down request.
- * This applies to revision <= r2p0 and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ------------------------------------------------------------------------
- */
-func errata_a710_2291219_wa
-	/* Check revision. */
-	mov	x17, x30
-	bl	check_errata_2291219
-	cbz	x0, 1f
-
+workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219
 	/* Set bit 36 in ACTLR2_EL1 */
-	mrs	x1, CORTEX_A710_CPUACTLR2_EL1
-	orr	x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36
-	msr	CORTEX_A710_CPUACTLR2_EL1, x1
-1:
-	ret	x17
-endfunc errata_a710_2291219_wa
+	sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB
 
-func check_errata_2291219
-	/* Applies to <= r2p0. */
-	mov	x1, #0x20
-	b	cpu_rev_var_ls
-endfunc check_errata_2291219
+check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0)
 
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2008768.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x2, x17
- * ---------------------------------------------------------------
+/*
+ * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as
+ * well. Create a symbollic link to existing errata workaround to get them
+ * registered under the Errata Framework.
  */
-func errata_a710_2008768_wa
-	mov     x17, x30
-	bl      check_errata_2008768
-	cbz     x0, 1f
-
-	/* Stash ERRSELR_EL1 in x2 */
-	mrs	x2, ERRSELR_EL1
+.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
 
-	/* Select error record 0 and clear ED bit */
-	msr	ERRSELR_EL1, xzr
-	mrs	x1, ERXCTLR_EL1
-	bfi	x1, xzr, #ERXCTLR_ED_SHIFT, #1
-	msr	ERXCTLR_EL1, x1
-
-	/* Select error record 1 and clear ED bit */
-	mov	x0, #1
-	msr	ERRSELR_EL1, x0
-	mrs	x1, ERXCTLR_EL1
-	bfi	x1, xzr, #ERXCTLR_ED_SHIFT, #1
-	msr	ERXCTLR_EL1, x1
-
-	/* Restore ERRSELR_EL1 from x2 */
-	msr	ERRSELR_EL1, x2
-
-1:
-	ret     x17
-endfunc errata_a710_2008768_wa
-
-func check_errata_2008768
-	/* Applies to r0p0, r1p0 and r2p0 */
-	mov     x1, #0x20
-	b       cpu_rev_var_ls
-endfunc check_errata_2008768
-
-/* -------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2371105.
- * This applies to revisions <= r2p0 and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_a710_2371105_wa
-	/* Check workaround compatibility. */
-	mov	x17, x30
-	bl	check_errata_2371105
-	cbz	x0, 1f
-
+workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105
 	/* Set bit 40 in CPUACTLR2_EL1 */
-	mrs	x1, CORTEX_A710_CPUACTLR2_EL1
-	orr	x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40
-	msr	CORTEX_A710_CPUACTLR2_EL1, x1
-	isb
-1:
-	ret	x17
-endfunc errata_a710_2371105_wa
+	sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a710, ERRATUM(2371105)
 
-func check_errata_2371105
-	/* Applies to <= r2p0. */
-	mov	x1, #0x20
-	b	cpu_rev_var_ls
-endfunc check_errata_2371105
+check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0)
 
-/* ----------------------------------------------------
- * Errata Workaround for Cortex-A710 Errata #2768515
- * This applies to revisions <= r2p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a710_2768515_wa
-	mov	x17, x30
-	bl	check_errata_2768515
-	cbz	x0, 1f
-
+workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515
 	/* dsb before isb of power down sequence */
 	dsb	sy
-1:
-	ret	x17
-endfunc errata_a710_2768515_wa
+workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB
 
-func check_errata_2768515
-	/* Applies to all revisions <= r2p1 */
-	mov	x1, #0x21
-	b	cpu_rev_var_ls
-endfunc check_errata_2768515
+check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1)
 
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
-	mov	x0, #ERRATA_APPLIES
-#else
-	mov	x0, #ERRATA_MISSING
-#endif
-	ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+	/*
+	 * The Cortex-A710 generic vectors are overridden to apply errata
+	 * mitigation on exception entry from lower ELs.
+	 */
+	override_vector_table wa_cve_vbar_cortex_a710
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a710, CVE(2022, 23960)
+
+check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ----------------------------------------------------
 	 */
 func cortex_a710_core_pwr_dwn
-
-#if ERRATA_A710_2008768
-	mov	x4, x30
-	bl	cpu_get_rev_var
-	bl	errata_a710_2008768_wa
-	mov	x30, x4
-#endif
-
-#if ERRATA_A710_2291219
-	mov	x15, x30
-	bl	cpu_get_rev_var
-	bl	errata_a710_2291219_wa
-	mov	x30, x15
-#endif /* ERRATA_A710_2291219 */
+	apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
+	apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
 
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
 	 */
-	mrs	x0, CORTEX_A710_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	msr	CORTEX_A710_CPUPWRCTLR_EL1, x0
-#if ERRATA_A710_2768515
-	mov	x15, x30
-	bl	cpu_get_rev_var
-	bl	errata_a710_2768515_wa
-	mov	x30, x15
-#endif /* ERRATA_A710_2768515 */
+	sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV
 	isb
 	ret
 endfunc cortex_a710_core_pwr_dwn
 
-#if REPORT_ERRATA
-	/*
-	 * Errata printing function for Cortex-A710. Must follow AAPCS.
-	 */
-func cortex_a710_errata_report
-	stp	x8, x30, [sp, #-16]!
-
-	bl	cpu_get_rev_var
-	mov	x8, x0
-
-	/*
-	 * Report all errata. The revision-variant information is passed to
-	 * checking functions of each errata.
-	 */
-	report_errata ERRATA_A710_1987031, cortex_a710, 1987031
-	report_errata ERRATA_A710_2081180, cortex_a710, 2081180
-	report_errata ERRATA_A710_2055002, cortex_a710, 2055002
-	report_errata ERRATA_A710_2017096, cortex_a710, 2017096
-	report_errata ERRATA_A710_2083908, cortex_a710, 2083908
-	report_errata ERRATA_A710_2058056, cortex_a710, 2058056
-	report_errata ERRATA_A710_2267065, cortex_a710, 2267065
-	report_errata ERRATA_A710_2136059, cortex_a710, 2136059
-	report_errata ERRATA_A710_2282622, cortex_a710, 2282622
-	report_errata ERRATA_A710_2008768, cortex_a710, 2008768
-	report_errata ERRATA_A710_2147715, cortex_a710, 2147715
-	report_errata ERRATA_A710_2216384, cortex_a710, 2216384
-	report_errata ERRATA_A710_2291219, cortex_a710, 2291219
-	report_errata ERRATA_A710_2371105, cortex_a710, 2371105
-	report_errata ERRATA_A710_2768515, cortex_a710, 2768515
-	report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960
-	report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941
-
-	ldp	x8, x30, [sp], #16
-	ret
-endfunc cortex_a710_errata_report
-#endif
+errata_report_shim cortex_a710
 
-func cortex_a710_reset_func
-	mov	x19, x30
-
+cpu_reset_func_start cortex_a710
 	/* Disable speculative loads */
 	msr	SSBS, xzr
-
-	bl	cpu_get_rev_var
-	mov	x18, x0
-
-#if ERRATA_DSU_2313941
-	bl	errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_A710_1987031
-	mov	x0, x18
-	bl	errata_a710_1987031_wa
-#endif
-
-#if ERRATA_A710_2081180
-	mov	x0, x18
-	bl	errata_a710_2081180_wa
-#endif
-
-#if ERRATA_A710_2055002
-	mov	x0, x18
-	bl	errata_a710_2055002_wa
-#endif
-
-#if ERRATA_A710_2017096
-	mov	x0, x18
-	bl	errata_a710_2017096_wa
-#endif
-
-#if ERRATA_A710_2083908
-	mov	x0, x18
-	bl	errata_a710_2083908_wa
-#endif
-
-#if ERRATA_A710_2058056
-	mov	x0, x18
-	bl	errata_a710_2058056_wa
-#endif
-
-#if ERRATA_A710_2267065
-	mov	x0, x18
-	bl	errata_a710_2267065_wa
-#endif
-
-#if ERRATA_A710_2136059
-	mov	x0, x18
-	bl	errata_a710_2136059_wa
-#endif
-
-#if ERRATA_A710_2147715
-	mov	x0, x18
-	bl 	errata_a710_2147715_wa
-#endif
-
-#if ERRATA_A710_2216384
-	mov	x0, x18
-	bl 	errata_a710_2216384_wa
-#endif /* ERRATA_A710_2216384 */
-
-#if ERRATA_A710_2282622
-	mov	x0, x18
-	bl	errata_a710_2282622_wa
-#endif
-
-#if ERRATA_A710_2371105
-	mov	x0, x18
-	bl	errata_a710_2371105_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
-	/*
-	 * The Cortex-A710 generic vectors are overridden to apply errata
-	 * mitigation on exception entry from lower ELs.
-	 */
-	adr	x0, wa_cve_vbar_cortex_a710
-	msr	vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
-	isb
-	ret	x19
-endfunc cortex_a710_reset_func
+cpu_reset_func_end cortex_a710
 
 	/* ---------------------------------------------
 	 * This function provides Cortex-A710 specific
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 0a7b9fb..c90be67 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c
index bd2c697..11190c8 100644
--- a/lib/cpus/aarch64/cortex_a75_pubsub.c
+++ b/lib/cpus/aarch64/cortex_a75_pubsub.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch64/cpuamu_helpers.S b/lib/cpus/aarch64/cpuamu_helpers.S
index 5a77fc7..e71e345 100644
--- a/lib/cpus/aarch64/cpuamu_helpers.S
+++ b/lib/cpus/aarch64/cpuamu_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch64/neoverse_n1_pubsub.c b/lib/cpus/aarch64/neoverse_n1_pubsub.c
index b1b7bb8..ecfb501 100644
--- a/lib/cpus/aarch64/neoverse_n1_pubsub.c
+++ b/lib/cpus/aarch64/neoverse_n1_pubsub.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
index 0222818..8d9aa5e 100644
--- a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
+++ b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
index ed0a549..823f849 100644
--- a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
+++ b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
index ceb93f1..bf26658 100644
--- a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
+++ b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/debugfs/debugfs.mk b/lib/debugfs/debugfs.mk
index 138fc72..caa9fcf 100644
--- a/lib/debugfs/debugfs.mk
+++ b/lib/debugfs/debugfs.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/debugfs/debugfs_smc.c b/lib/debugfs/debugfs_smc.c
index 13ced3d..64c64f8 100644
--- a/lib/debugfs/debugfs_smc.c
+++ b/lib/debugfs/debugfs_smc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/el3_runtime/aarch32/cpu_data.S b/lib/el3_runtime/aarch32/cpu_data.S
index bdad2c1..e59b7fd 100644
--- a/lib/el3_runtime/aarch32/cpu_data.S
+++ b/lib/el3_runtime/aarch32/cpu_data.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S
index 2392d6b..313f882 100644
--- a/lib/el3_runtime/aarch64/cpu_data.S
+++ b/lib/el3_runtime/aarch64/cpu_data.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/el3_runtime/cpu_data_array.c b/lib/el3_runtime/cpu_data_array.c
index 13d464c..2056182 100644
--- a/lib/el3_runtime/cpu_data_array.c
+++ b/lib/el3_runtime/cpu_data_array.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c
index 03186d6..351a552 100644
--- a/lib/extensions/amu/aarch32/amu.c
+++ b/lib/extensions/amu/aarch32/amu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/extensions/amu/aarch32/amu_helpers.S b/lib/extensions/amu/aarch32/amu_helpers.S
index 8ac7678..7090b2d 100644
--- a/lib/extensions/amu/aarch32/amu_helpers.S
+++ b/lib/extensions/amu/aarch32/amu_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index e0d3399..8c5ef0b 100644
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/extensions/amu/aarch64/amu_helpers.S b/lib/extensions/amu/aarch64/amu_helpers.S
index 0f6d799..95d4ad6 100644
--- a/lib/extensions/amu/aarch64/amu_helpers.S
+++ b/lib/extensions/amu/aarch64/amu_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/extensions/amu/amu_private.h b/lib/extensions/amu/amu_private.h
index eb7ff0e..a3b6845 100644
--- a/lib/extensions/amu/amu_private.h
+++ b/lib/extensions/amu/amu_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c
index 622879e..50f3727 100644
--- a/lib/extensions/ras/ras_common.c
+++ b/lib/extensions/ras/ras_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/extensions/ras/std_err_record.c b/lib/extensions/ras/std_err_record.c
index c03fbbe..6c1dc9f 100644
--- a/lib/extensions/ras/std_err_record.c
+++ b/lib/extensions/ras/std_err_record.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/fconf/fconf.c b/lib/fconf/fconf.c
index b1d6eaa..136e056 100644
--- a/lib/fconf/fconf.c
+++ b/lib/fconf/fconf.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/fconf/fconf.mk b/lib/fconf/fconf.mk
index fb88910..ff781aa 100644
--- a/lib/fconf/fconf.mk
+++ b/lib/fconf/fconf.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/libc/aarch64/setjmp.S b/lib/libc/aarch64/setjmp.S
index 9d9eb49..9cb31ea 100644
--- a/lib/libc/aarch64/setjmp.S
+++ b/lib/libc/aarch64/setjmp.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/abort.c b/lib/libc/abort.c
index 432b1d0..ac27f62 100644
--- a/lib/libc/abort.c
+++ b/lib/libc/abort.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/assert.c b/lib/libc/assert.c
index 8973ed5..301d142 100644
--- a/lib/libc/assert.c
+++ b/lib/libc/assert.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/exit.c b/lib/libc/exit.c
index f4ffe27..6de2e93 100644
--- a/lib/libc/exit.c
+++ b/lib/libc/exit.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/libc.mk b/lib/libc/libc.mk
index 5eb8b52..95da68c 100644
--- a/lib/libc/libc.mk
+++ b/lib/libc/libc.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/libc/memchr.c b/lib/libc/memchr.c
index 8cbb715..66d7ba1 100644
--- a/lib/libc/memchr.c
+++ b/lib/libc/memchr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/memcmp.c b/lib/libc/memcmp.c
index cd5f0df..db2701b 100644
--- a/lib/libc/memcmp.c
+++ b/lib/libc/memcmp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c
index 158df9b..af9ed45 100644
--- a/lib/libc/memcpy.c
+++ b/lib/libc/memcpy.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/memcpy_s.c b/lib/libc/memcpy_s.c
index 01e88b0..26953bf 100644
--- a/lib/libc/memcpy_s.c
+++ b/lib/libc/memcpy_s.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c
index 63acf26..5c2b661 100644
--- a/lib/libc/memmove.c
+++ b/lib/libc/memmove.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/memset.c b/lib/libc/memset.c
index 17f798c..c5bac8d 100644
--- a/lib/libc/memset.c
+++ b/lib/libc/memset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/putchar.c b/lib/libc/putchar.c
index 340bdd8..1f919d1 100644
--- a/lib/libc/putchar.c
+++ b/lib/libc/putchar.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/puts.c b/lib/libc/puts.c
index 2a0ca11..f57fc98 100644
--- a/lib/libc/puts.c
+++ b/lib/libc/puts.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/strchr.c b/lib/libc/strchr.c
index d94bb9e..1cd03ca 100644
--- a/lib/libc/strchr.c
+++ b/lib/libc/strchr.c
@@ -30,7 +30,7 @@
  */
 
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/lib/libc/strcmp.c b/lib/libc/strcmp.c
index b742f9b..290db4c 100644
--- a/lib/libc/strcmp.c
+++ b/lib/libc/strcmp.c
@@ -33,7 +33,7 @@
  */
 
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/lib/libc/strlen.c b/lib/libc/strlen.c
index 3c27630..e4b79d9 100644
--- a/lib/libc/strlen.c
+++ b/lib/libc/strlen.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/libc/strncmp.c b/lib/libc/strncmp.c
index ce9e5ed..f0bbadc 100644
--- a/lib/libc/strncmp.c
+++ b/lib/libc/strncmp.c
@@ -30,7 +30,7 @@
  */
 
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/lib/libc/strnlen.c b/lib/libc/strnlen.c
index b944e95..49e9f7a 100644
--- a/lib/libc/strnlen.c
+++ b/lib/libc/strnlen.c
@@ -27,7 +27,7 @@
  */
 
 /*
- * Portions copyright (c) 2018, ARM Limited and Contributors.
+ * Portions copyright (c) 2018, Arm Limited and Contributors.
  * All rights reserved.
  */
 
diff --git a/lib/libfdt/libfdt.mk b/lib/libfdt/libfdt.mk
index 1cbbd78..812057d 100644
--- a/lib/libfdt/libfdt.mk
+++ b/lib/libfdt/libfdt.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c
index 748eedd..bcd89ef 100644
--- a/lib/locks/bakery/bakery_lock_coherent.c
+++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 3c03ae6..9f27322 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/locks/exclusive/aarch32/spinlock.S b/lib/locks/exclusive/aarch32/spinlock.S
index 9492cc0..853d096 100644
--- a/lib/locks/exclusive/aarch32/spinlock.S
+++ b/lib/locks/exclusive/aarch32/spinlock.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S
index e941b8a..5144bf7 100644
--- a/lib/locks/exclusive/aarch64/spinlock.S
+++ b/lib/locks/exclusive/aarch64/spinlock.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index 6641db9..14f5533 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c
index ce2f0d9..bf0ad83 100644
--- a/lib/pmf/pmf_main.c
+++ b/lib/pmf/pmf_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c
index 6d79502..71486df 100644
--- a/lib/pmf/pmf_smc.c
+++ b/lib/pmf/pmf_smc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S
index d28d469..4e1013c 100644
--- a/lib/psci/aarch32/psci_helpers.S
+++ b/lib/psci/aarch32/psci_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index 61f31e5..3b77ab2 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/psci/psci_mem_protect.c b/lib/psci/psci_mem_protect.c
index 481051f..385dcd2 100644
--- a/lib/psci/psci_mem_protect.c
+++ b/lib/psci/psci_mem_protect.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 1f619ae..31875ff 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index 1f93cc9..6bf1ff4 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c
index ecef95a..ad88d07 100644
--- a/lib/psci/psci_stat.c
+++ b/lib/psci/psci_stat.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 2ff480b..c3ddc5a 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/romlib/gen_combined_bl1_romlib.sh b/lib/romlib/gen_combined_bl1_romlib.sh
index 1e3f73a..3941467 100755
--- a/lib/romlib/gen_combined_bl1_romlib.sh
+++ b/lib/romlib/gen_combined_bl1_romlib.sh
@@ -1,5 +1,5 @@
 #!/bin/sh
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
diff --git a/lib/romlib/init.s b/lib/romlib/init.s
index 7d97e4d..2bea15b 100644
--- a/lib/romlib/init.s
+++ b/lib/romlib/init.s
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i
index 33710f5..44751a2 100644
--- a/lib/romlib/jmptbl.i
+++ b/lib/romlib/jmptbl.i
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/romlib/romlib.ld.S b/lib/romlib/romlib.ld.S
index d54a684..0d076b4 100644
--- a/lib/romlib/romlib.ld.S
+++ b/lib/romlib/romlib.ld.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/semihosting/aarch32/semihosting_call.S b/lib/semihosting/aarch32/semihosting_call.S
index aced3d1..42d4718 100644
--- a/lib/semihosting/aarch32/semihosting_call.S
+++ b/lib/semihosting/aarch32/semihosting_call.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/semihosting/aarch64/semihosting_call.S b/lib/semihosting/aarch64/semihosting_call.S
index 97d2bca..6f60f3e 100644
--- a/lib/semihosting/aarch64/semihosting_call.S
+++ b/lib/semihosting/aarch64/semihosting_call.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c
index 163a82d..adc6b78 100644
--- a/lib/semihosting/semihosting.c
+++ b/lib/semihosting/semihosting.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/stack_protector/aarch32/asm_stack_protector.S b/lib/stack_protector/aarch32/asm_stack_protector.S
index 19b7525..0ffcf8a 100644
--- a/lib/stack_protector/aarch32/asm_stack_protector.S
+++ b/lib/stack_protector/aarch32/asm_stack_protector.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/stack_protector/aarch64/asm_stack_protector.S b/lib/stack_protector/aarch64/asm_stack_protector.S
index c2245d3..a002617 100644
--- a/lib/stack_protector/aarch64/asm_stack_protector.S
+++ b/lib/stack_protector/aarch64/asm_stack_protector.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/stack_protector/stack_protector.c b/lib/stack_protector/stack_protector.c
index 3ff74fc..d0f2400 100644
--- a/lib/stack_protector/stack_protector.c
+++ b/lib/stack_protector/stack_protector.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/stack_protector/stack_protector.mk b/lib/stack_protector/stack_protector.mk
index b5aba15..4f13bc3 100644
--- a/lib/stack_protector/stack_protector.mk
+++ b/lib/stack_protector/stack_protector.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/utils/mem_region.c b/lib/utils/mem_region.c
index fec086b..e9f0a12 100644
--- a/lib/utils/mem_region.c
+++ b/lib/utils/mem_region.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_mpu/aarch64/enable_mpu.S b/lib/xlat_mpu/aarch64/enable_mpu.S
index 3791f2d..0dda979 100644
--- a/lib/xlat_mpu/aarch64/enable_mpu.S
+++ b/lib/xlat_mpu/aarch64/enable_mpu.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
index 5068eb8..5a2120b 100644
--- a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
+++ b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_mpu/ro_xlat_mpu.mk b/lib/xlat_mpu/ro_xlat_mpu.mk
index 23f1d46..d3af3bd 100644
--- a/lib/xlat_mpu/ro_xlat_mpu.mk
+++ b/lib/xlat_mpu/ro_xlat_mpu.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021, ARM Limited. All rights reserved.
+# Copyright (c) 2021, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/xlat_mpu/xlat_mpu.mk b/lib/xlat_mpu/xlat_mpu.mk
index 041b91c..31bef04 100644
--- a/lib/xlat_mpu/xlat_mpu.mk
+++ b/lib/xlat_mpu/xlat_mpu.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/xlat_mpu/xlat_mpu_context.c b/lib/xlat_mpu/xlat_mpu_context.c
index 28c463b..783f21d 100644
--- a/lib/xlat_mpu/xlat_mpu_context.c
+++ b/lib/xlat_mpu/xlat_mpu_context.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_mpu/xlat_mpu_core.c b/lib/xlat_mpu/xlat_mpu_core.c
index 6b4b0c2..33f381d 100644
--- a/lib/xlat_mpu/xlat_mpu_core.c
+++ b/lib/xlat_mpu/xlat_mpu_core.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_mpu/xlat_mpu_private.h b/lib/xlat_mpu/xlat_mpu_private.h
index e0e479d..14800e9 100644
--- a/lib/xlat_mpu/xlat_mpu_private.h
+++ b/lib/xlat_mpu/xlat_mpu_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_mpu/xlat_mpu_utils.c b/lib/xlat_mpu/xlat_mpu_utils.c
index 5400875..dc5f956 100644
--- a/lib/xlat_mpu/xlat_mpu_utils.c
+++ b/lib/xlat_mpu/xlat_mpu_utils.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index 4b01b9b..6d098be 100644
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index dc167e3..4dbfc11 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c
index e2c8370..8b44df2 100644
--- a/lib/xlat_tables/xlat_tables_common.c
+++ b/lib/xlat_tables/xlat_tables_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h
index 82bc70c..cfecc39 100644
--- a/lib/xlat_tables/xlat_tables_private.h
+++ b/lib/xlat_tables/xlat_tables_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_tables_v2/aarch32/enable_mmu.S b/lib/xlat_tables_v2/aarch32/enable_mmu.S
index f2fff36..22c2876 100644
--- a/lib/xlat_tables_v2/aarch32/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch32/enable_mmu.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index a1a44af..920754b 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_tables_v2/aarch64/enable_mmu.S b/lib/xlat_tables_v2/aarch64/enable_mmu.S
index 9f075e4..247a796 100644
--- a/lib/xlat_tables_v2/aarch64/enable_mmu.S
+++ b/lib/xlat_tables_v2/aarch64/enable_mmu.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/xlat_tables_v2/ro_xlat_tables.mk b/lib/xlat_tables_v2/ro_xlat_tables.mk
index fb8a426..20bb015 100644
--- a/lib/xlat_tables_v2/ro_xlat_tables.mk
+++ b/lib/xlat_tables_v2/ro_xlat_tables.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/xlat_tables_v2/xlat_tables.mk b/lib/xlat_tables_v2/xlat_tables.mk
index bcc3e68..b4ad34b 100644
--- a/lib/xlat_tables_v2/xlat_tables.mk
+++ b/lib/xlat_tables_v2/xlat_tables.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c
index 95dae88..2fbbc78 100644
--- a/lib/xlat_tables_v2/xlat_tables_context.c
+++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/zlib/tf_gunzip.c b/lib/zlib/tf_gunzip.c
index 3ac80bc..8b8d14d 100644
--- a/lib/zlib/tf_gunzip.c
+++ b/lib/zlib/tf_gunzip.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/lib/zlib/zlib.mk b/lib/zlib/zlib.mk
index 98d4efa..a8937a7 100644
--- a/lib/zlib/zlib.mk
+++ b/lib/zlib/zlib.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
diff --git a/plat/arm/board/juno/cert_create_tbbr.mk b/plat/arm/board/juno/cert_create_tbbr.mk
index c092fe0..4d133b2 100644
--- a/plat/arm/board/juno/cert_create_tbbr.mk
+++ b/plat/arm/board/juno/cert_create_tbbr.mk
@@ -7,7 +7,7 @@
 PLAT_DEF_OID := 1
 
 ifeq (${PLAT_DEF_OID},1)
-  ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+  ifeq (${ETHOSN_NPU_DRIVER},1)
     $(eval $(call add_define, PLAT_DEF_OID))
     $(eval $(call add_define, PDEF_CERTS))
     $(eval $(call add_define, PDEF_EXTS))
diff --git a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
index 986299e..ec72160 100644
--- a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
+++ b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
@@ -51,10 +51,10 @@
 			tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d";
 			nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7";
 			plat_sp_content_cert_uuid = "776dfd44-8697-4c3b-91eb-c13e025a2a6f";
-#if ARM_ETHOSN_NPU_TZMP1
-			arm_ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1";
-			arm_ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2";
-			arm_ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed";
+#if ETHOSN_NPU_TZMP1
+			ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1";
+			ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2";
+			ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed";
 #endif
 		};
 	};
diff --git a/plat/arm/board/juno/fip/plat_def_fip_uuid.h b/plat/arm/board/juno/fip/plat_def_fip_uuid.h
index 0f0d11d..46adf24 100644
--- a/plat/arm/board/juno/fip/plat_def_fip_uuid.h
+++ b/plat/arm/board/juno/fip/plat_def_fip_uuid.h
@@ -7,8 +7,8 @@
 #ifndef PLAT_DEF_FIP_UUID_H
 #define PLAT_DEF_FIP_UUID_H
 
-#ifdef ARM_ETHOSN_NPU_TZMP1
+#ifdef ETHOSN_NPU_TZMP1
 #include <drivers/arm/ethosn_fip.h>
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 #endif /* PLAT_DEF_FIP_UUID_H */
diff --git a/plat/arm/board/juno/fip/plat_def_uuid_config.c b/plat/arm/board/juno/fip/plat_def_uuid_config.c
index 8133927..705a8ca 100644
--- a/plat/arm/board/juno/fip/plat_def_uuid_config.c
+++ b/plat/arm/board/juno/fip/plat_def_uuid_config.c
@@ -12,11 +12,11 @@
 #include "plat_def_fip_uuid.h"
 
 toc_entry_t plat_def_toc_entries[] = {
-#ifdef ARM_ETHOSN_NPU_TZMP1
+#ifdef ETHOSN_NPU_TZMP1
 	ETHOSN_FW_KEY_CERTIFICATE_DEF,
 	ETHOSN_FW_CONTENT_CERTIFICATE_DEF,
 	ETHOSN_FW_DEF,
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 	{
 		.name = NULL,
 		.uuid = { { 0 } },
diff --git a/plat/arm/board/juno/include/plat_tbbr_img_def.h b/plat/arm/board/juno/include/plat_tbbr_img_def.h
index 3e17ed3..5fbeb4e 100644
--- a/plat/arm/board/juno/include/plat_tbbr_img_def.h
+++ b/plat/arm/board/juno/include/plat_tbbr_img_def.h
@@ -7,12 +7,12 @@
 #ifndef JUNO_IMG_DEF_H
 #define JUNO_IMG_DEF_H
 
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 /* Arm(R) Ethos(TM)-N NPU images */
-#define ARM_ETHOSN_NPU_FW_KEY_CERT_ID		U(MAX_IMG_IDS_WITH_SPMDS + 1)
-#define ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID	U(MAX_IMG_IDS_WITH_SPMDS + 2)
-#define ARM_ETHOSN_NPU_FW_IMAGE_ID		U(MAX_IMG_IDS_WITH_SPMDS + 3)
+#define ETHOSN_NPU_FW_KEY_CERT_ID		U(MAX_IMG_IDS_WITH_SPMDS + 1)
+#define ETHOSN_NPU_FW_CONTENT_CERT_ID		U(MAX_IMG_IDS_WITH_SPMDS + 2)
+#define ETHOSN_NPU_FW_IMAGE_ID			U(MAX_IMG_IDS_WITH_SPMDS + 3)
 #define MAX_NUMBER_IDS				U(MAX_IMG_IDS_WITH_SPMDS + 4)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 #endif	/* JUNO_IMG_DEF_H */
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 47258cb..aa96038 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -327,15 +327,15 @@
 
 /* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */
 #ifdef JUNO_ETHOSN_TZMP1
-#define ARM_ETHOSN_NPU_PROT_FW_NSAID		JUNO_ETHOSN_TZC400_NSAID_FW_PROT
-#define ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID	JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
-#define ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID	JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
+#define ETHOSN_NPU_PROT_FW_NSAID		JUNO_ETHOSN_TZC400_NSAID_FW_PROT
+#define ETHOSN_NPU_PROT_RW_DATA_NSAID		JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT
+#define ETHOSN_NPU_PROT_RO_DATA_NSAID		JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT
 
-#define ARM_ETHOSN_NPU_NS_RW_DATA_NSAID		JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
-#define ARM_ETHOSN_NPU_NS_RO_DATA_NSAID		JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
+#define ETHOSN_NPU_NS_RW_DATA_NSAID		JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS
+#define ETHOSN_NPU_NS_RO_DATA_NSAID		JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS
 
-#define ARM_ETHOSN_NPU_FW_IMAGE_BASE		JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
-#define ARM_ETHOSN_NPU_FW_IMAGE_LIMIT \
+#define ETHOSN_NPU_FW_IMAGE_BASE		JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE
+#define ETHOSN_NPU_FW_IMAGE_LIMIT \
 	(JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE)
 #endif
 
diff --git a/plat/arm/board/juno/juno_tbbr_cot_bl2.c b/plat/arm/board/juno/juno_tbbr_cot_bl2.c
index d48d2e6..8930dbb 100644
--- a/plat/arm/board/juno/juno_tbbr_cot_bl2.c
+++ b/plat/arm/board/juno/juno_tbbr_cot_bl2.c
@@ -32,9 +32,9 @@
 #if defined(SPD_spmd)
 static unsigned char sp_pkg_hash_buf[MAX_SP_IDS][HASH_DER_LEN];
 #endif /* SPD_spmd */
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 static unsigned char npu_fw_image_hash_buf[HASH_DER_LEN];
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
 
 
 static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
@@ -87,12 +87,12 @@
 static auth_param_type_desc_t sp_pkg8_hash = AUTH_PARAM_TYPE_DESC(
 		AUTH_PARAM_HASH, SP_PKG8_HASH_OID);
 #endif /* SPD_spmd */
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 static auth_param_type_desc_t npu_fw_cert_pk = AUTH_PARAM_TYPE_DESC(
 		AUTH_PARAM_PUB_KEY, ETHOSN_NPU_FW_CONTENT_CERT_PK_OID);
 static auth_param_type_desc_t npu_fw_image_hash = AUTH_PARAM_TYPE_DESC(
 		AUTH_PARAM_HASH, ETHOSN_NPU_FW_BINARY_OID);
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
 
 /*
  * Trusted key certificate
@@ -662,9 +662,9 @@
 DEFINE_SIP_SP_PKG(8);
 #endif /* SPD_spmd */
 
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 static const auth_img_desc_t npu_fw_key_cert = {
-	.img_id = ARM_ETHOSN_NPU_FW_KEY_CERT_ID,
+	.img_id = ETHOSN_NPU_FW_KEY_CERT_ID,
 	.img_type = IMG_CERT,
 	.parent = &trusted_key_cert,
 	.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -697,7 +697,7 @@
 };
 
 static const auth_img_desc_t npu_fw_content_cert = {
-	.img_id = ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID,
+	.img_id = ETHOSN_NPU_FW_CONTENT_CERT_ID,
 	.img_type = IMG_CERT,
 	.parent = &npu_fw_key_cert,
 	.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -730,7 +730,7 @@
 };
 
 static const auth_img_desc_t npu_fw_image = {
-	.img_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
+	.img_id = ETHOSN_NPU_FW_IMAGE_ID,
 	.img_type = IMG_RAW,
 	.parent = &npu_fw_content_cert,
 	.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
@@ -743,7 +743,7 @@
 		}
 	}
 };
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
 
 
 static const auth_img_desc_t * const cot_desc[] = {
@@ -778,11 +778,11 @@
 	[SP_PKG7_ID]				=	&sp_pkg7,
 	[SP_PKG8_ID]				=       &sp_pkg8,
 #endif
-#if ARM_ETHOSN_NPU_TZMP1
-	[ARM_ETHOSN_NPU_FW_KEY_CERT_ID]		=	&npu_fw_key_cert,
-	[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID]	=	&npu_fw_content_cert,
-	[ARM_ETHOSN_NPU_FW_IMAGE_ID]		=	&npu_fw_image,
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+	[ETHOSN_NPU_FW_KEY_CERT_ID]		=	&npu_fw_key_cert,
+	[ETHOSN_NPU_FW_CONTENT_CERT_ID]		=	&npu_fw_content_cert,
+	[ETHOSN_NPU_FW_IMAGE_ID]		=	&npu_fw_image,
+#endif /* ETHOSN_NPU_TZMP1 */
 };
 
 /* Register the CoT in the authentication module */
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index a4e6407..19091f3 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -43,8 +43,8 @@
 JUNO_TZMP1		:=	0
 $(eval $(call assert_boolean,JUNO_TZMP1))
 ifeq (${JUNO_TZMP1}, 1)
-  ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
-    $(error JUNO_TZMP1 cannot be used together with ARM_ETHOSN_NPU_TZMP1)
+  ifeq (${ETHOSN_NPU_TZMP1},1)
+    $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1)
   else
     $(eval $(call add_define,JUNO_TZMP1))
   endif
@@ -207,6 +207,7 @@
 # Add the HW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
 
+include drivers/arm/ethosn/ethosn_npu.mk
 include plat/arm/board/common/board_common.mk
 include plat/arm/common/arm_common.mk
 include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
index e512192..9a65e7c 100644
--- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
+++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
@@ -223,17 +223,17 @@
 	},
 #endif /* EL3_PAYLOAD_BASE */
 
-# if ARM_ETHOSN_NPU_TZMP1
+# if ETHOSN_NPU_TZMP1
 	{
-		.image_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
+		.image_id = ETHOSN_NPU_FW_IMAGE_ID,
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
 				      VERSION_2, image_info_t, 0),
-		.image_info.image_base = ARM_ETHOSN_NPU_FW_IMAGE_BASE,
-		.image_info.image_max_size = ARM_ETHOSN_NPU_FW_IMAGE_LIMIT -
-			ARM_ETHOSN_NPU_FW_IMAGE_BASE,
+		.image_info.image_base = ETHOSN_NPU_FW_IMAGE_BASE,
+		.image_info.image_max_size = ETHOSN_NPU_FW_IMAGE_LIMIT -
+			ETHOSN_NPU_FW_IMAGE_BASE,
 		.next_handoff_image_id = INVALID_IMAGE_ID,
 	},
-# endif
+#endif /* ETHOSN_NPU_TZMP1 */
 };
 
 REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 647a9d9..4914553 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -114,48 +114,6 @@
   endif
 endif
 
-# Arm(R) Ethos(TM)-N NPU SiP service
-ARM_ETHOSN_NPU_DRIVER			:=	0
-$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
-$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
-
-# Arm(R) Ethos(TM)-N NPU TZMP1
-ARM_ETHOSN_NPU_TZMP1			:=	0
-$(eval $(call assert_boolean,ARM_ETHOSN_NPU_TZMP1))
-$(eval $(call add_define,ARM_ETHOSN_NPU_TZMP1))
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
-  ifeq (${ARM_ETHOSN_NPU_DRIVER},0)
-    $(error ARM_ETHOSN_NPU_TZMP1 is only available if ARM_ETHOSN_NPU_DRIVER=1)
-  endif
-  ifeq (${PLAT},juno)
-    $(eval $(call add_define,JUNO_ETHOSN_TZMP1))
-  else
-    $(error ARM_ETHOSN_NPU_TZMP1 only supported on Juno platform, not ${PLAT})
-  endif
-
-  ifeq (${TRUSTED_BOARD_BOOT},0)
-    # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
-    # tampered with, which is required to protect the confidentiality of protected
-    # inference data.
-    $(error ARM_ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
-  endif
-
-  # We need the FW certificate and key certificate
-  $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
-  $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
-  # Needed for our OIDs to be available in tbbr_cot_bl2.c
-  $(eval $(call add_define, PLAT_DEF_OID))
-  PLAT_INCLUDES	+=	-I${PLAT_DIR}certificate/include
-  PLAT_INCLUDES	+=	-Iinclude/drivers/arm/
-
-  # We need the firmware to be built into the FIP
-  $(eval $(call TOOL_ADD_IMG,ARM_ETHOSN_NPU_FW,--npu-fw))
-
-  # Needed so that UUIDs from the FIP are available in BL2
-  $(eval $(call add_define,PLAT_DEF_FIP_UUID))
-  PLAT_INCLUDES		+=	-I${PLAT_DIR}fip
-endif # ARM_ETHOSN_NPU_TZMP1
-
 # Use an implementation of SHA-256 with a smaller memory footprint but reduced
 # speed.
 $(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
@@ -348,18 +306,18 @@
 				plat/arm/common/arm_topology.c			\
 				plat/common/plat_psci_common.c
 
-ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),)
+ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),)
 ARM_SVC_HANDLER_SRCS :=
 
 ifeq (${ENABLE_PMF},1)
 ARM_SVC_HANDLER_SRCS	+=	lib/pmf/pmf_smc.c
 endif
 
-ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+ifeq (${ETHOSN_NPU_DRIVER},1)
 ARM_SVC_HANDLER_SRCS	+=	plat/arm/common/fconf/fconf_ethosn_getter.c	\
 				drivers/delay_timer/delay_timer.c		\
 				drivers/arm/ethosn/ethosn_smc.c
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
+ifeq (${ETHOSN_NPU_TZMP1},1)
 ARM_SVC_HANDLER_SRCS	+=	drivers/arm/ethosn/ethosn_big_fw.c
 endif
 endif
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index af8a02f..6af23a7 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -34,13 +34,13 @@
 
 #endif /* USE_DEBUGFS */
 
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
 
 	if (ethosn_smc_setup() != 0) {
 		return 1;
 	}
 
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
 
 	return 0;
 }
@@ -81,14 +81,14 @@
 
 #endif /* USE_DEBUGFS */
 
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
 
 	if (is_ethosn_fid(smc_fid)) {
 		return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
 					  handle, flags);
 	}
 
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
 
 	switch (smc_fid) {
 	case ARM_SIP_SVC_EXE_STATE_SWITCH: {
@@ -114,10 +114,10 @@
 		/* PMF calls */
 		call_count += PMF_NUM_SMC_CALLS;
 
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
 		/* ETHOSN calls */
 		call_count += ETHOSN_NUM_SMC_CALLS;
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif          /* ETHOSN_NPU_DRIVER */
 
 		/* State switch call */
 		call_count += 1;
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 743cc90..27acc3a 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -68,9 +68,9 @@
 	[TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG},
 	[NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG},
 	[RMM_IMAGE_ID] = {UUID_REALM_MONITOR_MGMT_FIRMWARE},
-#if ARM_ETHOSN_NPU_TZMP1
-	[ARM_ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+	[ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
+#endif /* ETHOSN_NPU_TZMP1 */
 #endif /* ARM_IO_IN_DTB */
 #if TRUSTED_BOARD_BOOT
 	[TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT},
@@ -91,10 +91,10 @@
 	[SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT},
 	[PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT},
 #endif
-#if ARM_ETHOSN_NPU_TZMP1
-	[ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
-	[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+	[ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
+	[ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
+#endif /* ETHOSN_NPU_TZMP1 */
 #endif /* ARM_IO_IN_DTB */
 #endif /* TRUSTED_BOARD_BOOT */
 };
@@ -198,13 +198,13 @@
 		(uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID],
 		open_fip
 	},
-#if ARM_ETHOSN_NPU_TZMP1
-	[ARM_ETHOSN_NPU_FW_IMAGE_ID] = {
+#if ETHOSN_NPU_TZMP1
+	[ETHOSN_NPU_FW_IMAGE_ID] = {
 		&fip_dev_handle,
-		(uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_IMAGE_ID],
+		(uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_IMAGE_ID],
 		open_fip
 	},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
 #endif /* ARM_IO_IN_DTB */
 #if TRUSTED_BOARD_BOOT
 	[TRUSTED_BOOT_FW_CERT_ID] = {
@@ -285,18 +285,18 @@
 		open_fip
 	},
 #endif
-#if ARM_ETHOSN_NPU_TZMP1
-	[ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {
+#if ETHOSN_NPU_TZMP1
+	[ETHOSN_NPU_FW_KEY_CERT_ID] = {
 		&fip_dev_handle,
-		(uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_KEY_CERT_ID],
+		(uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_KEY_CERT_ID],
 		open_fip
 	},
-	[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
+	[ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
 		&fip_dev_handle,
-		(uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID],
+		(uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_CONTENT_CERT_ID],
 		open_fip
 	},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
 #endif /* ARM_IO_IN_DTB */
 #endif /* TRUSTED_BOARD_BOOT */
 };
@@ -305,11 +305,11 @@
 
 #define FCONF_ARM_IO_UUID_NUM_BASE	U(10)
 
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
 #define FCONF_ARM_IO_UUID_NUM_NPU	U(1)
 #else
 #define FCONF_ARM_IO_UUID_NUM_NPU	U(0)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
 
 #if TRUSTED_BOARD_BOOT
 #define FCONF_ARM_IO_UUID_NUM_TBB	U(12)
@@ -323,11 +323,11 @@
 #define FCONF_ARM_IO_UUID_NUM_SPD	U(0)
 #endif /* TRUSTED_BOARD_BOOT && defined(SPD_spmd) */
 
-#if TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1
+#if TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1
 #define FCONF_ARM_IO_UUID_NUM_NPU_TBB	U(2)
 #else
 #define FCONF_ARM_IO_UUID_NUM_NPU_TBB	U(0)
-#endif /* TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1 */
+#endif /* TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 */
 
 #define FCONF_ARM_IO_UUID_NUMBER	FCONF_ARM_IO_UUID_NUM_BASE + \
 					FCONF_ARM_IO_UUID_NUM_NPU + \
@@ -355,9 +355,9 @@
 	{SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"},
 	{TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"},
 	{NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"},
-#if ARM_ETHOSN_NPU_TZMP1
-	{ARM_ETHOSN_NPU_FW_IMAGE_ID, "arm_ethosn_npu_fw_uuid"},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+	{ETHOSN_NPU_FW_IMAGE_ID, "ethosn_npu_fw_uuid"},
+#endif /* ETHOSN_NPU_TZMP1 */
 #if TRUSTED_BOARD_BOOT
 	{CCA_CONTENT_CERT_ID, "cca_cert_uuid"},
 	{CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"},
@@ -375,10 +375,10 @@
 	{SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"},
 	{PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"},
 #endif
-#if ARM_ETHOSN_NPU_TZMP1
-	{ARM_ETHOSN_NPU_FW_KEY_CERT_ID, "arm_ethosn_npu_fw_key_cert_uuid"},
-	{ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID, "arm_ethosn_npu_fw_content_cert_uuid"},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+	{ETHOSN_NPU_FW_KEY_CERT_ID, "ethosn_npu_fw_key_cert_uuid"},
+	{ETHOSN_NPU_FW_CONTENT_CERT_ID, "ethosn_npu_fw_content_cert_uuid"},
+#endif /* ETHOSN_NPU_TZMP1 */
 #endif /* TRUSTED_BOARD_BOOT */
 };
 
diff --git a/plat/nvidia/tegra/include/lib/profiler.h b/plat/nvidia/tegra/include/lib/profiler.h
index 684c872..a7d5e7b 100644
--- a/plat/nvidia/tegra/include/lib/profiler.h
+++ b/plat/nvidia/tegra/include/lib/profiler.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
diff --git a/plat/nvidia/tegra/lib/debug/profiler.c b/plat/nvidia/tegra/lib/debug/profiler.c
index dd76a4e..b5baf42 100644
--- a/plat/nvidia/tegra/lib/debug/profiler.c
+++ b/plat/nvidia/tegra/lib/debug/profiler.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index c935b7d..5b0a171 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -222,7 +222,7 @@
 static void boot_mmc(enum mmc_device_type mmc_dev_type,
 		     uint16_t boot_interface_instance)
 {
-	int io_result __unused;
+	int io_result __maybe_unused;
 	struct stm32_sdmmc2_params params;
 
 	zeromem(&params, sizeof(struct stm32_sdmmc2_params));
@@ -294,7 +294,7 @@
 #if STM32MP_SPI_NOR
 static void boot_spi_nor(boot_api_context_t *boot_context)
 {
-	int io_result __unused;
+	int io_result __maybe_unused;
 
 	io_result = stm32_qspi_init();
 	assert(io_result == 0);
@@ -313,7 +313,7 @@
 #if STM32MP_RAW_NAND
 static void boot_fmc2_nand(boot_api_context_t *boot_context)
 {
-	int io_result __unused;
+	int io_result __maybe_unused;
 
 	io_result = stm32_fmc2_init();
 	assert(io_result == 0);
@@ -332,7 +332,7 @@
 #if STM32MP_SPI_NAND
 static void boot_spi_nand(boot_api_context_t *boot_context)
 {
-	int io_result __unused;
+	int io_result __maybe_unused;
 
 	io_result = stm32_qspi_init();
 	assert(io_result == 0);
@@ -351,7 +351,7 @@
 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
 static void mmap_io_setup(void)
 {
-	int io_result __unused;
+	int io_result __maybe_unused;
 
 	io_result = register_io_dev_memmap(&memmap_dev_con);
 	assert(io_result == 0);
@@ -364,7 +364,7 @@
 #if STM32MP_UART_PROGRAMMER
 static void stm32cubeprogrammer_uart(void)
 {
-	int ret __unused;
+	int ret __maybe_unused;
 	boot_api_context_t *boot_context =
 		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
 	uintptr_t uart_base;
@@ -378,7 +378,7 @@
 #if STM32MP_USB_PROGRAMMER
 static void stm32cubeprogrammer_usb(void)
 {
-	int ret __unused;
+	int ret __maybe_unused;
 	struct usb_handle *pdev;
 
 	/* Init USB on platform */
@@ -390,10 +390,9 @@
 #endif
 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
 
-
 void stm32mp_io_setup(void)
 {
-	int io_result __unused;
+	int io_result __maybe_unused;
 	boot_api_context_t *boot_context =
 		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
 
@@ -473,7 +472,7 @@
 
 int bl2_plat_handle_pre_image_load(unsigned int image_id)
 {
-	static bool gpt_init_done __unused;
+	static bool gpt_init_done __maybe_unused;
 	uint16_t boot_itf = stm32mp_get_boot_itf_selected();
 
 	switch (boot_itf) {
@@ -516,6 +515,7 @@
 			gpt_init_done = true;
 		} else {
 			bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+
 			assert(bl_mem_params != NULL);
 
 			mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base;
@@ -538,7 +538,14 @@
 
 #if STM32MP_SPI_NOR
 	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+/*
+ * With FWU Multi Bank feature enabled, the selection of
+ * the image to boot will be done by fwu_init calling the
+ * platform hook, plat_fwu_set_images_source.
+ */
+#if !PSA_FWU_SUPPORT
 		image_block_spec.offset = STM32MP_NOR_FIP_OFFSET;
+#endif
 		break;
 #endif
 
@@ -591,7 +598,7 @@
 	return rc;
 }
 
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
 /*
  * In each boot in non-trial mode, we set the BKP register to
  * FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata.
@@ -652,54 +659,108 @@
 {
 	unsigned int i;
 	uint32_t boot_idx;
-	const partition_entry_t *entry;
-	const uuid_t *img_type_uuid, *img_uuid;
+	const partition_entry_t *entry __maybe_unused;
+	const uuid_t *img_type_uuid;
+	const uuid_t *img_uuid __maybe_unused;
 	io_block_spec_t *image_spec;
+	const uint16_t boot_itf = stm32mp_get_boot_itf_selected();
 
 	boot_idx = plat_fwu_get_boot_idx();
 	assert(boot_idx < NR_OF_FW_BANKS);
 
 	for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
 		img_type_uuid = &metadata->img_entry[i].img_type_uuid;
+
+		img_uuid = &metadata->img_entry[i].img_props[boot_idx].img_uuid;
+
 		image_spec = stm32_get_image_spec(img_type_uuid);
 		if (image_spec == NULL) {
 			ERROR("Unable to get image spec for the image in the metadata\n");
 			panic();
 		}
 
-		img_uuid =
-			&metadata->img_entry[i].img_props[boot_idx].img_uuid;
+		switch (boot_itf) {
+#if (STM32MP_SDMMC || STM32MP_EMMC)
+		case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
+		case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
+			entry = get_partition_entry_by_uuid(img_uuid);
+			if (entry == NULL) {
+				ERROR("No partition with the uuid mentioned in metadata\n");
+				panic();
+			}
 
-		entry = get_partition_entry_by_uuid(img_uuid);
-		if (entry == NULL) {
-			ERROR("Unable to find the partition with the uuid mentioned in metadata\n");
+			image_spec->offset = entry->start;
+			image_spec->length = entry->length;
+			break;
+#endif
+#if STM32MP_SPI_NOR
+		case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+			if (guidcmp(img_uuid, &STM32MP_NOR_FIP_A_GUID) == 0) {
+				image_spec->offset = STM32MP_NOR_FIP_A_OFFSET;
+			} else if (guidcmp(img_uuid, &STM32MP_NOR_FIP_B_GUID) == 0) {
+				image_spec->offset = STM32MP_NOR_FIP_B_OFFSET;
+			} else {
+				ERROR("Invalid uuid mentioned in metadata\n");
+				panic();
+			}
+			break;
+#endif
+		default:
 			panic();
+			break;
 		}
-
-		image_spec->offset = entry->start;
-		image_spec->length = entry->length;
 	}
 }
 
 static int plat_set_image_source(unsigned int image_id,
 				 uintptr_t *handle,
-				 uintptr_t *image_spec,
-				 const char *part_name)
+				 uintptr_t *image_spec)
 {
 	struct plat_io_policy *policy;
-	io_block_spec_t *spec;
-	const partition_entry_t *entry = get_partition_entry(part_name);
-
-	if (entry == NULL) {
-		ERROR("Unable to find the %s partition\n", part_name);
-		return -ENOENT;
-	}
+	io_block_spec_t *spec __maybe_unused;
+	const partition_entry_t *entry __maybe_unused;
+	const uint16_t boot_itf = stm32mp_get_boot_itf_selected();
 
 	policy = &policies[image_id];
-
 	spec = (io_block_spec_t *)policy->image_spec;
-	spec->offset = entry->start;
-	spec->length = entry->length;
+
+	switch (boot_itf) {
+#if (STM32MP_SDMMC || STM32MP_EMMC)
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
+		partition_init(GPT_IMAGE_ID);
+
+		if (image_id == FWU_METADATA_IMAGE_ID) {
+			entry = get_partition_entry(METADATA_PART_1);
+		} else {
+			entry = get_partition_entry(METADATA_PART_2);
+		}
+
+		if (entry == NULL) {
+			ERROR("Unable to find a metadata partition\n");
+			return -ENOENT;
+		}
+
+		spec->offset = entry->start;
+		spec->length = entry->length;
+		break;
+#endif
+
+#if STM32MP_SPI_NOR
+	case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
+		if (image_id == FWU_METADATA_IMAGE_ID) {
+			spec->offset = STM32MP_NOR_METADATA1_OFFSET;
+		} else {
+			spec->offset = STM32MP_NOR_METADATA2_OFFSET;
+		}
+
+		spec->length = sizeof(struct fwu_metadata);
+		break;
+#endif
+	default:
+		panic();
+		break;
+	}
 
 	*image_spec = policy->image_spec;
 	*handle = *policy->dev_handle;
@@ -711,20 +772,9 @@
 				       uintptr_t *handle,
 				       uintptr_t *image_spec)
 {
-	char *part_name;
-
 	assert((image_id == FWU_METADATA_IMAGE_ID) ||
 	       (image_id == BKUP_FWU_METADATA_IMAGE_ID));
 
-	partition_init(GPT_IMAGE_ID);
-
-	if (image_id == FWU_METADATA_IMAGE_ID) {
-		part_name = METADATA_PART_1;
-	} else {
-		part_name = METADATA_PART_2;
-	}
-
-	return plat_set_image_source(image_id, handle, image_spec,
-				     part_name);
+	return plat_set_image_source(image_id, handle, image_spec);
 }
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 1a59f0b..5514c09 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,12 +27,12 @@
 };
 #endif
 
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
 static io_block_spec_t metadata_block_spec = {
 	.offset = 0,    /* To be filled at runtime */
 	.length = 0,    /* To be filled at runtime */
 };
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
 
 /* By default, STM32 platforms load images from the FIP */
 struct plat_io_policy policies[MAX_NUMBER_IDS] = {
@@ -58,7 +58,7 @@
 		.check = open_storage
 	},
 #endif
-#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
+#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
 	[FWU_METADATA_IMAGE_ID] = {
 		.dev_handle = &storage_dev_handle,
 		.image_spec = (uintptr_t)&metadata_block_spec,
@@ -71,7 +71,7 @@
 		.img_type_guid = NULL_GUID,
 		.check = open_storage
 	},
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */
+#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
 };
 
 #define DEFAULT_UUID_NUMBER	U(7)
diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h
index 4098386..fa2d20e 100644
--- a/plat/st/stm32mp1/stm32mp1_fip_def.h
+++ b/plat/st/stm32mp1/stm32mp1_fip_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2023, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -128,11 +128,26 @@
  * STM32MP1 RAW partition offset for devices without GPT
  ******************************************************************************/
 #define STM32MP_EMMC_BOOT_FIP_OFFSET	U(0x00040000)
+#if PSA_FWU_SUPPORT
+#define STM32MP_NOR_METADATA1_OFFSET	U(0x00080000)
+#define STM32MP_NOR_METADATA2_OFFSET	U(0x000C0000)
+#define STM32MP_NOR_FIP_A_OFFSET	U(0x00100000)
+#define STM32MP_NOR_FIP_A_GUID		(const struct efi_guid)EFI_GUID(0x4fd84c93,  \
+					0x54ef, 0x463f, 0xa7, 0xef, 0xae, 0x25, 0xff,\
+					0x88, 0x70, 0x87)
+
+#define STM32MP_NOR_FIP_B_OFFSET	U(0x00500000)
+#define STM32MP_NOR_FIP_B_GUID		(const struct efi_guid)EFI_GUID(0x09c54952,  \
+					0xd5bf, 0x45af, 0xac, 0xee, 0x33, 0x53, 0x03,\
+					0x76, 0x6f, 0xb3)
+
+#else /* PSA_FWU_SUPPORT */
 #ifndef STM32MP_NOR_FIP_OFFSET
 #define STM32MP_NOR_FIP_OFFSET		U(0x00080000)
 #endif
 #ifndef STM32MP_NAND_FIP_OFFSET
 #define STM32MP_NAND_FIP_OFFSET		U(0x00200000)
 #endif
+#endif /* PSA_FWU_SUPPORT */
 
 #endif /* STM32MP1_FIP_DEF_H */
diff --git a/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
index 46b5179..fef2116 100644
--- a/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/arm/board/juno/plat_fiptool.mk
@@ -8,8 +8,8 @@
 
 ifeq (${PLAT_DEF_UUID}, yes)
 HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
-HOSTCCFLAGS += -DARM_ETHOSN_NPU_TZMP1
+ifeq (${ETHOSN_NPU_TZMP1},1)
+HOSTCCFLAGS += -DETHOSN_NPU_TZMP1
 endif
 INCLUDE_PATHS += -I./ -I${PLAT_DIR}fip -I../../include/
 OBJECTS += ${PLAT_DIR}fip/plat_def_uuid_config.o