| commit | 50ed13a5ec411b1d7ba7c1c82069c5c907af1008 | [log] [tgz] |
|---|---|---|
| author | Joel Hutton <Joel.Hutton@Arm.com> | Tue Apr 09 14:45:34 2019 +0100 |
| committer | Joel Hutton <Joel.Hutton@arm.com> | Wed Apr 10 10:57:58 2019 +0100 |
| tree | 0a4bdd798e26ca9e54018ce623252bb611ce6536 | |
| parent | ae4bb0d2a2771e558412aa4d42772a10f1bd20b7 [diff] |
Add note about erratum 814220 for A7 On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruction before changing cache. The cache cleaning code happens to already be doing this, so only a comment was added. Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>