diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index 5717516..d88d7b1 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -31,26 +31,26 @@
 					unsigned long long max_addr)
 {
 	/* Physical address can't exceed 48 bits */
-	assert((max_addr & ADDR_MASK_48_TO_63) == 0);
+	assert((max_addr & ADDR_MASK_48_TO_63) == 0U);
 
 	/* 48 bits address */
-	if (max_addr & ADDR_MASK_44_TO_47)
+	if ((max_addr & ADDR_MASK_44_TO_47) != 0U)
 		return TCR_PS_BITS_256TB;
 
 	/* 44 bits address */
-	if (max_addr & ADDR_MASK_42_TO_43)
+	if ((max_addr & ADDR_MASK_42_TO_43) != 0U)
 		return TCR_PS_BITS_16TB;
 
 	/* 42 bits address */
-	if (max_addr & ADDR_MASK_40_TO_41)
+	if ((max_addr & ADDR_MASK_40_TO_41) != 0U)
 		return TCR_PS_BITS_4TB;
 
 	/* 40 bits address */
-	if (max_addr & ADDR_MASK_36_TO_39)
+	if ((max_addr & ADDR_MASK_36_TO_39) != 0U)
 		return TCR_PS_BITS_1TB;
 
 	/* 36 bits address */
-	if (max_addr & ADDR_MASK_32_TO_35)
+	if ((max_addr & ADDR_MASK_32_TO_35) != 0U)
 		return TCR_PS_BITS_64GB;
 
 	return TCR_PS_BITS_4GB;
@@ -78,21 +78,21 @@
 }
 #endif /* ENABLE_ASSERTIONS */
 
-int xlat_arch_current_el(void)
+unsigned int xlat_arch_current_el(void)
 {
-	int el = GET_EL(read_CurrentEl());
+	unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
 
-	assert(el > 0);
+	assert(el > 0U);
 
 	return el;
 }
 
-uint64_t xlat_arch_get_xn_desc(int el)
+uint64_t xlat_arch_get_xn_desc(unsigned int el)
 {
-	if (el == 3) {
+	if (el == 3U) {
 		return UPPER_ATTRS(XN);
 	} else {
-		assert(el == 1);
+		assert(el == 1U);
 		return UPPER_ATTRS(PXN);
 	}
 }
@@ -102,12 +102,12 @@
 	unsigned long long max_pa;
 	uintptr_t max_va;
 	print_mmap();
-	init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
+	init_xlation_table(0U, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
 			   &max_va, &max_pa);
 
-	assert(max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
-	assert(max_pa <= PLAT_PHY_ADDR_SPACE_SIZE - 1);
-	assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= get_max_supported_pa());
+	assert(max_va <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
+	assert(max_pa <= (PLAT_PHY_ADDR_SPACE_SIZE - 1U));
+	assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
 
 	tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
 }
@@ -129,7 +129,7 @@
 		uint32_t sctlr;						\
 									\
 		assert(IS_IN_EL(_el));					\
-		assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0);	\
+		assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0U);	\
 									\
 		/* Set attributes in the right indices of the MAIR */	\
 		mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);	\
@@ -144,16 +144,18 @@
 									\
 		/* Set TCR bits as well. */				\
 		/* Set T0SZ to (64 - width of virtual address space) */	\
-		if (flags & XLAT_TABLE_NC) {				\
+		int t0sz = 64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE);\
+									\
+		if ((flags & XLAT_TABLE_NC) != 0U) {			\
 			/* Inner & outer non-cacheable non-shareable. */\
 			tcr = TCR_SH_NON_SHAREABLE |			\
 				TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC |	\
-				(64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));\
+				(uint64_t) t0sz;			\
 		} else {						\
 			/* Inner & outer WBWA & shareable. */		\
 			tcr = TCR_SH_INNER_SHAREABLE |			\
 				TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA |	\
-				(64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));\
+				(uint64_t) t0sz;			\
 		}							\
 		tcr |= _tcr_extra;					\
 		write_tcr_el##_el(tcr);					\
@@ -172,7 +174,7 @@
 		sctlr = read_sctlr_el##_el();				\
 		sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;			\
 									\
-		if (flags & DISABLE_DCACHE)				\
+		if ((flags & DISABLE_DCACHE) != 0U)			\
 			sctlr &= ~SCTLR_C_BIT;				\
 		else							\
 			sctlr |= SCTLR_C_BIT;				\