tree a73d0036adaeefae97043b7ae28b85de2cc56898
parent 8bb9193926c5aa94398f3310f767050d88451877
author Jit Loon Lim <jit.loon.lim@intel.com> 1684297571 +0800
committer Jit Loon Lim <jit.loon.lim@intel.com> 1688519296 +0800

feat(intel): uart support for Agilex5 SoC FPGA

This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.

	1. Added watchdog support.
	2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9346cfde6e033026e4c1e612250e9521bc6b0d47