tree 568a10c4c8e732fed313c612e275a25d1b8f5b58
parent 462c6c46d72c043716dccf2ee866d81f1988ae01
author Alexei Fedorov <Alexei.Fedorov@arm.com> 1565705873 +0100
committer Alexei Fedorov <Alexei.Fedorov@arm.com> 1566398604 +0100

AArch64: Disable Secure Cycle Counter

This patch fixes an issue when secure world timing information
can be leaked because Secure Cycle Counter is not disabled.
For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD
bit on CPU cold/warm boot.
For the earlier architectures PMCR_EL0 register is saved/restored
on secure world entry/exit from/to Non-secure state, and cycle
counting gets disabled by setting PMCR_EL0.DP bit.
'include\aarch64\arch.h' header file was tided up and new
ARMv8.5-PMU related definitions were added.

Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>