diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index bf78a14..440e6aa 100644
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -35,7 +35,7 @@
 {
 	void *from_bl2;
 
-	from_bl2 = (void *) arg0;
+	from_bl2 = (void *)arg0;
 
 	bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
 
@@ -76,7 +76,7 @@
 
 	/* Enable and initialize the System level generic timer */
 	mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
-			CNTCR_FCREQ(0U) | CNTCR_EN);
+		      CNTCR_FCREQ(0U) | CNTCR_EN);
 }
 
 void bl31_plat_arch_setup(void)
diff --git a/plat/socionext/uniphier/uniphier_gicv3.c b/plat/socionext/uniphier/uniphier_gicv3.c
index 5148e8f..266efe7 100644
--- a/plat/socionext/uniphier/uniphier_gicv3.c
+++ b/plat/socionext/uniphier/uniphier_gicv3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,34 +21,34 @@
 
 	/* SGI0 */
 	INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
-			GIC_INTR_CFG_EDGE),
+		       GIC_INTR_CFG_EDGE),
 	/* SGI6 */
 	INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
-			GIC_INTR_CFG_EDGE),
+		       GIC_INTR_CFG_EDGE),
 
 	/* G1S interrupts */
 
 	/* Timer */
 	INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
-			GIC_INTR_CFG_LEVEL),
+		       GIC_INTR_CFG_LEVEL),
 	/* SGI1 */
 	INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
-			GIC_INTR_CFG_EDGE),
+		       GIC_INTR_CFG_EDGE),
 	/* SGI2 */
 	INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
-			GIC_INTR_CFG_EDGE),
+		       GIC_INTR_CFG_EDGE),
 	/* SGI3 */
 	INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
-			GIC_INTR_CFG_EDGE),
+		       GIC_INTR_CFG_EDGE),
 	/* SGI4 */
 	INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
-			GIC_INTR_CFG_EDGE),
+		       GIC_INTR_CFG_EDGE),
 	/* SGI5 */
 	INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
-			GIC_INTR_CFG_EDGE),
+		       GIC_INTR_CFG_EDGE),
 	/* SGI7 */
 	INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
-			GIC_INTR_CFG_EDGE)
+		       GIC_INTR_CFG_EDGE)
 };
 
 static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c
index 451e84f..b456bc5 100644
--- a/plat/socionext/uniphier/uniphier_io_storage.c
+++ b/plat/socionext/uniphier/uniphier_io_storage.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -331,7 +331,7 @@
 
 	assert(image_id < ARRAY_SIZE(uniphier_io_policies));
 
-	*dev_handle = *(uniphier_io_policies[image_id].dev_handle);
+	*dev_handle = *uniphier_io_policies[image_id].dev_handle;
 	*image_spec = uniphier_io_policies[image_id].image_spec;
 	init_params = uniphier_io_policies[image_id].init_params;
 
diff --git a/plat/socionext/uniphier/uniphier_psci.c b/plat/socionext/uniphier/uniphier_psci.c
index ce11aa7..464252d 100644
--- a/plat/socionext/uniphier/uniphier_psci.c
+++ b/plat/socionext/uniphier/uniphier_psci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,9 +14,9 @@
 #define UNIPHIER_ROM_RSV0		0x59801200
 
 #define UNIPHIER_SLFRSTSEL		0x61843010
-#define   UNIPHIER_SLFRSTSEL_MASK		(0x3 << 0)
+#define   UNIPHIER_SLFRSTSEL_MASK		GENMASK(1, 0)
 #define UNIPHIER_SLFRSTCTL		0x61843014
-#define   UNIPHIER_SLFRSTCTL_RST		(1 << 0)
+#define   UNIPHIER_SLFRSTCTL_RST		BIT(0)
 
 #define MPIDR_AFFINITY_INVALID		((u_register_t)-1)
 
@@ -58,7 +58,7 @@
 					const psci_power_state_t *target_state)
 {
 	/*
-	 * The Boot ROM cannot distinguish warn and cold resets.
+	 * The Boot ROM cannot distinguish warm and cold resets.
 	 * Instead of the CPU reset, fake it.
 	 */
 	uniphier_holding_pen_release = MPIDR_AFFINITY_INVALID;