Merge pull request #410 from soby-mathew/sm/psci_handler_reorg
Reorganise PSCI PM handler setup on ARM Standard platforms
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 1ca3a6c..ef390d4 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -115,51 +115,13 @@
/* Enable the SError interrupt */
msr daifclr, #DAIF_ABT_BIT
- /* ------------------------------------------------
- * Only a single SMC exception from BL2 to ask
- * BL1 to pass EL3 control to BL31 is expected
- * here.
- * It expects X0 with RUN_IMAGE SMC function id
- * X1 with address of a entry_point_info_t structure
- * describing the BL3-1 entrypoint
- * ------------------------------------------------
- */
- mov x19, x0
- mov x20, x1
-
- mrs x0, esr_el3
- ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
- cmp x1, #EC_AARCH64_SMC
- b.ne panic
-
- mov x0, #RUN_IMAGE
- cmp x19, x0
- b.ne panic
-
- mov x0, x20
- bl display_boot_progress
-
- ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
- msr elr_el3, x0
- msr spsr_el3, x1
- ubfx x0, x1, #MODE_EL_SHIFT, #2
- cmp x0, #MODE_EL3
- b.ne panic
-
- bl disable_mmu_icache_el3
- tlbi alle3
+ /* Expect only SMC exceptions */
+ mrs x19, esr_el3
+ ubfx x20, x19, #ESR_EC_SHIFT, #ESR_EC_LENGTH
+ cmp x20, #EC_AARCH64_SMC
+ b.ne unexpected_sync_exception
- ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
- ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
- ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
- ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
- eret
-panic:
- mov x0, #SYNC_EXCEPTION_AARCH64
- bl plat_report_exception
-
- wfi
- b panic
+ b smc_handler64
check_vector_size SynchronousExceptionA64
.align 7
@@ -214,3 +176,48 @@
bl plat_report_exception
b SErrorA32
check_vector_size SErrorA32
+
+
+func smc_handler64
+ /* ---------------------------------------------------------------------
+ * Only a single SMC exception from BL2 to ask BL1 to pass EL3 control
+ * to BL31 is expected here. It expects:
+ * - X0 with RUN_IMAGE SMC function ID;
+ * - X1 with the address of a entry_point_info_t structure describing
+ * the BL31 entrypoint.
+ * ---------------------------------------------------------------------
+ */
+ mov x19, x0
+ mov x20, x1
+
+ mov x0, #RUN_IMAGE
+ cmp x19, x0
+ b.ne unexpected_sync_exception
+
+ mov x0, x20
+ bl display_boot_progress
+
+ ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
+ msr elr_el3, x0
+ msr spsr_el3, x1
+ ubfx x0, x1, #MODE_EL_SHIFT, #2
+ cmp x0, #MODE_EL3
+ b.ne unexpected_sync_exception
+
+ bl disable_mmu_icache_el3
+ tlbi alle3
+
+ bl bl1_plat_prepare_exit
+
+ ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
+ ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
+ ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
+ ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
+ eret
+endfunc smc_handler64
+
+unexpected_sync_exception:
+ mov x0, #SYNC_EXCEPTION_AARCH64
+ bl plat_report_exception
+ wfi
+ b unexpected_sync_exception
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 50d36ea..c369844 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -788,6 +788,17 @@
represents the entry point system state for BL2.
+### Function : bl1_plat_prepare_exit() [optional]
+
+ Argument : void
+ Return : void
+
+This function is called prior to exiting BL1 in response to the `RUN_IMAGE_SMC`
+request raised by BL2. It should be used to perform platform specific clean up
+or bookkeeping operations before transferring control to the next image. This
+function runs with MMU disabled.
+
+
3.2 Boot Loader Stage 2 (BL2)
-----------------------------
diff --git a/include/lib/cassert.h b/include/lib/cassert.h
index 0e5529d..e8089cb 100644
--- a/include/lib/cassert.h
+++ b/include/lib/cassert.h
@@ -34,9 +34,12 @@
/*******************************************************************************
* Macro to flag a compile time assertion. It uses the preprocessor to generate
* an invalid C construct if 'cond' evaluates to false.
- * The following compilation error is triggered if the assertion fails:
+ * The following compilation error is triggered if the assertion fails:
* "error: size of array 'msg' is negative"
+ * The 'unused' attribute ensures that the unused typedef does not emit a
+ * compiler warning.
******************************************************************************/
-#define CASSERT(cond, msg) typedef char msg[(cond) ? 1 : -1]
+#define CASSERT(cond, msg) \
+ typedef char msg[(cond) ? 1 : -1] __attribute__((unused))
#endif /* __CASSERT_H__ */
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 6970aa3..ddf383f 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -35,7 +35,7 @@
#include <console.h>
#include <platform_def.h>
#include <plat_arm.h>
-#include "../../bl1/bl1_private.h"
+#include "../../../bl1/bl1_private.h"
#if USE_COHERENT_MEM
diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S
index 9f4b672..f51d24e 100644
--- a/plat/common/aarch64/platform_helpers.S
+++ b/plat/common/aarch64/platform_helpers.S
@@ -37,6 +37,7 @@
.weak plat_crash_console_putc
.weak plat_reset_handler
.weak plat_disable_acp
+ .weak bl1_plat_prepare_exit
#if !ENABLE_PLAT_COMPAT
.globl platform_get_core_pos
@@ -111,3 +112,12 @@
func plat_disable_acp
ret
endfunc plat_disable_acp
+
+ /* -----------------------------------------------------
+ * void bl1_plat_prepare_exit(void);
+ * Called before exiting BL1. Default: do nothing
+ * -----------------------------------------------------
+ */
+func bl1_plat_prepare_exit
+ ret
+endfunc bl1_plat_prepare_exit