tree 3ba1adb255932b29129ed0bad10dded55cb1deb4
parent b3421ce71e156f6fdf99b1c021c1c08e8ab5defb
author Varun Wadekar <vwadekar@nvidia.com> 1514931018 -0800
committer Varun Wadekar <vwadekar@nvidia.com> 1548953141 -0800

Tegra: fix offset used to dump GICD registers from crash handler

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.

Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>