Merge "docs(changelog): changelog for v2.11 release" into integration
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index eed2c77..85cc612 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -63,8 +63,8 @@
:|G|: `bipinravi-arm`_
:|M|: Joanna Farley <joanna.farley@arm.com>
:|G|: `joannafarley-arm`_
-:|M|: Okash Khawaja <okash@google.com>
-:|G|: `bytefire`_
+:|M|: Jidong Sun <jidong@google.com>
+:|G|: `jidongsun`_
:|M|: Varun Wadekar <vwadekar@nvidia.com>
:|G|: `vwadekar`_
:|M|: Yann Gautier <yann.gautier@st.com>
@@ -1035,7 +1035,7 @@
.. _bijucdas: https://github.com/bijucdas
.. _bipinravi-arm: https://github.com/bipinravi-arm
.. _bryanodonoghue: https://github.com/bryanodonoghue
-.. _bytefire: https://github.com/bytefire
+.. _jidongsun: https://github.com/jidongsun
.. _carlocaione: https://github.com/carlocaione
.. _chandnich: https://github.com/chandnich
.. _ChiaweiW: https://github.com/chiaweiw
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 6ab95f9..2f2116f 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -701,13 +701,6 @@
This option defaults to 0.
-- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot
- backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When
- set to ``1`` then measurements and additional metadata collected during the
- measured boot process are sent to the DICE Protection Environment for storage
- and processing. A certificate chain, which represents the boot state of the
- device, can be queried from the DPE.
-
- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build
options to the compiler. An example usage:
@@ -1257,6 +1250,13 @@
Common build options
~~~~~~~~~~~~~~~~~~~~
+- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot
+ backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When
+ set to ``1`` then measurements and additional metadata collected during the
+ measured boot process are sent to the DICE Protection Environment for storage
+ and processing. A certificate chain, which represents the boot state of the
+ device, can be queried from the DPE.
+
- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust
for Measurement (DRTM). This feature has trust dependency on BL31 for taking
the measurements and recording them as per `PSA DRTM specification`_. For
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index bab1086..43a7d59 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -31,8 +31,8 @@
The following source trees and binaries were used:
-- TF-A [`v2.9-rc0`_]
-- TFTF [`v2.9-rc0`_]
+- `TF-A v2.11-rc0`_
+- `TFTF v2.11-rc0`_
Please see the Runtime Instrumentation :ref:`Testing Methodology
<Runtime Instrumentation Methodology>`
@@ -73,23 +73,23 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- parallel (v2.9)
+ parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 104.58 | 241.20 | 5.26 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 384.24 | 22.50 | 138.76 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 244.56 | 22.18 | 5.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 670.56 | 18.58 | 4.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 809.36 | 269.28 | 4.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 984.96 | 219.70 | 79.62 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-------------------+--------------------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-------------------+--------------------+-------------+
+ | 0 | 0 | 112.98 (-53.44%) | 26.16 (-89.33%) | 5.48 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 0 | 1 | 411.18 | 438.88 (+1572.56%) | 138.54 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 0 | 261.82 (+150.88%) | 474.06 (+1649.30%) | 5.6 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 1 | 714.76 (+86.84%) | 26.44 | 4.48 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 2 | 862.66 | 149.34 (-45.00%) | 4.38 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 3 | 1045.12 | 98.12 (-55.76%) | 79.74 |
+ +---------+------+-------------------+--------------------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
parallel (v2.10)
@@ -111,22 +111,22 @@
+---------+------+-------------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- serial (v2.9)
+ serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 236.56 | 23.24 | 138.18 |
+ | 0 | 0 | 244.42 | 27.42 | 138.12 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 236.86 | 23.28 | 138.10 |
+ | 0 | 1 | 245.02 | 27.34 | 138.08 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 281.04 | 22.80 | 77.24 |
+ | 1 | 0 | 297.66 | 26.2 | 77.68 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 100.28 | 18.52 | 4.54 |
+ | 1 | 1 | 108.02 | 21.94 | 4.52 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 100.12 | 18.78 | 4.50 |
+ | 1 | 2 | 107.48 | 21.88 | 4.46 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 100.36 | 18.94 | 4.44 |
+ | 1 | 3 | 107.52 | 21.86 | 4.46 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
@@ -152,23 +152,23 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
- parallel (v2.9)
+ parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 662.34 | 15.22 | 8.08 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 802.00 | 15.50 | 8.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 385.22 | 15.74 | 7.88 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 106.16 | 16.06 | 7.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 524.38 | 15.64 | 7.34 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 246.00 | 15.78 | 7.72 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-------------------+--------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-------------------+--------+-------------+
+ | 0 | 0 | 704.46 | 19.28 | 7.86 |
+ +---------+------+-------------------+--------+-------------+
+ | 0 | 1 | 853.66 | 18.78 | 7.82 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 0 | 556.52 (+425.51%) | 19.06 | 7.82 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 1 | 113.28 (-70.47%) | 19.28 | 7.48 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 2 | 260.62 (-50.22%) | 19.8 | 7.26 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 3 | 408.16 (+66.94%) | 19.82 | 7.38 |
+ +---------+------+-------------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
parallel (v2.10)
@@ -189,22 +189,22 @@
| 1 | 3 | 244.5 | 20.16 | 7.56 |
+---------+------+-------------------+--------+-------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 99.80 | 15.94 | 5.42 |
+ | 0 | 0 | 106.78 | 19.2 | 5.32 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 99.76 | 15.80 | 5.24 |
+ | 0 | 1 | 107.44 | 19.64 | 5.44 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 278.26 | 16.16 | 4.58 |
+ | 1 | 0 | 295.82 | 19.14 | 4.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 96.88 | 16.00 | 4.52 |
+ | 1 | 1 | 104.34 | 19.18 | 4.28 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 96.80 | 16.12 | 4.54 |
+ | 1 | 2 | 103.96 | 19.34 | 4.4 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 96.88 | 16.12 | 4.54 |
+ | 1 | 3 | 104.32 | 19.18 | 4.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
@@ -231,22 +231,22 @@
``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
core to the deepest power level.
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.9)
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 235.76 | 26.14 | 137.80 |
+ | 0 | 0 | 243.62 | 29.84 | 137.66 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 235.40 | 25.72 | 137.62 |
+ | 0 | 1 | 243.88 | 29.54 | 137.8 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 174.70 | 22.40 | 77.26 |
+ | 1 | 0 | 183.26 | 26.22 | 77.76 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 100.92 | 24.04 | 4.52 |
+ | 1 | 1 | 107.64 | 26.74 | 4.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 100.68 | 22.44 | 4.36 |
+ | 1 | 2 | 107.52 | 25.9 | 4.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 101.36 | 22.70 | 4.52 |
+ | 1 | 3 | 107.74 | 25.8 | 4.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.10)
@@ -272,23 +272,23 @@
``CPU_VERSION`` in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.9)
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.11)
- +-------------+--------+-------------+
- | Cluster | Core | Latency |
- +-------------+--------+-------------+
- | 0 | 0 | 1.48 |
- +-------------+--------+-------------+
- | 0 | 1 | 1.04 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.56 |
- +-------------+--------+-------------+
- | 1 | 1 | 0.92 |
- +-------------+--------+-------------+
- | 1 | 2 | 0.96 |
- +-------------+--------+-------------+
- | 1 | 3 | 0.96 |
- +-------------+--------+-------------+
+ +-------------+--------+--------------+
+ | Cluster | Core | Latency |
+ +-------------+--------+--------------+
+ | 0 | 0 | 1.26 |
+ +-------------+--------+--------------+
+ | 0 | 1 | 0.96 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.54 |
+ +-------------+--------+--------------+
+ | 1 | 1 | 0.94 |
+ +-------------+--------+--------------+
+ | 1 | 2 | 0.92 |
+ +-------------+--------+--------------+
+ | 1 | 3 | 1.02 |
+ +-------------+--------+--------------+
.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.10)
@@ -526,8 +526,9 @@
--------------
-*Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
.. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
-.. _v2.9-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.9-rc0
+.. _TF-A v2.11-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.11-rc0
+.. _TFTF v2.11-rc0: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/?h=v2.11-rc0
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
index fd3c9c9..c1c4dd6 100644
--- a/docs/perf/psci-performance-n1sdp.rst
+++ b/docs/perf/psci-performance-n1sdp.rst
@@ -6,8 +6,8 @@
The following source trees and binaries were used:
-- TF-A [`v2.9-rc0-16-g666aec401`_]
-- TFTF [`v2.9-rc0`_]
+- `TF-A v2.11-rc0`_
+- `TFTF v2.11-rc0`_
- SCP/MCP `Prebuilt Images`_
Please see the Runtime Instrumentation :ref:`Testing Methodology
@@ -92,20 +92,19 @@
``CPU_SUSPEND`` to deepest power level
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- parallel (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.80 | 10.08 | 0.80 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 4.14 | 15.92 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 3.68 | 12.96 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 3.36 | 18.58 | 0.18 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+----------------+--------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+--------+----------------+
+ | 0 | 0 | 3.0 (+41.51%) | 23.14 | 1.2 (+185.71%) |
+ +---------+------+----------------+--------+----------------+
+ | 0 | 0 | 4.6 | 35.86 | 0.3 |
+ +---------+------+----------------+--------+----------------+
+ | 1 | 0 | 3.68 (+33.33%) | 33.36 | 0.3 |
+ +---------+------+----------------+--------+----------------+
+ | 1 | 0 | 3.7 (+40.15%) | 38.1 | 0.28 |
+ +---------+------+----------------+--------+----------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
parallel (v2.10)
@@ -122,19 +121,18 @@
| 1 | 0 | 2.64 | 44.56 (+139.83%) | 0.36 (+100.00%) |
+---------+------+----------------+------------------+-----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.86 | 9.92 | 0.32 |
+ | 0 | 0 | 1.7 | 22.46 | 0.3 |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.70 | 10.48 | 0.36 |
+ | 0 | 0 | 2.28 | 22.5 | 0.3 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.78 | 9.72 | 0.16 |
+ | 1 | 0 | 2.14 | 21.5 | 0.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.94 | 10.44 | 0.16 |
+ | 1 | 0 | 2.24 | 22.66 | 0.3 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
@@ -155,22 +153,19 @@
``CPU_SUSPEND`` to power level 0
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
- parallel (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.11)
- +---------------------------------------------------+
- | test_rt_instr_cpu_susp_parallel |
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 0.88 | 12.32 | 0.26 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.12 | 14.62 | 0.26 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.86 | 14.14 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.92 | 9.44 | 0.18 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+----------------+--------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+--------+-------------+
+ | 0 | 0 | 0.94 (-37.33%) | 30.36 | 0.3 |
+ +---------+------+----------------+--------+-------------+
+ | 0 | 0 | 2.12 | 33.12 | 0.28 |
+ +---------+------+----------------+--------+-------------+
+ | 1 | 0 | 2.08 | 32.56 | 0.3 |
+ +---------+------+----------------+--------+-------------+
+ | 1 | 0 | 2.14 | 21.92 | 0.28 |
+ +---------+------+----------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
parallel (v2.10)
@@ -187,20 +182,18 @@
| 1 | 0 | 2.04 | 23.1 (+144.70%) | 0.24 |
+---------+------+---------------+------------------+----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
- +---------------------------------------------------+
- | test_rt_instr_cpu_susp_serial |
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.52 | 9.40 | 0.30 |
+ | 0 | 0 | 1.64 | 21.88 | 0.34 |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.92 | 9.80 | 0.18 |
+ | 0 | 0 | 2.42 | 21.76 | 0.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 2.20 | 9.60 | 0.14 |
+ | 1 | 0 | 2.02 | 21.14 | 0.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.82 | 9.78 | 0.18 |
+ | 1 | 0 | 2.18 | 22.3 | 0.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
@@ -223,19 +216,19 @@
``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
core to the deepest power level.
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.9)
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.84 | 9.94 | 0.32 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 14.20 | 13.10 | 0.50 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 13.88 | 12.36 | 0.42 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 14.40 | 13.26 | 0.52 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-----------+--------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-----------+--------+----------------+
+ | 0 | 0 | 1.96 | 22.44 | 0.38 |
+ +---------+------+-----------+--------+----------------+
+ | 0 | 0 | 13.76 | 30.34 | 0.26 |
+ +---------+------+-----------+--------+----------------+
+ | 1 | 0 | 13.46 | 28.28 | 0.24 |
+ +---------+------+-----------+--------+----------------+
+ | 1 | 0 | 13.84 | 30.06 | 0.28 (-60.00%) |
+ +---------+------+-----------+--------+----------------+
.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.10)
@@ -254,21 +247,19 @@
``CPU_VERSION`` in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.9)
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.11)
- +------------------------------------+
- | test_rt_instr_psci_version_parallel|
- +-------------+--------+-------------+
- | Cluster | Core | Latency |
- +-------------+--------+-------------+
- | 0 | 0 | 0.08 |
- +-------------+--------+-------------+
- | 0 | 0 | 0.26 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.20 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.26 |
- +-------------+--------+-------------+
+ +-------------+--------+--------------+
+ | Cluster | Core | Latency |
+ +-------------+--------+--------------+
+ | 0 | 0 | 0.12 |
+ +-------------+--------+--------------+
+ | 0 | 0 | 0.24 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.2 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.26 |
+ +-------------+--------+--------------+
.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.10)
@@ -288,10 +279,10 @@
--------------
-*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
-.. _v2.9-rc0-16-g666aec401: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/heads/v2.9-rc0-16-g666aec401
-.. _v2.9-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.9-rc0
+.. _TF-A v2.11-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.11-rc0
+.. _TFTF v2.11-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.11-rc0
.. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
.. _Prebuilt Images: https://downloads.trustedfirmware.org/tf-a/css_scp_2.11.0/n1sdp/release/
.. _N1SDP: https://developer.arm.com/documentation/101489/latest