commit 4f29e6cb9ba8c0f8d154b3abcf5ccb8e23ac9476
author Stephan Gerhold <stephan@gerhold.net> Sat Mar 25 13:28:46 2023 +0100
committer Manish Pandey <manish.pandey2@arm.com> Tue Jun 20 18:52:37 2023 +0200
tree d9f3ab4e447f167039eeb615e166027e06178ea0
parent d0fed05bcf4256f4b66319976688950e48d0da2a

feat(msm8916): add Test Secure Payload (TSP) port

Use the new shared msm8916 setup code to easily allow compiling the
Test Secure Payload (TSP) for the msm8916 platform.

Unlike BL31, TSP only calls msm8916_platform_setup() but not
msm8916_configure() because this is already done in BL31.

Change-Id: I3225ef9e61387d49870e9759ffd5b899a8805961
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

plat/qti/msm8916/include/platform_def.h

diff --git a/plat/qti/msm8916/include/platform_def.h b/plat/qti/msm8916/include/platform_def.h
index 02bfd37..4677f06 100644
--- a/plat/qti/msm8916/include/platform_def.h
+++ b/plat/qti/msm8916/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
+ * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net>
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,8 +45,9 @@
 #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 32)
 
-/* Timer frequency */
+/* Timer */
 #define PLAT_SYSCNT_FREQ		19200000
+#define IRQ_SEC_PHY_TIMER		(16 + 2)	/* PPI #2 */
 
 /*
  * The Qualcomm QGIC2 implementation seems to have PIDR0-4 and PIDR4-7
@@ -55,4 +56,9 @@
  */
 #define GICD_PIDR2_GICV2		U(0xFD8)
 
+/* TSP */
+#define TSP_IRQ_SEC_PHY_TIMER		IRQ_SEC_PHY_TIMER
+#define TSP_SEC_MEM_BASE		BL32_BASE
+#define TSP_SEC_MEM_SIZE		(BL32_LIMIT - BL32_BASE)
+
 #endif /* PLATFORM_DEF_H */