commit 4efede7c8dccd09007ac6f6e5dbf95bca31ce014
author Madhukar Pappireddy <madhukar.pappireddy@arm.com> Wed Dec 18 15:56:27 2019 -0600
committer Madhukar Pappireddy <madhukar.pappireddy@arm.com> Mon Dec 23 11:21:16 2019 -0600
tree 35a44b43b9f5f73e43ec8040107ba63d419dfdf7
parent ce9af961eb8528162b271811174d2dfa26f102a2

Workaround for Hercules erratum 1688305

Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.

Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

lib/cpus/cpu-ops.mk

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 078888e..c9b9b38 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -234,6 +234,10 @@
 # only to revision <= r3p0 of the Cortex A76 cpu.
 ERRATA_A76_1286807	?=0
 
+# Flag to apply erratum 1688305 workaround during reset. This erratum applies
+# to revisions r0p0 - r1p0 of the Hercules cpu.
+ERRATA_HERCULES_1688305	?=0
+
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202	?=1
@@ -467,6 +471,10 @@
 $(eval $(call assert_boolean,ERRATA_A76_1286807))
 $(eval $(call add_define,ERRATA_A76_1286807))
 
+# Process ERRATA_HERCULES_1688305 flag
+$(eval $(call assert_boolean,ERRATA_HERCULES_1688305))
+$(eval $(call add_define,ERRATA_HERCULES_1688305))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))