diff --git a/plat/renesas/rcar/include/plat.ld.S b/plat/renesas/rcar/include/plat.ld.S
deleted file mode 100644
index 7aef324..0000000
--- a/plat/renesas/rcar/include/plat.ld.S
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef RCAR_PLAT_LD_S
-#define RCAR_PLAT_LD_S
-
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <platform_def.h>
-
-MEMORY {
-    SRAM (rwx): ORIGIN = BL31_SRAM_BASE, LENGTH = DEVICE_SRAM_SIZE
-    PRAM (r): ORIGIN = BL31_LIMIT - DEVICE_SRAM_SIZE, LENGTH = DEVICE_SRAM_SIZE
-}
-
-SECTIONS
-{
-	/* SRAM_COPY is in PRAM */
-	. = BL31_LIMIT - DEVICE_SRAM_SIZE;
-	__SRAM_COPY_START__ = .;
-
-	.system_ram : {
-		/* system ram start is in SRAM */
-		__system_ram_start__ = .;
-		*(.system_ram*)
-		*iic_dvfs.o(.rodata)
-	        __system_ram_end__ = .;
-	} >SRAM AT>PRAM
-
-    ASSERT(__BL31_END__ <= BL31_LIMIT - DEVICE_SRAM_SIZE,
-    "BL31 image too large - writing on top of SRAM!")
-
-}
-
-#endif /* RCAR_PLAT_LD_S */
diff --git a/plat/renesas/rcar/include/plat_macros.S b/plat/renesas/rcar/include/plat_macros.S
deleted file mode 100644
index 927cd39..0000000
--- a/plat/renesas/rcar/include/plat_macros.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <drivers/arm/cci.h>
-#include <drivers/arm/gic_common.h>
-#include <drivers/arm/gicv2.h>
-
-#include "rcar_def.h"
-
-.section .rodata.gic_reg_name, "aS"
-gicc_regs:
-	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
-newline:
-	.asciz "\n"
-spacer:
-	.asciz ":\t\t0x"
-
-	/* ---------------------------------------------
-	 * The below macro prints out relevant GIC
-	 * registers whenever an unhandled exception is
-	 * taken in BL3-1.
-	 * Clobbers: x0 - x10, x16, x17, sp
-	 * ---------------------------------------------
-	 */
-	.macro plat_print_gic_regs
-	mov_imm	x17, RCAR_GICC_BASE
-	mov_imm	x16, RCAR_GICD_BASE
-print_gicc_regs:
-	/* gicc base address is now in x17 */
-	adr	x6, gicc_regs	/* Load the gicc reg list to x6 */
-	/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
-	ldr	w8, [x17, #GICC_HPPIR]
-	ldr	w9, [x17, #GICC_AHPPIR]
-	ldr	w10, [x17, #GICC_CTLR]
-	/* Store to the crash buf and print to console */
-	bl	str_in_crash_buf_print
-
-	/* Print the GICD_ISPENDR regs */
-	add	x7, x16, #GICD_ISPENDR
-	adr	x4, gicd_pend_reg
-	bl	asm_print_str
-gicd_ispendr_loop:
-	sub	x4, x7, x16
-	cmp	x4, #0x280
-	b.eq	exit_print_gic_regs
-	bl	asm_print_hex
-	adr	x4, spacer
-	bl	asm_print_str
-	ldr	x4, [x7], #8
-	bl	asm_print_hex
-	adr	x4, newline
-	bl	asm_print_str
-	b	gicd_ispendr_loop
-exit_print_gic_regs:
-	.endm
-
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
-	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
-	/* ------------------------------------------------
-	 * The below macro prints out relevant interconnect
-	 * registers whenever an unhandled exception is
-	 * taken in BL3-1.
-	 * Clobbers: x0 - x9, sp
-	 * ------------------------------------------------
-	 */
-	.macro plat_print_interconnect_regs
-	adr	x6, cci_iface_regs
-	/* Store in x7 the base address of the first interface */
-	mov_imm	x7, (CCI500_BASE + SLAVE_IFACE3_OFFSET)
-	ldr	w8, [x7, #SNOOP_CTRL_REG]
-	/* Store in x7 the base address of the second interface */
-	mov_imm	x7, (CCI500_BASE + SLAVE_IFACE4_OFFSET)
-	ldr	w9, [x7, #SNOOP_CTRL_REG]
-	/* Store to the crash buf and print to console */
-	bl	str_in_crash_buf_print
-	.endm
-
-	.macro plat_crash_print_regs
-	plat_print_gic_regs
-	plat_print_interconnect_regs
-	.endm
diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h
deleted file mode 100644
index 7378714..0000000
--- a/plat/renesas/rcar/include/platform_def.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#ifndef __ASSEMBLER__
-#include <stdlib.h>
-#endif
-
-#include <arch.h>
-
-#include "rcar_def.h"
-
-/*******************************************************************************
- * Platform binary types for linking
- ******************************************************************************/
-#define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH            aarch64
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
- #define FIRMWARE_WELCOME_STR	"Booting Rcar-gen3 Trusted Firmware\n"
-
-/* Size of cacheable stacks */
-#if IMAGE_BL1
-#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE	U(0x1000)
-#else
-#define PLATFORM_STACK_SIZE	U(0x440)
-#endif
-#elif IMAGE_BL2
-#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE	U(0x1000)
-#else
-#define PLATFORM_STACK_SIZE	U(0x400)
-#endif
-#elif IMAGE_BL31
-#define PLATFORM_STACK_SIZE	U(0x400)
-#elif IMAGE_BL32
-#define PLATFORM_STACK_SIZE	U(0x440)
-#endif
-
-#define BL332_IMAGE_ID		(NS_BL2U_IMAGE_ID + 1)
-#define BL333_IMAGE_ID		(NS_BL2U_IMAGE_ID + 2)
-#define BL334_IMAGE_ID		(NS_BL2U_IMAGE_ID + 3)
-#define BL335_IMAGE_ID		(NS_BL2U_IMAGE_ID + 4)
-#define BL336_IMAGE_ID		(NS_BL2U_IMAGE_ID + 5)
-#define BL337_IMAGE_ID		(NS_BL2U_IMAGE_ID + 6)
-#define BL338_IMAGE_ID		(NS_BL2U_IMAGE_ID + 7)
-
-#define BL332_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 8)
-#define BL333_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 9)
-#define BL334_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 10)
-#define BL335_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 11)
-#define BL336_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 12)
-#define BL337_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 13)
-#define BL338_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 14)
-
-#define BL332_CERT_ID		(NS_BL2U_IMAGE_ID + 15)
-#define BL333_CERT_ID		(NS_BL2U_IMAGE_ID + 16)
-#define BL334_CERT_ID		(NS_BL2U_IMAGE_ID + 17)
-#define BL335_CERT_ID		(NS_BL2U_IMAGE_ID + 18)
-#define BL336_CERT_ID		(NS_BL2U_IMAGE_ID + 19)
-#define BL337_CERT_ID		(NS_BL2U_IMAGE_ID + 20)
-#define BL338_CERT_ID		(NS_BL2U_IMAGE_ID + 21)
-
-/* io drivers id */
-#define FLASH_DEV_ID		U(0)
-#define EMMC_DEV_ID		U(1)
-
-/*
- * R-Car H3 Cortex-A57
- * L1:I/48KB(16KBx3way) D/32KB(16KBx2way) L2:2MB(128KBx16way)
- *          Cortex-A53
- * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
- */
-#define PLATFORM_CACHE_LINE_SIZE	64
-#define PLATFORM_CLUSTER_COUNT		U(2)
-#define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
-#define PLATFORM_CLUSTER1_CORE_COUNT	U(4)
-#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
-					 PLATFORM_CLUSTER0_CORE_COUNT)
-#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
-
-#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL2
-#define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CORE_COUNT + \
-					 PLATFORM_CLUSTER_COUNT + 1)
-
-#define PLAT_MAX_RET_STATE		U(1)
-#define PLAT_MAX_OFF_STATE		U(2)
-
-#define MAX_IO_DEVICES			U(3)
-#define MAX_IO_HANDLES			U(4)
-
-/*
- ******************************************************************************
- * BL2 specific defines.
- ******************************************************************************
- * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
- * size plus a little space for growth.
- */
-#define RCAR_SYSRAM_BASE		U(0xE6300000)
-#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
-#define BL2_LIMIT			U(0xE6320000)
-#else
-#define BL2_LIMIT			U(0xE6360000)
-#endif
-
-#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
-#define BL2_BASE			U(0xE6304000)
-#define BL2_IMAGE_LIMIT			U(0xE6318000)
-#elif (RCAR_LSI == RCAR_V3M)
-#define BL2_BASE			U(0xE6344000)
-#define BL2_IMAGE_LIMIT			U(0xE636E800)
-#else
-#define BL2_BASE			U(0xE6304000)
-#define BL2_IMAGE_LIMIT			U(0xE632E800)
-#endif
-#define RCAR_SYSRAM_SIZE		(BL2_BASE - RCAR_SYSRAM_BASE)
-
-/*
- ******************************************************************************
- * BL31 specific defines.
- ******************************************************************************
- * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
- * current BL3-1 debug size plus a little space for growth.
- */
-#define BL31_BASE		(RCAR_TRUSTED_SRAM_BASE)
-#define BL31_LIMIT		(RCAR_TRUSTED_SRAM_BASE + \
-				 RCAR_TRUSTED_SRAM_SIZE)
-#define RCAR_BL31_LOG_BASE	(0x44040000)
-#define RCAR_BL31_SDRAM_BTM	(RCAR_BL31_LOG_BASE + 0x14000)
-#define RCAR_BL31_LOG_SIZE	(RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
-#define BL31_SRAM_BASE		(DEVICE_SRAM_BASE)
-#define BL31_SRAM_LIMIT		(DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
-
-/*******************************************************************************
- * BL32 specific defines.
- ******************************************************************************/
-#ifndef SPD_NONE
-#define BL32_BASE		U(0x44100000)
-#define BL32_LIMIT		(BL32_BASE + U(0x100000))
-#endif
-
-/*******************************************************************************
- * BL33
- ******************************************************************************/
-#define BL33_BASE		DRAM1_NS_BASE
-
-
-/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#if IMAGE_BL1
-#define MAX_XLAT_TABLES		U(2)
-#elif IMAGE_BL2
-#define MAX_XLAT_TABLES		U(5)
-#elif IMAGE_BL31
-#define MAX_XLAT_TABLES		U(4)
-#elif IMAGE_BL32
-#define MAX_XLAT_TABLES		U(3)
-#endif
-
-#if IMAGE_BL2
-#define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 40)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 40)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 32)
-#endif
-
-#define MAX_MMAP_REGIONS	(RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS)
-
-/*******************************************************************************
- * Declarations and constants to access the mailboxes safely. Each mailbox is
- * aligned on the biggest cache line size in the platform. This is known only
- * to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two mailboxes do not sit on the same cache
- * line at any cache level. They could belong to different cpus/clusters &
- * get written while being protected by different locks causing corruption of
- * a valid mailbox address.
- ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT   (6)
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-/*******************************************************************************
- * Size of the per-cpu data in bytes that should be reserved in the generic
- * per-cpu data structure for the RCAR port.
- ******************************************************************************/
-#if !USE_COHERENT_MEM
-#define PLAT_PCPU_DATA_SIZE	(2)
-#endif
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h
deleted file mode 100644
index 6c5b295..0000000
--- a/plat/renesas/rcar/include/rcar_def.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RCAR_DEF_H
-#define RCAR_DEF_H
-
-#include <common/tbbr/tbbr_img_def.h>
-#include <lib/utils_def.h>
-
-#define RCAR_PRIMARY_CPU		0x0
-#define RCAR_TRUSTED_SRAM_BASE		0x44000000
-#define RCAR_TRUSTED_SRAM_SIZE		0x0003E000
-#define RCAR_SHARED_MEM_BASE		(RCAR_TRUSTED_SRAM_BASE + \
-					RCAR_TRUSTED_SRAM_SIZE)
-#define RCAR_SHARED_MEM_SIZE		U(0x00001000)
-#define FLASH0_BASE			U(0x08000000)
-#define FLASH0_SIZE			U(0x04000000)
-#define FLASH_MEMORY_SIZE		U(0x04000000)	/* hyper flash */
-#define FLASH_TRANS_SIZE_UNIT		U(0x00000100)
-#define DEVICE_RCAR_BASE		U(0xE6000000)
-#define DEVICE_RCAR_SIZE		U(0x00300000)
-#define DEVICE_RCAR_BASE2		U(0xE6360000)
-#define DEVICE_RCAR_SIZE2		U(0x19CA0000)
-#define DEVICE_SRAM_BASE		U(0xE6300000)
-#define DEVICE_SRAM_SIZE		U(0x00002000)
-#define DEVICE_SRAM_STACK_BASE		(DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
-#define DEVICE_SRAM_STACK_SIZE		U(0x00001000)
-#define DRAM_LIMIT			ULL(0x0000010000000000)
-#define DRAM1_BASE			U(0x40000000)
-#define DRAM1_SIZE			U(0x80000000)
-#define DRAM1_NS_BASE			(DRAM1_BASE + U(0x10000000))
-#define DRAM1_NS_SIZE			(DRAM1_SIZE - DRAM1_NS_BASE)
-#define DRAM_40BIT_BASE			ULL(0x0400000000)
-#define DRAM_40BIT_SIZE			ULL(0x0400000000)
-#define DRAM_PROTECTED_BASE		ULL(0x43F00000)
-#define DRAM_40BIT_PROTECTED_BASE	ULL(0x0403F00000)
-#define DRAM_PROTECTED_SIZE		ULL(0x03F00000)
-#define RCAR_BL31_CRASH_BASE		U(0x4403F000)
-#define RCAR_BL31_CRASH_SIZE		U(0x00001000)
-/* Entrypoint mailboxes */
-#define MBOX_BASE			RCAR_SHARED_MEM_BASE
-#define MBOX_SIZE			0x200
-/* Base address where parameters to BL31 are stored */
-#define PARAMS_BASE			(MBOX_BASE + MBOX_SIZE)
-#define BOOT_KIND_BASE			(RCAR_SHARED_MEM_BASE + \
-					RCAR_SHARED_MEM_SIZE - 0x100)
-/*
- * The number of regions like RO(code), coherent and data required by
- * different BL stages which need to be mapped in the MMU
- */
-#if USE_COHERENT_MEM
-#define RCAR_BL_REGIONS			(3)
-#else
-#define RCAR_BL_REGIONS			(2)
-#endif
-/*
- * The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[]
- * defined for each BL stage in rcar_common.c.
- */
-#if IMAGE_BL2
-#define RCAR_MMAP_ENTRIES		(9)
-#endif
-#if IMAGE_BL31
-#define RCAR_MMAP_ENTRIES		(9)
-#endif
-#if IMAGE_BL2
-#define REG1_BASE			U(0xE6400000)
-#define REG1_SIZE			U(0x04C00000)
-#define ROM0_BASE			U(0xEB100000)
-#define ROM0_SIZE			U(0x00028000)
-#define REG2_BASE			U(0xEC000000)
-#define REG2_SIZE			U(0x14000000)
-#endif
-/* BL33  */
-#define NS_IMAGE_OFFSET			(DRAM1_BASE + U(0x09000000))
-/* BL31 */
-#define RCAR_DEVICE_BASE		DEVICE_RCAR_BASE
-#define RCAR_DEVICE_SIZE		(0x1A000000)
-#define RCAR_LOG_RES_SIZE		(64)
-#define RCAR_LOG_HEADER_SIZE		(16)
-#define RCAR_LOG_OTHER_SIZE		(RCAR_LOG_HEADER_SIZE + \
-					RCAR_LOG_RES_SIZE)
-#define RCAR_BL31_LOG_MAX		(RCAR_BL31_LOG_SIZE - \
-					RCAR_LOG_OTHER_SIZE)
-#define RCAR_CRASH_STACK		RCAR_BL31_CRASH_BASE
-#define AARCH64_SPACE_BASE		ULL(0x00000000000)
-#define AARCH64_SPACE_SIZE		ULL(0x10000000000)
-/* CCI related constants */
-#define CCI500_BASE				U(0xF1200000)
-#define CCI500_CLUSTER0_SL_IFACE_IX		(2)
-#define CCI500_CLUSTER1_SL_IFACE_IX		(3)
-#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3	(1)
-#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3	(2)
-#define RCAR_CCI_BASE				CCI500_BASE
-/* GIC */
-#define RCAR_GICD_BASE			U(0xF1010000)
-#define RCAR_GICR_BASE			U(0xF1010000)
-#define RCAR_GICC_BASE			U(0xF1020000)
-#define RCAR_GICH_BASE			U(0xF1040000)
-#define RCAR_GICV_BASE			U(0xF1060000)
-#define ARM_IRQ_SEC_PHY_TIMER		U(29)
-#define ARM_IRQ_SEC_SGI_0		U(8)
-#define ARM_IRQ_SEC_SGI_1		U(9)
-#define ARM_IRQ_SEC_SGI_2		U(10)
-#define ARM_IRQ_SEC_SGI_3		U(11)
-#define ARM_IRQ_SEC_SGI_4		U(12)
-#define ARM_IRQ_SEC_SGI_5		U(13)
-#define ARM_IRQ_SEC_SGI_6		U(14)
-#define ARM_IRQ_SEC_SGI_7		U(15)
-#define ARM_IRQ_SEC_RPC			U(70)
-#define ARM_IRQ_SEC_TIMER		U(166)
-#define ARM_IRQ_SEC_TIMER_UP		U(171)
-#define ARM_IRQ_SEC_WDT			U(173)
-#define ARM_IRQ_SEC_CRYPT		U(102)
-#define ARM_IRQ_SEC_CRYPT_SecPKA	U(97)
-#define ARM_IRQ_SEC_CRYPT_PubPKA	U(98)
-/* Timer control */
-#define RCAR_CNTC_BASE		U(0xE6080000)
-/* Reset */
-#define RCAR_CPGWPR		U(0xE6150900)	/* CPG write protect    */
-#define RCAR_MODEMR		U(0xE6160060)	/* Mode pin             */
-#define RCAR_CA57RESCNT		U(0xE6160040)	/* Reset control A57    */
-#define RCAR_CA53RESCNT		U(0xE6160044)	/* Reset control A53    */
-#define RCAR_SRESCR		U(0xE6160110)	/* Soft Power On Reset  */
-#define RCAR_CA53WUPCR		U(0xE6151010)	/* Wake-up control A53  */
-#define RCAR_CA57WUPCR		U(0xE6152010)	/* Wake-up control A57  */
-#define RCAR_CA53PSTR		U(0xE6151040)	/* Power status A53     */
-#define RCAR_CA57PSTR		U(0xE6152040)	/* Power status A57     */
-#define RCAR_CA53CPU0CR		U(0xE6151100)	/* CPU control  A53     */
-#define RCAR_CA57CPU0CR		U(0xE6152100)	/* CPU control  A57     */
-#define RCAR_CA53CPUCMCR	U(0xE6151184)	/* Common power A53     */
-#define RCAR_CA57CPUCMCR	U(0xE6152184)	/* Common power A57     */
-#define RCAR_WUPMSKCA57		U(0xE6180014)	/* Wake-up mask A57     */
-#define RCAR_WUPMSKCA53		U(0xE6180018)	/* Wake-up mask A53     */
-/* SYSC	*/
-#define RCAR_PWRSR3		U(0xE6180140)	/* Power stat A53-SCU   */
-#define RCAR_PWRSR5		U(0xE61801C0)	/* Power stat A57-SCU   */
-#define RCAR_SYSCIER		U(0xE618000C)	/* Interrupt enable     */
-#define RCAR_SYSCIMR		U(0xE6180010)	/* Interrupt mask       */
-#define RCAR_SYSCSR		U(0xE6180000)	/* SYSC status          */
-#define RCAR_PWRONCR3		U(0xE618014C)	/* Power resume A53-SCU */
-#define RCAR_PWRONCR5		U(0xE61801CC)	/* Power resume A57-SCU */
-#define RCAR_PWROFFCR3		U(0xE6180144)	/* Power shutoff A53-SCU */
-#define RCAR_PWROFFCR5		U(0xE61801C4)	/* Power shutoff A57-SCU */
-#define RCAR_PWRER3		U(0xE6180154)	/* shutoff/resume error */
-#define RCAR_PWRER5		U(0xE61801D4)	/* shutoff/resume error */
-#define RCAR_SYSCISR		U(0xE6180004)	/* Interrupt status     */
-#define RCAR_SYSCISCR		U(0xE6180008)	/* Interrupt stat clear */
-/* Product register */
-#define RCAR_PRR			U(0xFFF00044)
-#define RCAR_M3_CUT_VER11		U(0x00000010)	/* M3 Ver.1.1/Ver.1.2 */
-#define RCAR_MAJOR_MASK			U(0x000000F0)
-#define RCAR_MINOR_MASK			U(0x0000000F)
-#define PRR_PRODUCT_SHIFT		U(8)
-#define RCAR_MAJOR_SHIFT		U(4)
-#define RCAR_MINOR_SHIFT		U(0)
-#define RCAR_MAJOR_OFFSET		U(1)
-#define RCAR_M3_MINOR_OFFSET		U(2)
-#define PRR_PRODUCT_H3_CUT10		(PRR_PRODUCT_H3 | U(0x00))	/* 1.0 */
-#define PRR_PRODUCT_H3_CUT11		(PRR_PRODUCT_H3 | U(0x01))	/* 1.1 */
-#define PRR_PRODUCT_H3_CUT20		(PRR_PRODUCT_H3 | U(0x10))	/* 2.0 */
-#define PRR_PRODUCT_M3_CUT10		(PRR_PRODUCT_M3 | U(0x00))	/* 1.0 */
-#define PRR_PRODUCT_M3_CUT11		(PRR_PRODUCT_M3 | U(0x10))
-#define PRR				0xFFF00044U
-#define PRR_PRODUCT_MASK		0x00007F00U
-#define PRR_CUT_MASK			0x000000FFU
-#define PRR_PRODUCT_H3			0x00004F00U	/* R-Car H3 */
-#define PRR_PRODUCT_M3			0x00005200U	/* R-Car M3-W */
-#define PRR_PRODUCT_V3M			0x00005400U	/* R-Car V3M */
-#define PRR_PRODUCT_M3N			0x00005500U	/* R-Car M3-N */
-#define PRR_PRODUCT_V3H			0x00005600U	/* R-Car V3H */
-#define PRR_PRODUCT_E3			0x00005700U	/* R-Car E3 */
-#define PRR_PRODUCT_D3			0x00005800U	/* R-Car D3 */
-#define PRR_PRODUCT_10			0x00U		/* Ver.1.0 */
-#define PRR_PRODUCT_11			0x01U		/* Ver.1.1 */
-#define PRR_PRODUCT_20			0x10U		/* Ver.2.0 */
-#define PRR_PRODUCT_21			0x11U		/* Ver.2.1 */
-#define PRR_PRODUCT_30			0x20U		/* Ver.3.0 */
-#define RCAR_CPU_MASK_CA57		U(0x80000000)
-#define RCAR_CPU_MASK_CA53		U(0x04000000)
-#define RCAR_CPU_HAVE_CA57		U(0x00000000)
-#define RCAR_CPU_HAVE_CA53		U(0x00000000)
-#define RCAR_SSCG_MASK			U(0x1000)	/* MD12 */
-#define RCAR_SSCG_ENABLE		U(0x1000)
-/* MD pin information */
-#define MODEMR_BOOT_CPU_MASK		U(0x000000C0)
-#define MODEMR_BOOT_CPU_CR7		U(0x000000C0)
-#define MODEMR_BOOT_CPU_CA57		U(0x00000000)
-#define MODEMR_BOOT_CPU_CA53		U(0x00000040)
-#define MODEMR_BOOT_DEV_MASK		U(0x0000001E)
-#define MODEMR_BOOT_DEV_HYPERFLASH160	U(0x00000004)
-#define MODEMR_BOOT_DEV_HYPERFLASH80	U(0x00000006)
-#define MODEMR_BOOT_DEV_QSPI_FLASH40	U(0x00000008)
-#define MODEMR_BOOT_DEV_QSPI_FLASH80	U(0x0000000C)
-#define MODEMR_BOOT_DEV_EMMC_25X1	U(0x0000000A)
-#define MODEMR_BOOT_DEV_EMMC_50X8	U(0x0000001A)
-#define MODEMR_BOOT_PLL_MASK		U(0x00006000)
-#define MODEMR_BOOT_PLL_SHIFT		U(13)
-/* Memory mapped Generic timer interfaces */
-#define ARM_SYS_CNTCTL_BASE		RCAR_CNTC_BASE
-/* MODEMR PLL masks and bitfield values */
-#define CHECK_MD13_MD14			U(0x6000)
-#define MD14_MD13_TYPE_0		U(0x0000)	/* MD14=0 MD13=0 */
-#define MD14_MD13_TYPE_1		U(0x2000)	/* MD14=0 MD13=1 */
-#define MD14_MD13_TYPE_2		U(0x4000)	/* MD14=1 MD13=0 */
-#define MD14_MD13_TYPE_3		U(0x6000)	/* MD14=1 MD13=1 */
-/* Frequency of EXTAL(Hz) */
-#define EXTAL_MD14_MD13_TYPE_0		U(8333300)	/* MD14=0 MD13=0 */
-#define EXTAL_MD14_MD13_TYPE_1		U(10000000)	/* MD14=0 MD13=1 */
-#define EXTAL_MD14_MD13_TYPE_2		U(12500000)	/* MD14=1 MD13=0 */
-#define EXTAL_MD14_MD13_TYPE_3		U(16666600)	/* MD14=1 MD13=1 */
-#define EXTAL_SALVATOR_XS		U(8320000)	/* Salvator-XS */
-#define EXTAL_EBISU			U(24000000)	/* Ebisu */
-#define EXTAL_DRAAK			U(24000000)	/* Draak */
-/* CPG write protect registers	*/
-#define CPGWPR_PASSWORD			(0x5A5AFFFFU)
-#define CPGWPCR_PASSWORD		(0xA5A50000U)
-/* CA5x Debug Resource control registers */
-#define CPG_CA57DBGRCR			(CPG_BASE + 0x2180U)
-#define CPG_CA53DBGRCR			(CPG_BASE + 0x1180U)
-#define DBGCPUPREN			((uint32_t)1U << 19U)
-#define CPG_PLL0CR			(CPG_BASE + 0x00D8U)
-#define CPG_PLL2CR			(CPG_BASE + 0x002CU)
-#define CPG_PLL4CR			(CPG_BASE + 0x01F4U)
-#define CPG_CPGWPCR			(CPG_BASE + 0x0904U)
-/* RST Registers */
-#define RST_BASE			(0xE6160000U)
-#define RST_WDTRSTCR			(RST_BASE + 0x0054U)
-#define RST_MODEMR			(RST_BASE + 0x0060U)
-#define WDTRSTCR_PASSWORD		(0xA55A0000U)
-#define WDTRSTCR_RWDT_RSTMSK		((uint32_t)1U << 0U)
-/* MFIS Registers */
-#define MFISWPCNTR_PASSWORD		(0xACCE0000U)
-#define MFISWPCNTR			(0xE6260900U)
-/* IPMMU registers */
-#define IPMMU_MM_BASE			(0xE67B0000U)
-#define IPMMUMM_IMSCTLR			(IPMMU_MM_BASE + 0x0500U)
-#define IPMMUMM_IMAUXCTLR		(IPMMU_MM_BASE + 0x0504U)
-#define IPMMUMM_IMSCTLR_ENABLE		(0xC0000000U)
-#define IPMMUMM_IMAUXCTLR_NMERGE40_BIT	(0x01000000U)
-#define IMSCTLR_DISCACHE		(0xE0000000U)
-#define IPMMU_VP0_BASE			(0xFE990000U)
-#define IPMMUVP0_IMSCTLR		(IPMMU_VP0_BASE + 0x0500U)
-#define IPMMU_VI0_BASE			(0xFEBD0000U)
-#define IPMMUVI0_IMSCTLR		(IPMMU_VI0_BASE + 0x0500U)
-#define IPMMU_VI1_BASE			(0xFEBE0000U)
-#define IPMMUVI1_IMSCTLR		(IPMMU_VI1_BASE + 0x0500U)
-#define IPMMU_PV0_BASE			(0xFD800000U)
-#define IPMMUPV0_IMSCTLR		(IPMMU_PV0_BASE + 0x0500U)
-#define IPMMU_PV1_BASE			(0xFD950000U)
-#define IPMMUPV1_IMSCTLR		(IPMMU_PV1_BASE + 0x0500U)
-#define IPMMU_PV2_BASE			(0xFD960000U)
-#define IPMMUPV2_IMSCTLR		(IPMMU_PV2_BASE + 0x0500U)
-#define IPMMU_PV3_BASE			(0xFD970000U)
-#define IPMMUPV3_IMSCTLR		(IPMMU_PV3_BASE + 0x0500U)
-#define IPMMU_HC_BASE			(0xE6570000U)
-#define IPMMUHC_IMSCTLR			(IPMMU_HC_BASE + 0x0500U)
-#define IPMMU_RT_BASE			(0xFFC80000U)
-#define IPMMURT_IMSCTLR			(IPMMU_RT_BASE + 0x0500U)
-#define IPMMU_MP_BASE			(0xEC670000U)
-#define IPMMUMP_IMSCTLR			(IPMMU_MP_BASE + 0x0500U)
-#define IPMMU_DS0_BASE			(0xE6740000U)
-#define IPMMUDS0_IMSCTLR		(IPMMU_DS0_BASE + 0x0500U)
-#define IPMMU_DS1_BASE			(0xE7740000U)
-#define IPMMUDS1_IMSCTLR		(IPMMU_DS1_BASE + 0x0500U)
-/* ARMREG registers */
-#define P_ARMREG_SEC_CTRL		(0xE62711F0U)
-#define P_ARMREG_SEC_CTRL_PROT		(0x00000001U)
-/* MIDR */
-#define MIDR_CA57			(0x0D07U << MIDR_PN_SHIFT)
-#define MIDR_CA53			(0x0D03U << MIDR_PN_SHIFT)
-/* for SuspendToRAM */
-#define GPIO_BASE			(0xE6050000U)
-#define GPIO_INDT1			(GPIO_BASE + 0x100CU)
-#define GPIO_INDT3			(GPIO_BASE + 0x300CU)
-#define GPIO_INDT6			(GPIO_BASE + 0x540CU)
-#define GPIO_OUTDT1			(GPIO_BASE + 0x1008U)
-#define GPIO_OUTDT3			(GPIO_BASE + 0x3008U)
-#define GPIO_OUTDT6			(GPIO_BASE + 0x5408U)
-#define RCAR_COLD_BOOT			(0x00U)
-#define RCAR_WARM_BOOT			(0x01U)
-#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
-#define KEEP10_MAGIC		(0x55U)
-#endif
-/* lossy registers */
-#define LOSSY_PARAMS_BASE		(0x47FD7000U)
-#define AXI_DCMPAREACRA0		(0xE6784100U)
-#define AXI_DCMPAREACRB0		(0xE6784104U)
-#define LOSSY_ENABLE			(0x80000000U)
-#define LOSSY_DISABLE			(0x00000000U)
-#define LOSSY_FMT_YUVPLANAR		(0x00000000U)
-#define LOSSY_FMT_YUV422INTLV		(0x20000000U)
-#define LOSSY_FMT_ARGB8888		(0x40000000U)
-#define LOSSY_ST_ADDR0			(0x54000000U)
-#define LOSSY_END_ADDR0			(0x57000000U)
-#define LOSSY_FMT0			LOSSY_FMT_YUVPLANAR
-#define LOSSY_ENA_DIS0			LOSSY_ENABLE
-#define LOSSY_ST_ADDR1			0x0U
-#define LOSSY_END_ADDR1			0x0U
-#define LOSSY_FMT1			LOSSY_FMT_ARGB8888
-#define LOSSY_ENA_DIS1			LOSSY_DISABLE
-#define LOSSY_ST_ADDR2			0x0U
-#define LOSSY_END_ADDR2			0x0U
-#define LOSSY_FMT2			LOSSY_FMT_YUV422INTLV
-#define LOSSY_ENA_DIS2			LOSSY_DISABLE
-
-#endif /* RCAR_DEF_H */
diff --git a/plat/renesas/rcar/include/rcar_private.h b/plat/renesas/rcar/include/rcar_private.h
deleted file mode 100644
index 36f4ca5..0000000
--- a/plat/renesas/rcar/include/rcar_private.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RCAR_PRIVATE_H
-#define RCAR_PRIVATE_H
-
-#include <common/bl_common.h>
-#include <lib/bakery_lock.h>
-#include <lib/el3_runtime/cpu_data.h>
-
-#include <platform_def.h>
-
-typedef volatile struct mailbox {
-	unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
-} mailbox_t;
-
-/*
- * This structure represents the superset of information that is passed to
- * BL31 e.g. while passing control to it from BL2 which is bl31_params
- * and bl31_plat_params and its elements
- */
-typedef struct bl2_to_bl31_params_mem {
-	image_info_t bl32_image_info;
-	image_info_t bl33_image_info;
-	entry_point_info_t bl33_ep_info;
-	entry_point_info_t bl32_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-#if USE_COHERENT_MEM
-#define RCAR_INSTANTIATE_LOCK	DEFINE_BAKERY_LOCK(rcar_lock);
-#define rcar_lock_init()	bakery_lock_init(&rcar_lock)
-#define rcar_lock_get()		bakery_lock_get(&rcar_lock)
-#define rcar_lock_release()	bakery_lock_release(&rcar_lock)
-#else
-/*
- * Constants to specify how many bakery locks this platform implements. These
- * are used if the platform chooses not to use coherent memory for bakery lock
- * data structures.
- */
-#define RCAR_MAX_BAKERIES	2
-#define RCAR_PWRC_BAKERY_ID	0
-
-/*
- * Definition of structure which holds platform specific per-cpu data. Currently
- * it holds only the bakery lock information for each cpu. Constants to
- * specify how many bakeries this platform implements and bakery ids are
- * specified in rcar_def.h
- */
-typedef struct rcar_cpu_data {
-	bakery_info_t pcpu_bakery_info[RCAR_MAX_BAKERIES];
-} rcar_cpu_data_t;
-
-#define RCAR_CPU_DATA_LOCK_OFFSET	\
-	__builtin_offsetof(rcar_cpu_data_t, pcpu_bakery_info)
-/*
- * Helper macros for bakery lock api when using the above rcar_cpu_data_t for
- * bakery lock data structures. It assumes that the bakery_info is at the
- * beginning of the platform specific per-cpu data.
- */
-#define rcar_lock_init(_lock_arg)
-
-#define rcar_lock_get(_lock_arg)					\
-	bakery_lock_get(_lock_arg,					\
-		CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
-
-#define rcar_lock_release(_lock_arg)					\
-	bakery_lock_release(_lock_arg,					\
-		CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
-/*
- * Ensure that the size of the RCAR specific per-cpu data structure and the size
- * of the memory allocated in generic per-cpu data for the platform are the same
- */
-CASSERT(sizeof(rcar_cpu_data_t) == PLAT_PCPU_DATA_SIZE,
-	rcar_pcpu_data_size_mismatch);
-#endif
-/*
- * Function and variable prototypes
- */
-void rcar_configure_mmu_el3(unsigned long total_base,
-			    unsigned long total_size,
-			    unsigned long ro_start, unsigned long ro_limit
-#if USE_COHERENT_MEM
-			    , unsigned long coh_start, unsigned long coh_limit
-#endif
-			    );
-
-void rcar_setup_topology(void);
-void rcar_cci_disable(void);
-void rcar_cci_enable(void);
-void rcar_cci_init(void);
-
-void plat_invalidate_icache(void);
-void plat_cci_disable(void);
-void plat_cci_enable(void);
-void plat_cci_init(void);
-
-void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit);
-void cpg_write(uintptr_t regadr, uint32_t regval);
-
-void rcar_console_boot_init(void);
-void rcar_console_boot_end(void);
-void rcar_console_runtime_init(void);
-void rcar_console_runtime_end(void);
-
-#endif /* RCAR_PRIVATE_H */
diff --git a/plat/renesas/rcar/include/rcar_version.h b/plat/renesas/rcar/include/rcar_version.h
deleted file mode 100644
index 67cbd71..0000000
--- a/plat/renesas/rcar/include/rcar_version.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RCAR_VERSION_H
-#define RCAR_VERSION_H
-
-#include <arch_helpers.h>
-
-#define VERSION_OF_RENESAS		"2.0.6"
-#define VERSION_OF_RENESAS_MAXLEN	128
-
-extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
-
-#endif /* RCAR_VERSION_H */
diff --git a/plat/renesas/rcar/include/registers/axi_registers.h b/plat/renesas/rcar/include/registers/axi_registers.h
deleted file mode 100644
index 36cd58b..0000000
--- a/plat/renesas/rcar/include/registers/axi_registers.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef AXI_REGISTERS_H
-#define AXI_REGISTERS_H
-
-/* AXI registers */
-
-/* AXI base address */
-#define	AXI_BASE	(0xE6780000U)
-
-/* address split */
-
-/* AXI address split control 0 */
-#define	AXI_ADSPLCR0	(AXI_BASE + 0x4008U)
-/* AXI address split control 1 */
-#define	AXI_ADSPLCR1	(AXI_BASE + 0x400CU)
-/* AXI address split control 2 */
-#define	AXI_ADSPLCR2	(AXI_BASE + 0x4010U)
-/* AXI address split control 3 */
-#define	AXI_ADSPLCR3	(AXI_BASE + 0x4014U)
-
-/* functional safety */
-
-/* AXI functional safety control */
-#define	AXI_FUSACR	(AXI_BASE + 0x4020U)
-
-/* decompression */
-
-/* AXI decompression area configuration A0 */
-#define	AXI_DCMPAREACRA0	(AXI_BASE + 0x4100U)
-/* AXI decompression area configuration B0 */
-#define	AXI_DCMPAREACRB0	(AXI_BASE + 0x4104U)
-/* AXI decompression area configuration A1 */
-#define	AXI_DCMPAREACRA1	(AXI_BASE + 0x4108U)
-/* AXI decompression area configuration B1 */
-#define	AXI_DCMPAREACRB1	(AXI_BASE + 0x410CU)
-/* AXI decompression area configuration A2 */
-#define	AXI_DCMPAREACRA2	(AXI_BASE + 0x4110U)
-/* AXI decompression area configuration B2 */
-#define	AXI_DCMPAREACRB2	(AXI_BASE + 0x4114U)
-/* AXI decompression area configuration A3 */
-#define	AXI_DCMPAREACRA3	(AXI_BASE + 0x4118U)
-/* AXI decompression area configuration B3 */
-#define	AXI_DCMPAREACRB3	(AXI_BASE + 0x411CU)
-/* AXI decompression area configuration A4 */
-#define	AXI_DCMPAREACRA4	(AXI_BASE + 0x4120U)
-/* AXI decompression area configuration B4 */
-#define	AXI_DCMPAREACRB4	(AXI_BASE + 0x4124U)
-/* AXI decompression area configuration A5 */
-#define	AXI_DCMPAREACRA5	(AXI_BASE + 0x4128U)
-/* AXI decompression area configuration B5 */
-#define	AXI_DCMPAREACRB5	(AXI_BASE + 0x412CU)
-/* AXI decompression area configuration A6 */
-#define	AXI_DCMPAREACRA6	(AXI_BASE + 0x4130U)
-/* AXI decompression area configuration B6 */
-#define	AXI_DCMPAREACRB6	(AXI_BASE + 0x4134U)
-/* AXI decompression area configuration A7 */
-#define	AXI_DCMPAREACRA7	(AXI_BASE + 0x4138U)
-/* AXI decompression area configuration B7 */
-#define	AXI_DCMPAREACRB7	(AXI_BASE + 0x413CU)
-/* AXI decompression area configuration A8 */
-#define	AXI_DCMPAREACRA8	(AXI_BASE + 0x4140U)
-/* AXI decompression area configuration B8 */
-#define	AXI_DCMPAREACRB8	(AXI_BASE + 0x4144U)
-/* AXI decompression area configuration A9 */
-#define	AXI_DCMPAREACRA9	(AXI_BASE + 0x4148U)
-/* AXI decompression area configuration B9 */
-#define	AXI_DCMPAREACRB9	(AXI_BASE + 0x414CU)
-/* AXI decompression area configuration A10 */
-#define	AXI_DCMPAREACRA10	(AXI_BASE + 0x4150U)
-/* AXI decompression area configuration B10 */
-#define	AXI_DCMPAREACRB10	(AXI_BASE + 0x4154U)
-/* AXI decompression area configuration A11 */
-#define	AXI_DCMPAREACRA11	(AXI_BASE + 0x4158U)
-/* AXI decompression area configuration B11 */
-#define	AXI_DCMPAREACRB11	(AXI_BASE + 0x415CU)
-/* AXI decompression area configuration A12 */
-#define	AXI_DCMPAREACRA12	(AXI_BASE + 0x4160U)
-/* AXI decompression area configuration B12 */
-#define	AXI_DCMPAREACRB12	(AXI_BASE + 0x4164U)
-/* AXI decompression area configuration A13 */
-#define	AXI_DCMPAREACRA13	(AXI_BASE + 0x4168U)
-/* AXI decompression area configuration B13 */
-#define	AXI_DCMPAREACRB13	(AXI_BASE + 0x416CU)
-/* AXI decompression area configuration A14 */
-#define	AXI_DCMPAREACRA14	(AXI_BASE + 0x4170U)
-/* AXI decompression area configuration B14 */
-#define	AXI_DCMPAREACRB14	(AXI_BASE + 0x4174U)
-/* AXI decompression area configuration A15 */
-#define	AXI_DCMPAREACRA15	(AXI_BASE + 0x4178U)
-/* AXI decompression area configuration B15 */
-#define	AXI_DCMPAREACRB15	(AXI_BASE + 0x417CU)
-/* AXI decompression shadow area configuration */
-#define	AXI_DCMPSHDWCR	(AXI_BASE + 0x4280U)
-
-/* SDRAM protection */
-
-/* AXI dram protected area division 0 */
-#define	AXI_DPTDIVCR0	(AXI_BASE + 0x4400U)
-/* AXI dram protected area division 1 */
-#define	AXI_DPTDIVCR1	(AXI_BASE + 0x4404U)
-/* AXI dram protected area division 2 */
-#define	AXI_DPTDIVCR2	(AXI_BASE + 0x4408U)
-/* AXI dram protected area division 3 */
-#define	AXI_DPTDIVCR3	(AXI_BASE + 0x440CU)
-/* AXI dram protected area division 4 */
-#define	AXI_DPTDIVCR4	(AXI_BASE + 0x4410U)
-/* AXI dram protected area division 5 */
-#define	AXI_DPTDIVCR5	(AXI_BASE + 0x4414U)
-/* AXI dram protected area division 6 */
-#define	AXI_DPTDIVCR6	(AXI_BASE + 0x4418U)
-/* AXI dram protected area division 7 */
-#define	AXI_DPTDIVCR7	(AXI_BASE + 0x441CU)
-/* AXI dram protected area division 8 */
-#define	AXI_DPTDIVCR8	(AXI_BASE + 0x4420U)
-/* AXI dram protected area division 9 */
-#define	AXI_DPTDIVCR9	(AXI_BASE + 0x4424U)
-/* AXI dram protected area division 10 */
-#define	AXI_DPTDIVCR10	(AXI_BASE + 0x4428U)
-/* AXI dram protected area division 11 */
-#define	AXI_DPTDIVCR11	(AXI_BASE + 0x442CU)
-/* AXI dram protected area division 12 */
-#define	AXI_DPTDIVCR12	(AXI_BASE + 0x4430U)
-/* AXI dram protected area division 13 */
-#define	AXI_DPTDIVCR13	(AXI_BASE + 0x4434U)
-/* AXI dram protected area division 14 */
-#define	AXI_DPTDIVCR14	(AXI_BASE + 0x4438U)
-
-/* AXI dram protected area setting 0 */
-#define	AXI_DPTCR0	(AXI_BASE + 0x4440U)
-/* AXI dram protected area setting 1 */
-#define	AXI_DPTCR1	(AXI_BASE + 0x4444U)
-/* AXI dram protected area setting 2 */
-#define	AXI_DPTCR2	(AXI_BASE + 0x4448U)
-/* AXI dram protected area setting 3 */
-#define	AXI_DPTCR3	(AXI_BASE + 0x444CU)
-/* AXI dram protected area setting 4 */
-#define	AXI_DPTCR4	(AXI_BASE + 0x4450U)
-/* AXI dram protected area setting 5 */
-#define	AXI_DPTCR5	(AXI_BASE + 0x4454U)
-/* AXI dram protected area setting 6 */
-#define	AXI_DPTCR6	(AXI_BASE + 0x4458U)
-/* AXI dram protected area setting 7 */
-#define	AXI_DPTCR7	(AXI_BASE + 0x445CU)
-/* AXI dram protected area setting 8 */
-#define	AXI_DPTCR8	(AXI_BASE + 0x4460U)
-/* AXI dram protected area setting 9 */
-#define	AXI_DPTCR9	(AXI_BASE + 0x4464U)
-/* AXI dram protected area setting 10 */
-#define	AXI_DPTCR10	(AXI_BASE + 0x4468U)
-/* AXI dram protected area setting 11 */
-#define	AXI_DPTCR11	(AXI_BASE + 0x446CU)
-/* AXI dram protected area setting 12 */
-#define	AXI_DPTCR12	(AXI_BASE + 0x4470U)
-/* AXI dram protected area setting 13 */
-#define	AXI_DPTCR13	(AXI_BASE + 0x4474U)
-/* AXI dram protected area setting 14 */
-#define	AXI_DPTCR14	(AXI_BASE + 0x4478U)
-/* AXI dram protected area setting 15 */
-#define	AXI_DPTCR15	(AXI_BASE + 0x447CU)
-
-/* SRAM protection */
-
-/* AXI sram protected area division 0 */
-#define	AXI_SPTDIVCR0	(AXI_BASE + 0x4500U)
-/* AXI sram protected area division 1 */
-#define	AXI_SPTDIVCR1	(AXI_BASE + 0x4504U)
-/* AXI sram protected area division 2 */
-#define	AXI_SPTDIVCR2	(AXI_BASE + 0x4508U)
-/* AXI sram protected area division 3 */
-#define	AXI_SPTDIVCR3	(AXI_BASE + 0x450CU)
-/* AXI sram protected area division 4 */
-#define	AXI_SPTDIVCR4	(AXI_BASE + 0x4510U)
-/* AXI sram protected area division 5 */
-#define	AXI_SPTDIVCR5	(AXI_BASE + 0x4514U)
-/* AXI sram protected area division 6 */
-#define	AXI_SPTDIVCR6	(AXI_BASE + 0x4518U)
-/* AXI sram protected area division 7 */
-#define	AXI_SPTDIVCR7	(AXI_BASE + 0x451CU)
-/* AXI sram protected area division 8 */
-#define	AXI_SPTDIVCR8	(AXI_BASE + 0x4520U)
-/* AXI sram protected area division 9 */
-#define	AXI_SPTDIVCR9	(AXI_BASE + 0x4524U)
-/* AXI sram protected area division 10 */
-#define	AXI_SPTDIVCR10	(AXI_BASE + 0x4528U)
-/* AXI sram protected area division 11 */
-#define	AXI_SPTDIVCR11	(AXI_BASE + 0x452CU)
-/* AXI sram protected area division 12 */
-#define	AXI_SPTDIVCR12	(AXI_BASE + 0x4530U)
-/* AXI sram protected area division 13 */
-#define	AXI_SPTDIVCR13	(AXI_BASE + 0x4534U)
-/* AXI sram protected area division 14 */
-#define	AXI_SPTDIVCR14	(AXI_BASE + 0x4538U)
-
-/* AXI sram protected area setting 0 */
-#define	AXI_SPTCR0	(AXI_BASE + 0x4540U)
-/* AXI sram protected area setting 1 */
-#define	AXI_SPTCR1	(AXI_BASE + 0x4544U)
-/* AXI sram protected area setting 2 */
-#define	AXI_SPTCR2	(AXI_BASE + 0x4548U)
-/* AXI sram protected area setting 3 */
-#define	AXI_SPTCR3	(AXI_BASE + 0x454CU)
-/* AXI sram protected area setting 4 */
-#define	AXI_SPTCR4	(AXI_BASE + 0x4550U)
-/* AXI sram protected area setting 5 */
-#define	AXI_SPTCR5	(AXI_BASE + 0x4554U)
-/* AXI sram protected area setting 6 */
-#define	AXI_SPTCR6	(AXI_BASE + 0x4558U)
-/* AXI sram protected area setting 7 */
-#define	AXI_SPTCR7	(AXI_BASE + 0x455CU)
-/* AXI sram protected area setting 8 */
-#define	AXI_SPTCR8	(AXI_BASE + 0x4560U)
-/* AXI sram protected area setting 9 */
-#define	AXI_SPTCR9	(AXI_BASE + 0x4564U)
-/* AXI sram protected area setting 10 */
-#define	AXI_SPTCR10	(AXI_BASE + 0x4568U)
-/* AXI sram protected area setting 11 */
-#define	AXI_SPTCR11	(AXI_BASE + 0x456CU)
-/* AXI sram protected area setting 12 */
-#define	AXI_SPTCR12	(AXI_BASE + 0x4570U)
-/* AXI sram protected area setting 13 */
-#define	AXI_SPTCR13	(AXI_BASE + 0x4574U)
-/* AXI sram protected area setting 14 */
-#define	AXI_SPTCR14	(AXI_BASE + 0x4578U)
-/* AXI sram protected area setting 15 */
-#define	AXI_SPTCR15	(AXI_BASE + 0x457CU)
-
-/* EDC base address */
-#define	EDC_BASE	(0xFF840000U)
-
-/* EDC edc enable */
-#define	EDC_EDCEN	(EDC_BASE + 0x0010U)
-/* EDC edc status 0 */
-#define	EDC_EDCST0	(EDC_BASE + 0x0020U)
-/* EDC edc status 1 */
-#define	EDC_EDCST1	(EDC_BASE + 0x0024U)
-/* EDC edc interrupt enable 0 */
-#define	EDC_EDCINTEN0	(EDC_BASE + 0x0040U)
-/* EDC edc interrupt enable 1 */
-#define	EDC_EDCINTEN1	(EDC_BASE + 0x0044U)
-
-#endif /* AXI_REGISTERS_H */
diff --git a/plat/renesas/rcar/include/registers/cpg_registers.h b/plat/renesas/rcar/include/registers/cpg_registers.h
deleted file mode 100644
index 0d698d9..0000000
--- a/plat/renesas/rcar/include/registers/cpg_registers.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CPG_REGISTERS_H
-#define CPG_REGISTERS_H
-
-/* CPG base address */
-#define	CPG_BASE	(0xE6150000U)
-
-/* CPG system module stop control 2 */
-#define CPG_SMSTPCR2	(CPG_BASE + 0x0138U)
-/* CPG software reset 2 */
-#define CPG_SRCR2	(CPG_BASE + 0x00B0U)
-/* CPG module stop status 2 */
-#define CPG_MSTPSR2	(CPG_BASE + 0x0040U)
-/* CPG write protect */
-#define CPG_CPGWPR	(CPG_BASE + 0x0900U)
-/* CPG write protect control */
-#define CPG_CPGWPCR	(CPG_BASE + 0x0904U)
-/* CPG system module stop control 9 */
-#define CPG_SMSTPCR9    (CPG_BASE + 0x0994U)
-/* CPG module stop status 9 */
-#define CPG_MSTPSR9     (CPG_BASE + 0x09A4U)
-
-/* CPG (SECURITY) registers */
-
-/* Secure Module Stop Control Register 0 */
-#define	SCMSTPCR0	(CPG_BASE + 0x0B20U)
-/* Secure Module Stop Control Register 1 */
-#define	SCMSTPCR1	(CPG_BASE + 0x0B24U)
-/* Secure Module Stop Control Register 2 */
-#define	SCMSTPCR2	(CPG_BASE + 0x0B28U)
-/* Secure Module Stop Control Register 3 */
-#define	SCMSTPCR3	(CPG_BASE + 0x0B2CU)
-/* Secure Module Stop Control Register 4 */
-#define	SCMSTPCR4	(CPG_BASE + 0x0B30U)
-/* Secure Module Stop Control Register 5 */
-#define	SCMSTPCR5	(CPG_BASE + 0x0B34U)
-/* Secure Module Stop Control Register 6 */
-#define	SCMSTPCR6	(CPG_BASE + 0x0B38U)
-/* Secure Module Stop Control Register 7 */
-#define	SCMSTPCR7	(CPG_BASE + 0x0B3CU)
-/* Secure Module Stop Control Register 8 */
-#define	SCMSTPCR8	(CPG_BASE + 0x0B40U)
-/* Secure Module Stop Control Register 9 */
-#define	SCMSTPCR9	(CPG_BASE + 0x0B44U)
-/* Secure Module Stop Control Register 10 */
-#define	SCMSTPCR10	(CPG_BASE + 0x0B48U)
-/* Secure Module Stop Control Register 11 */
-#define	SCMSTPCR11	(CPG_BASE + 0x0B4CU)
-
-/* CPG (SECURITY) registers */
-
-/* Secure Software Reset Access Enable Control Register 0 */
-#define	SCSRSTECR0	(CPG_BASE + 0x0B80U)
-/* Secure Software Reset Access Enable Control Register 1 */
-#define	SCSRSTECR1	(CPG_BASE + 0x0B84U)
-/* Secure Software Reset Access Enable Control Register 2 */
-#define	SCSRSTECR2	(CPG_BASE + 0x0B88U)
-/* Secure Software Reset Access Enable Control Register 3 */
-#define	SCSRSTECR3	(CPG_BASE + 0x0B8CU)
-/* Secure Software Reset Access Enable Control Register 4 */
-#define	SCSRSTECR4	(CPG_BASE + 0x0B90U)
-/* Secure Software Reset Access Enable Control Register 5 */
-#define	SCSRSTECR5	(CPG_BASE + 0x0B94U)
-/* Secure Software Reset Access Enable Control Register 6 */
-#define	SCSRSTECR6	(CPG_BASE + 0x0B98U)
-/* Secure Software Reset Access Enable Control Register 7 */
-#define	SCSRSTECR7	(CPG_BASE + 0x0B9CU)
-/* Secure Software Reset Access Enable Control Register 8 */
-#define	SCSRSTECR8	(CPG_BASE + 0x0BA0U)
-/* Secure Software Reset Access Enable Control Register 9 */
-#define	SCSRSTECR9	(CPG_BASE + 0x0BA4U)
-/* Secure Software Reset Access Enable Control Register 10 */
-#define	SCSRSTECR10	(CPG_BASE + 0x0BA8U)
-/* Secure Software Reset Access Enable Control Register 11 */
-#define	SCSRSTECR11	(CPG_BASE + 0x0BACU)
-
-/* CPG (REALTIME) registers */
-
-/* Realtime Module Stop Control Register 0 */
-#define	RMSTPCR0	(CPG_BASE + 0x0110U)
-/* Realtime Module Stop Control Register 1 */
-#define	RMSTPCR1	(CPG_BASE + 0x0114U)
-/* Realtime Module Stop Control Register 2 */
-#define	RMSTPCR2	(CPG_BASE + 0x0118U)
-/* Realtime Module Stop Control Register 3 */
-#define	RMSTPCR3	(CPG_BASE + 0x011CU)
-/* Realtime Module Stop Control Register 4 */
-#define	RMSTPCR4	(CPG_BASE + 0x0120U)
-/* Realtime Module Stop Control Register 5 */
-#define	RMSTPCR5	(CPG_BASE + 0x0124U)
-/* Realtime Module Stop Control Register 6 */
-#define	RMSTPCR6	(CPG_BASE + 0x0128U)
-/* Realtime Module Stop Control Register 7 */
-#define	RMSTPCR7	(CPG_BASE + 0x012CU)
-/* Realtime Module Stop Control Register 8 */
-#define	RMSTPCR8	(CPG_BASE + 0x0980U)
-/* Realtime Module Stop Control Register 9 */
-#define	RMSTPCR9	(CPG_BASE + 0x0984U)
-/* Realtime Module Stop Control Register 10 */
-#define	RMSTPCR10	(CPG_BASE + 0x0988U)
-/* Realtime Module Stop Control Register 11 */
-#define	RMSTPCR11	(CPG_BASE + 0x098CU)
-
-/* CPG (SYSTEM) registers */
-
-/* System Module Stop Control Register 0 */
-#define	SMSTPCR0	(CPG_BASE + 0x0130U)
-/* System Module Stop Control Register 1 */
-#define	SMSTPCR1	(CPG_BASE + 0x0134U)
-/* System Module Stop Control Register 2 */
-#define	SMSTPCR2	(CPG_BASE + 0x0138U)
-/* System Module Stop Control Register 3 */
-#define	SMSTPCR3	(CPG_BASE + 0x013CU)
-/* System Module Stop Control Register 4 */
-#define	SMSTPCR4	(CPG_BASE + 0x0140U)
-/* System Module Stop Control Register 5 */
-#define	SMSTPCR5	(CPG_BASE + 0x0144U)
-/* System Module Stop Control Register 6 */
-#define	SMSTPCR6	(CPG_BASE + 0x0148U)
-/* System Module Stop Control Register 7 */
-#define	SMSTPCR7	(CPG_BASE + 0x014CU)
-/* System Module Stop Control Register 8 */
-#define	SMSTPCR8	(CPG_BASE + 0x0990U)
-/* System Module Stop Control Register 9 */
-#define	SMSTPCR9	(CPG_BASE + 0x0994U)
-/* System Module Stop Control Register 10 */
-#define	SMSTPCR10	(CPG_BASE + 0x0998U)
-/* System Module Stop Control Register 11 */
-#define	SMSTPCR11	(CPG_BASE + 0x099CU)
-
-#endif /* CPG_REGISTERS_H */
diff --git a/plat/renesas/rcar/include/registers/lifec_registers.h b/plat/renesas/rcar/include/registers/lifec_registers.h
deleted file mode 100644
index 5f49e52..0000000
--- a/plat/renesas/rcar/include/registers/lifec_registers.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef LIFEC_REGISTERS_H
-#define LIFEC_REGISTERS_H
-
-#define LIFEC_SEC_BASE	(0xE6110000U)
-
-#define SEC_SRC		(LIFEC_SEC_BASE + 0x0008U)
-#define SEC_SEL0	(LIFEC_SEC_BASE + 0x0030U)
-#define SEC_SEL1	(LIFEC_SEC_BASE + 0x0034U)
-#define SEC_SEL2	(LIFEC_SEC_BASE + 0x0038U)
-#define SEC_SEL3	(LIFEC_SEC_BASE + 0x003CU)
-#define SEC_SEL4	(LIFEC_SEC_BASE + 0x0058U)
-#define SEC_SEL5	(LIFEC_SEC_BASE + 0x005CU)
-#define SEC_SEL6	(LIFEC_SEC_BASE + 0x0060U)
-#define SEC_SEL7	(LIFEC_SEC_BASE + 0x0064U)
-#define SEC_SEL8	(LIFEC_SEC_BASE + 0x0068U)
-#define SEC_SEL9	(LIFEC_SEC_BASE + 0x006CU)
-#define SEC_SEL10	(LIFEC_SEC_BASE + 0x0070U)
-#define SEC_SEL11	(LIFEC_SEC_BASE + 0x0074U)
-#define SEC_SEL12	(LIFEC_SEC_BASE + 0x0078U)
-#define SEC_SEL13	(LIFEC_SEC_BASE + 0x007CU)
-#define SEC_SEL14	(LIFEC_SEC_BASE + 0x0080U)
-#define SEC_SEL15	(LIFEC_SEC_BASE + 0x0084U)
-#define SEC_GRP0CR0	(LIFEC_SEC_BASE + 0x0138U)
-#define SEC_GRP1CR0	(LIFEC_SEC_BASE + 0x013CU)
-#define SEC_GRP0CR1	(LIFEC_SEC_BASE + 0x0140U)
-#define SEC_GRP1CR1	(LIFEC_SEC_BASE + 0x0144U)
-#define SEC_GRP0CR2	(LIFEC_SEC_BASE + 0x0148U)
-#define SEC_GRP1CR2	(LIFEC_SEC_BASE + 0x014CU)
-#define SEC_GRP0CR3	(LIFEC_SEC_BASE + 0x0150U)
-#define SEC_GRP1CR3	(LIFEC_SEC_BASE + 0x0154U)
-#define SEC_GRP0COND0	(LIFEC_SEC_BASE + 0x0158U)
-#define SEC_GRP1COND0	(LIFEC_SEC_BASE + 0x015CU)
-#define SEC_GRP0COND1	(LIFEC_SEC_BASE + 0x0160U)
-#define SEC_GRP1COND1	(LIFEC_SEC_BASE + 0x0164U)
-#define SEC_GRP0COND2	(LIFEC_SEC_BASE + 0x0168U)
-#define SEC_GRP1COND2	(LIFEC_SEC_BASE + 0x016CU)
-#define SEC_GRP0COND3	(LIFEC_SEC_BASE + 0x0170U)
-#define SEC_GRP1COND3	(LIFEC_SEC_BASE + 0x0174U)
-#define SEC_GRP0COND4	(LIFEC_SEC_BASE + 0x0178U)
-#define SEC_GRP1COND4	(LIFEC_SEC_BASE + 0x017CU)
-#define SEC_GRP0COND5	(LIFEC_SEC_BASE + 0x0180U)
-#define SEC_GRP1COND5	(LIFEC_SEC_BASE + 0x0184U)
-#define SEC_GRP0COND6	(LIFEC_SEC_BASE + 0x0188U)
-#define SEC_GRP1COND6	(LIFEC_SEC_BASE + 0x018CU)
-#define SEC_GRP0COND7	(LIFEC_SEC_BASE + 0x0190U)
-#define SEC_GRP1COND7	(LIFEC_SEC_BASE + 0x0194U)
-#define SEC_GRP0COND8	(LIFEC_SEC_BASE + 0x0198U)
-#define SEC_GRP1COND8	(LIFEC_SEC_BASE + 0x019CU)
-#define SEC_GRP0COND9	(LIFEC_SEC_BASE + 0x01A0U)
-#define SEC_GRP1COND9	(LIFEC_SEC_BASE + 0x01A4U)
-#define SEC_GRP0COND10	(LIFEC_SEC_BASE + 0x01A8U)
-#define SEC_GRP1COND10	(LIFEC_SEC_BASE + 0x01ACU)
-#define SEC_GRP0COND11	(LIFEC_SEC_BASE + 0x01B0U)
-#define SEC_GRP1COND11	(LIFEC_SEC_BASE + 0x01B4U)
-#define SEC_GRP0COND12	(LIFEC_SEC_BASE + 0x01B8U)
-#define SEC_GRP1COND12	(LIFEC_SEC_BASE + 0x01BCU)
-#define SEC_GRP0COND13	(LIFEC_SEC_BASE + 0x01C0U)
-#define SEC_GRP1COND13	(LIFEC_SEC_BASE + 0x01C4U)
-#define SEC_GRP0COND14	(LIFEC_SEC_BASE + 0x01C8U)
-#define SEC_GRP1COND14	(LIFEC_SEC_BASE + 0x01CCU)
-#define SEC_GRP0COND15	(LIFEC_SEC_BASE + 0x01D0U)
-#define SEC_GRP1COND15	(LIFEC_SEC_BASE + 0x01D4U)
-#define SEC_READONLY0	(LIFEC_SEC_BASE + 0x01D8U)
-#define SEC_READONLY1	(LIFEC_SEC_BASE + 0x01DCU)
-#define SEC_READONLY2	(LIFEC_SEC_BASE + 0x01E0U)
-#define SEC_READONLY3	(LIFEC_SEC_BASE + 0x01E4U)
-#define SEC_READONLY4	(LIFEC_SEC_BASE + 0x01E8U)
-#define SEC_READONLY5	(LIFEC_SEC_BASE + 0x01ECU)
-#define SEC_READONLY6	(LIFEC_SEC_BASE + 0x01F0U)
-#define SEC_READONLY7	(LIFEC_SEC_BASE + 0x01F4U)
-#define SEC_READONLY8	(LIFEC_SEC_BASE + 0x01F8U)
-#define SEC_READONLY9	(LIFEC_SEC_BASE + 0x01FCU)
-#define SEC_READONLY10	(LIFEC_SEC_BASE + 0x0200U)
-#define SEC_READONLY11	(LIFEC_SEC_BASE + 0x0204U)
-#define SEC_READONLY12	(LIFEC_SEC_BASE + 0x0208U)
-#define SEC_READONLY13	(LIFEC_SEC_BASE + 0x020CU)
-#define SEC_READONLY14	(LIFEC_SEC_BASE + 0x0210U)
-#define SEC_READONLY15	(LIFEC_SEC_BASE + 0x0214U)
-
-#define LIFEC_SAFE_BASE	(0xE6120000U)
-#define SAFE_GRP0CR0	(LIFEC_SAFE_BASE + 0x0138U)
-#define SAFE_GRP1CR0	(LIFEC_SAFE_BASE + 0x013CU)
-#define SAFE_GRP0CR1	(LIFEC_SAFE_BASE + 0x0140U)
-#define SAFE_GRP1CR1	(LIFEC_SAFE_BASE + 0x0144U)
-#define SAFE_GRP0CR2	(LIFEC_SAFE_BASE + 0x0148U)
-#define SAFE_GRP1CR2	(LIFEC_SAFE_BASE + 0x014CU)
-#define SAFE_GRP0CR3	(LIFEC_SAFE_BASE + 0x0150U)
-#define SAFE_GRP1CR3	(LIFEC_SAFE_BASE + 0x0154U)
-#define SAFE_GRP0COND0	(LIFEC_SAFE_BASE + 0x0158U)
-#define SAFE_GRP1COND0	(LIFEC_SAFE_BASE + 0x015CU)
-#define SAFE_GRP0COND1	(LIFEC_SAFE_BASE + 0x0160U)
-#define SAFE_GRP1COND1	(LIFEC_SAFE_BASE + 0x0164U)
-#define SAFE_GRP0COND2	(LIFEC_SAFE_BASE + 0x0168U)
-#define SAFE_GRP1COND2	(LIFEC_SAFE_BASE + 0x016CU)
-#define SAFE_GRP0COND3	(LIFEC_SAFE_BASE + 0x0170U)
-#define SAFE_GRP1COND3	(LIFEC_SAFE_BASE + 0x0174U)
-#define SAFE_GRP0COND4	(LIFEC_SAFE_BASE + 0x0178U)
-#define SAFE_GRP1COND4	(LIFEC_SAFE_BASE + 0x017CU)
-#define SAFE_GRP0COND5	(LIFEC_SAFE_BASE + 0x0180U)
-#define SAFE_GRP1COND5	(LIFEC_SAFE_BASE + 0x0184U)
-#define SAFE_GRP0COND6	(LIFEC_SAFE_BASE + 0x0188U)
-#define SAFE_GRP1COND6	(LIFEC_SAFE_BASE + 0x018CU)
-#define SAFE_GRP0COND7	(LIFEC_SAFE_BASE + 0x0190U)
-#define SAFE_GRP1COND7	(LIFEC_SAFE_BASE + 0x0194U)
-#define SAFE_GRP0COND8	(LIFEC_SAFE_BASE + 0x0198U)
-#define SAFE_GRP1COND8	(LIFEC_SAFE_BASE + 0x019CU)
-#define SAFE_GRP0COND9	(LIFEC_SAFE_BASE + 0x01A0U)
-#define SAFE_GRP1COND9	(LIFEC_SAFE_BASE + 0x01A4U)
-#define SAFE_GRP0COND10	(LIFEC_SAFE_BASE + 0x01A8U)
-#define SAFE_GRP1COND10	(LIFEC_SAFE_BASE + 0x01ACU)
-#define SAFE_GRP0COND11	(LIFEC_SAFE_BASE + 0x01B0U)
-#define SAFE_GRP1COND11	(LIFEC_SAFE_BASE + 0x01B4U)
-#define SAFE_GRP0COND12	(LIFEC_SAFE_BASE + 0x01B8U)
-#define SAFE_GRP1COND12	(LIFEC_SAFE_BASE + 0x01BCU)
-#define SAFE_GRP0COND13	(LIFEC_SAFE_BASE + 0x01C0U)
-#define SAFE_GRP1COND13	(LIFEC_SAFE_BASE + 0x01C4U)
-#define SAFE_GRP0COND14	(LIFEC_SAFE_BASE + 0x01C8U)
-#define SAFE_GRP1COND14	(LIFEC_SAFE_BASE + 0x01CCU)
-#define SAFE_GRP0COND15	(LIFEC_SAFE_BASE + 0x01D0U)
-#define SAFE_GRP1COND15	(LIFEC_SAFE_BASE + 0x01D4U)
-#define SAFE_READONLY0	(LIFEC_SAFE_BASE + 0x01D8U)
-#define SAFE_READONLY1	(LIFEC_SAFE_BASE + 0x01DCU)
-#define SAFE_READONLY2	(LIFEC_SAFE_BASE + 0x01E0U)
-#define SAFE_READONLY3	(LIFEC_SAFE_BASE + 0x01E4U)
-#define SAFE_READONLY4	(LIFEC_SAFE_BASE + 0x01E8U)
-#define SAFE_READONLY5	(LIFEC_SAFE_BASE + 0x01ECU)
-#define SAFE_READONLY6	(LIFEC_SAFE_BASE + 0x01F0U)
-#define SAFE_READONLY7	(LIFEC_SAFE_BASE + 0x01F4U)
-#define SAFE_READONLY8	(LIFEC_SAFE_BASE + 0x01F8U)
-#define SAFE_READONLY9	(LIFEC_SAFE_BASE + 0x01FCU)
-#define SAFE_READONLY10	(LIFEC_SAFE_BASE + 0x0200U)
-#define SAFE_READONLY11	(LIFEC_SAFE_BASE + 0x0204U)
-#define SAFE_READONLY12	(LIFEC_SAFE_BASE + 0x0208U)
-#define SAFE_READONLY13	(LIFEC_SAFE_BASE + 0x020CU)
-#define SAFE_READONLY14	(LIFEC_SAFE_BASE + 0x0210U)
-#define SAFE_READONLY15	(LIFEC_SAFE_BASE + 0x0214U)
-
-#endif /* LIFEC_REGISTERS_H */
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 4c41dd3..bdc29fe 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -1,56 +1,10 @@
 #
-# Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-PROGRAMMABLE_RESET_ADDRESS	:= 0
-COLD_BOOT_SINGLE_CPU		:= 1
-ARM_CCI_PRODUCT_ID		:= 500
-TRUSTED_BOARD_BOOT		:= 1
-RESET_TO_BL31			:= 1
-GENERATE_COT			:= 1
-BL2_AT_EL3			:= 1
-ENABLE_SVE_FOR_NS		:= 0
-MULTI_CONSOLE_API		:= 1
-
-CRASH_REPORTING			:= 1
-HANDLE_EA_EL3_FIRST		:= 1
-
-$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
-
-ifeq (${SPD},none)
-  SPD_NONE:=1
-  $(eval $(call add_define,SPD_NONE))
-endif
-
-# LSI setting common define
-RCAR_H3:=0
-RCAR_M3:=1
-RCAR_M3N:=2
-RCAR_E3:=3
-RCAR_H3N:=4
-RCAR_D3:=5
-RCAR_V3M:=6
-RCAR_AUTO:=99
-$(eval $(call add_define,RCAR_H3))
-$(eval $(call add_define,RCAR_M3))
-$(eval $(call add_define,RCAR_M3N))
-$(eval $(call add_define,RCAR_E3))
-$(eval $(call add_define,RCAR_H3N))
-$(eval $(call add_define,RCAR_D3))
-$(eval $(call add_define,RCAR_V3M))
-$(eval $(call add_define,RCAR_AUTO))
-RCAR_CUT_10:=0
-RCAR_CUT_11:=1
-RCAR_CUT_13:=3
-RCAR_CUT_20:=10
-RCAR_CUT_30:=20
-$(eval $(call add_define,RCAR_CUT_10))
-$(eval $(call add_define,RCAR_CUT_11))
-$(eval $(call add_define,RCAR_CUT_13))
-$(eval $(call add_define,RCAR_CUT_20))
-$(eval $(call add_define,RCAR_CUT_30))
+include plat/renesas/common/common.mk
 
 ifndef LSI
   $(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI")
@@ -339,21 +293,12 @@
   endif
 endif
 
-# Enable workarounds for selected Cortex-A53 erratas.
-ERRATA_A53_835769  := 1
-ERRATA_A53_843419  := 1
-ERRATA_A53_855873  := 1
-
-# Enable workarounds for selected Cortex-A57 erratas.
-ERRATA_A57_859972  := 1
-ERRATA_A57_813419  := 1
-
 include drivers/renesas/rcar/ddr/ddr.mk
 include drivers/renesas/rcar/qos/qos.mk
 include drivers/renesas/rcar/pfc/pfc.mk
 include lib/libfdt/libfdt.mk
 
-PLAT_INCLUDES	:=	-Idrivers/renesas/rcar/ddr		\
+PLAT_INCLUDES	+=	-Idrivers/renesas/rcar/ddr		\
 			-Idrivers/renesas/rcar/qos		\
 			-Idrivers/renesas/rcar/iic_dvfs		\
 			-Idrivers/renesas/rcar/board		\
@@ -364,25 +309,12 @@
 			-Idrivers/renesas/rcar/scif		\
 			-Idrivers/renesas/rcar/emmc		\
 			-Idrivers/renesas/rcar/pwrc		\
-			-Idrivers/renesas/rcar/io		\
-			-Iplat/renesas/rcar/include/registers	\
-			-Iplat/renesas/rcar/include		\
-			-Iplat/renesas/rcar
+			-Idrivers/renesas/rcar/io
 
 PLAT_BL_COMMON_SOURCES	:=	drivers/renesas/rcar/iic_dvfs/iic_dvfs.c \
 				plat/renesas/rcar/rcar_common.c
 
-RCAR_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
-				drivers/arm/gic/v2/gicv2_main.c		\
-				drivers/arm/gic/v2/gicv2_helpers.c	\
-				plat/common/plat_gicv2.c
-
-BL2_SOURCES	+=	${RCAR_GIC_SOURCES}				\
-			lib/cpus/aarch64/cortex_a53.S			\
-			lib/cpus/aarch64/cortex_a57.S			\
-			${LIBFDT_SRCS}					\
-			common/desc_image_load.c			\
-			plat/renesas/rcar/aarch64/platform_common.c	\
+BL2_SOURCES	+=	plat/renesas/rcar/aarch64/platform_common.c	\
 			plat/renesas/rcar/aarch64/plat_helpers.S	\
 			plat/renesas/rcar/bl2_interrupt_error.c		\
 			plat/renesas/rcar/bl2_secure_setting.c		\
@@ -393,7 +325,6 @@
 			plat/renesas/rcar/bl2_cpg_init.c		\
 			drivers/renesas/rcar/console/rcar_printf.c	\
 			drivers/renesas/rcar/scif/scif.S		\
-			drivers/renesas/rcar/common.c			\
 			drivers/renesas/rcar/io/io_emmcdrv.c		\
 			drivers/renesas/rcar/io/io_memdrv.c		\
 			drivers/renesas/rcar/io/io_rcar.c		\
@@ -410,14 +341,9 @@
 			drivers/renesas/rcar/emmc/emmc_cmd.c		\
 			drivers/renesas/rcar/watchdog/swdt.c		\
 			drivers/renesas/rcar/rom/rom_api.c		\
-			drivers/renesas/rcar/board/board.c		\
-			drivers/io/io_storage.c
+			drivers/renesas/rcar/board/board.c
 
-BL31_SOURCES	+=	${RCAR_GIC_SOURCES}				\
-			lib/cpus/aarch64/cortex_a53.S			\
-			lib/cpus/aarch64/cortex_a57.S			\
-			plat/common/plat_psci_common.c			\
-			plat/renesas/rcar/plat_topology.c		\
+BL31_SOURCES	+=	plat/renesas/rcar/plat_topology.c		\
 			plat/renesas/rcar/aarch64/plat_helpers.S	\
 			plat/renesas/rcar/aarch64/platform_common.c	\
 			plat/renesas/rcar/bl31_plat_setup.c		\
@@ -426,9 +352,7 @@
 			drivers/renesas/rcar/console/rcar_printf.c	\
 			drivers/renesas/rcar/delay/micro_delay.c	\
 			drivers/renesas/rcar/pwrc/call_sram.S		\
-			drivers/renesas/rcar/pwrc/pwrc.c		\
-			drivers/renesas/rcar/common.c			\
-			drivers/arm/cci/cci.c
+			drivers/renesas/rcar/pwrc/pwrc.c
 
 ifeq (${RCAR_GEN3_ULCB},1)
 BL31_SOURCES		+=	drivers/renesas/rcar/cpld/ulcb_cpld.c