Initialise CPU contexts from entry_point_info
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
* The first uses entry_point_info to initialize the relevant
cpu_context for first entry into a lower exception level on a CPU
* The second populates the EL1 and EL2 system registers as needed
from the cpu_context to ensure correct entry into the lower EL
This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).
In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.
Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
diff --git a/services/std_svc/psci/psci_afflvl_off.c b/services/std_svc/psci/psci_afflvl_off.c
index 21a4d1a..30f2bd1 100644
--- a/services/std_svc/psci/psci_afflvl_off.c
+++ b/services/std_svc/psci/psci_afflvl_off.c
@@ -42,8 +42,8 @@
******************************************************************************/
static int psci_afflvl0_off(unsigned long mpidr, aff_map_node_t *cpu_node)
{
- unsigned int index, plat_state;
- int rc = PSCI_E_SUCCESS;
+ unsigned int plat_state;
+ int rc;
unsigned long sctlr;
assert(cpu_node->level == MPIDR_AFFLVL0);
@@ -67,9 +67,6 @@
return rc;
}
- index = cpu_node->data;
- memset(&psci_ns_entry_info[index], 0, sizeof(psci_ns_entry_info[index]));
-
/*
* Arch. management. Perform the necessary steps to flush all
* cpu caches.
@@ -96,6 +93,7 @@
* Plat. management: Perform platform specific actions to turn this
* cpu off e.g. exit cpu coherency, program the power controller etc.
*/
+ rc = PSCI_E_SUCCESS;
if (psci_plat_pm_ops->affinst_off) {
/* Get the current physical state of this cpu */